ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20

For consistency with other SoCs, modify Tegra20's enum pmux_func to:

* Remove PMUX_FUNC values that aren't real
* Use the same PMUX_FUNC_RSVD[1-4] values, and ensure (RSVD1 & 3)==0;
  this will be assumed by pinmux_set_func() in a future patch.

Unfortunately, PMUX_FUNC_RSVD is still used in the pin macros. Use a
private define inside the driver to prevent this from causing compilaton
errors. This will be cleaned up when the pin tables are re-written in a
later patch in this series.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

arch/arm/cpu/tegra20-common/pinmux.c

@@ -307,7 +307,9 @@ struct tegra_pingroup_desc {
 
 /* A pin group number which is not used */
 #define PIN_RESERVED \
-	PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
+	PIN(NONE, NONE, RSVD, RSVD, RSVD, RSVD, RSVD)
+
+#define PMUX_FUNC_RSVD ((enum pmux_func)-1)
 
 const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
 	PIN(ATA,  NAND,  IDE,    NAND,   GMI,       RSVD,        IDE),

arch/arm/include/asm/arch-tegra20/pinmux.h

@@ -228,21 +228,18 @@ enum pmux_func {
 	PMUX_FUNC_VI_SENSOR_CLK,
 	PMUX_FUNC_XIO,
 
-	/* These don't have a name, but can be used in the table */
-	PMUX_FUNC_RSVD1,
-	PMUX_FUNC_RSVD2,
-	PMUX_FUNC_RSVD3,
-	PMUX_FUNC_RSVD4,
-	PMUX_FUNC_RSVD,	/* Not valid and should not be used */
-
 	PMUX_FUNC_COUNT,
 
-	PMUX_FUNC_NONE = -1,
+	PMUX_FUNC_RSVD1 = 0x8000,
+	PMUX_FUNC_RSVD2 = 0x8001,
+	PMUX_FUNC_RSVD3 = 0x8002,
+	PMUX_FUNC_RSVD4 = 0x8003,
 };
 
 /* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \
-		(func) != PMUX_FUNC_RSVD)
+#define pmux_func_isvalid(func) \
+	((((func) >= 0) && ((func) < PMUX_FUNC_COUNT)) ||\
+	 (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
 
 /* The pullup/pulldown state of a pin group */
 enum pmux_pull {