Merge branch 'master' into hpc2 Conflicts: drivers/cfi_flash.cmaster
roy zang
19 years ago
committed by
Zang Tiefei
commit
6bd87c0aee
@ -0,0 +1,51 @@ |
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#
|
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# (C) Copyright 2006
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
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#
|
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|
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include $(TOPDIR)/config.mk |
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|
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LIB = $(obj)lib$(BOARD).a
|
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|
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COBJS = $(BOARD).o fpga.o nand.o
|
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SOBJS = init.o
|
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|
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
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OBJS := $(addprefix $(obj),$(COBJS))
|
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SOBJS := $(addprefix $(obj),$(SOBJS))
|
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|
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
|
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|
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clean: |
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rm -f $(SOBJS) $(OBJS)
|
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|
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distclean: clean |
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rm -f $(LIB) core *.bak .depend *~
|
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|
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#########################################################################
|
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|
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# defines $(obj).depend target
|
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include $(SRCTREE)/rules.mk |
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|
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sinclude $(obj).depend |
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|
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#########################################################################
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@ -0,0 +1,328 @@ |
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/*
|
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* (C) Copyright 2006 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
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* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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|
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#include <common.h> |
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#include <asm/processor.h> |
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#include <spd_sdram.h> |
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#include <ppc4xx_enet.h> |
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#include <miiphy.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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extern int alpr_fpga_init(void); |
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|
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int board_early_init_f (void) |
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{ |
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/*-------------------------------------------------------------------------
|
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* Initialize EBC CONFIG |
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*-------------------------------------------------------------------------*/ |
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mtebc(xbcfg, EBC_CFG_LE_UNLOCK | |
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EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | |
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EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | |
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EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | |
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); |
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|
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/*--------------------------------------------------------------------
|
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* Setup the interrupt controller polarities, triggers, etc. |
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*-------------------------------------------------------------------*/ |
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mtdcr (uic0sr, 0xffffffff); /* clear all */ |
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mtdcr (uic0er, 0x00000000); /* disable all */ |
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mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ |
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mtdcr (uic0pr, 0xfffffe03); /* per manual */ |
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mtdcr (uic0tr, 0x01c00000); /* per manual */ |
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mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ |
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mtdcr (uic0sr, 0xffffffff); /* clear all */ |
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|
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mtdcr (uic1sr, 0xffffffff); /* clear all */ |
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mtdcr (uic1er, 0x00000000); /* disable all */ |
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mtdcr (uic1cr, 0x00000000); /* all non-critical */ |
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mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ |
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mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ |
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mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ |
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mtdcr (uic1sr, 0xffffffff); /* clear all */ |
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|
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mtdcr (uic2sr, 0xffffffff); /* clear all */ |
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mtdcr (uic2er, 0x00000000); /* disable all */ |
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mtdcr (uic2cr, 0x00000000); /* all non-critical */ |
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mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ |
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mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ |
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mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ |
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mtdcr (uic2sr, 0xffffffff); /* clear all */ |
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|
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mtdcr (uicb0sr, 0xfc000000); /* clear all */ |
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mtdcr (uicb0er, 0x00000000); /* disable all */ |
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mtdcr (uicb0cr, 0x00000000); /* all non-critical */ |
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mtdcr (uicb0pr, 0xfc000000); /* */ |
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mtdcr (uicb0tr, 0x00000000); /* */ |
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mtdcr (uicb0vr, 0x00000001); /* */ |
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|
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/* Setup GPIO/IRQ multiplexing */ |
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mtsdr(sdr_pfc0, 0x01a03e00); |
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|
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return 0; |
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} |
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|
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int last_stage_init(void) |
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{ |
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unsigned short reg; |
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|
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/*
|
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* Configure LED's of both Marvell 88E1111 PHY's |
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* |
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* This has to be done after the 4xx ethernet driver is loaded, |
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* so "last_stage_init()" is the right place. |
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*/ |
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miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®); |
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reg |= 0x0001; |
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miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg); |
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miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®); |
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reg |= 0x0001; |
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miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg); |
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|
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return 0; |
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} |
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|
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static int board_rev(void) |
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{ |
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int rev; |
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u32 pfc0; |
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|
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/* Setup GPIO14 & 15 as GPIO */ |
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mfsdr(sdr_pfc0, pfc0); |
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pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1; |
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mtsdr(sdr_pfc0, pfc0); |
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|
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/* Setup as input */ |
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); |
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); |
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|
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rev = (in32(GPIO0_IR) >> 16) & 0x3; |
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|
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/* Setup GPIO14 & 15 as non GPIO again */ |
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mfsdr(sdr_pfc0, pfc0); |
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pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1); |
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mtsdr(sdr_pfc0, pfc0); |
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|
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return rev; |
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} |
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|
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int checkboard (void) |
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{ |
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char *s = getenv ("serial#"); |
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|
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printf ("Board: ALPR"); |
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if (s != NULL) { |
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puts (", serial# "); |
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puts (s); |
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} |
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printf(" (Rev. %d)\n", board_rev()); |
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|
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return (0); |
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} |
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|
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#if defined(CFG_DRAM_TEST) |
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int testdram (void) |
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{ |
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uint *pstart = (uint *) 0x00000000; |
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uint *pend = (uint *) 0x08000000; |
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uint *p; |
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for (p = pstart; p < pend; p++) |
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*p = 0xaaaaaaaa; |
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|
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for (p = pstart; p < pend; p++) { |
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if (*p != 0xaaaaaaaa) { |
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printf ("SDRAM test fails at: %08x\n", (uint) p); |
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return 1; |
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} |
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} |
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for (p = pstart; p < pend; p++) |
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*p = 0x55555555; |
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for (p = pstart; p < pend; p++) { |
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if (*p != 0x55555555) { |
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printf ("SDRAM test fails at: %08x\n", (uint) p); |
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return 1; |
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} |
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} |
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return 0; |
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} |
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#endif |
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|
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/*************************************************************************
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* pci_pre_init |
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* |
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* This routine is called just prior to registering the hose and gives |
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* the board the opportunity to check things. Returning a value of zero |
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* indicates that things are bad & PCI initialization should be aborted. |
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* |
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* Different boards may wish to customize the pci controller structure |
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* (add regions, override default access routines, etc) or perform |
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* certain pre-initialization actions. |
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* |
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************************************************************************/ |
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) |
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int pci_pre_init(struct pci_controller * hose ) |
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{ |
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unsigned long strap; |
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|
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/*--------------------------------------------------------------------------+
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* The ocotea board is always configured as the host & requires the |
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* PCI arbiter to be enabled. |
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*--------------------------------------------------------------------------*/ |
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mfsdr(sdr_sdstp1, strap); |
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if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ |
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printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); |
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return 0; |
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} |
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|
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/* FPGA Init */ |
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alpr_fpga_init (); |
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return 1; |
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} |
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ |
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|
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/*************************************************************************
|
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* pci_target_init |
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* |
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* The bootstrap configuration provides default settings for the pci |
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* inbound map (PIM). But the bootstrap config choices are limited and |
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* may not be sufficient for a given board. |
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* |
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************************************************************************/ |
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) |
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void pci_target_init(struct pci_controller * hose ) |
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{ |
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/*--------------------------------------------------------------------------+
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* Disable everything |
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*--------------------------------------------------------------------------*/ |
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out32r( PCIX0_PIM0SA, 0 ); /* disable */ |
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out32r( PCIX0_PIM1SA, 0 ); /* disable */ |
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out32r( PCIX0_PIM2SA, 0 ); /* disable */ |
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out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ |
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|
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/*--------------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping |
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* options to not support sizes such as 128/256 MB. |
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*--------------------------------------------------------------------------*/ |
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out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); |
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out32r( PCIX0_PIM0LAH, 0 ); |
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out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); |
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|
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out32r( PCIX0_BAR0, 0 ); |
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|
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/*--------------------------------------------------------------------------+
|
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* Program the board's subsystem id/vendor id |
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*--------------------------------------------------------------------------*/ |
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out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); |
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out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); |
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|
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out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
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} |
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ |
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|
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/*************************************************************************
|
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* is_pci_host |
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* |
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* This routine is called to determine if a pci scan should be |
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* performed. With various hardware environments (especially cPCI and |
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* PPMC) it's insufficient to depend on the state of the arbiter enable |
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* bit in the strap register, or generic host/adapter assumptions. |
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* |
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* Rather than hard-code a bad assumption in the general 440 code, the |
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* 440 pci code requires the board to decide at runtime. |
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* |
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* Return 0 for adapter mode, non-zero for host (monarch) mode. |
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* |
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* |
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************************************************************************/ |
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#if defined(CONFIG_PCI) |
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|
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static void wait_for_pci_ready(void) |
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{ |
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/*
|
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* Configure EREADY as input |
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*/ |
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY); |
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udelay(1000); |
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|
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for (;;) { |
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if (in32(GPIO0_IR) & CFG_GPIO_EREADY) |
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return; |
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} |
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|
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} |
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|
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int is_pci_host(struct pci_controller *hose) |
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{ |
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wait_for_pci_ready(); |
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return 1; /* return 1 for host controller */ |
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} |
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#endif /* defined(CONFIG_PCI) */ |
||||
|
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/*************************************************************************
|
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* pci_master_init |
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* |
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************************************************************************/ |
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#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) |
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void pci_master_init(struct pci_controller *hose) |
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{ |
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/*--------------------------------------------------------------------------+
|
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| PowerPC440 PCI Master configuration. |
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| Map PLB/processor addresses to PCI memory space. |
||||
| PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF |
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| Use byte reversed out routines to handle endianess. |
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| Make this region non-prefetchable. |
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+--------------------------------------------------------------------------*/ |
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out32r( PCIX0_POM0SA, 0 ); /* disable */ |
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out32r( PCIX0_POM1SA, 0 ); /* disable */ |
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out32r( PCIX0_POM2SA, 0 ); /* disable */ |
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|
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out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */ |
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out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */ |
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out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ |
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out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ |
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out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ |
||||
|
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out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ |
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out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */ |
||||
out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ |
||||
out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ |
||||
out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ |
||||
|
||||
#ifdef CONFIG_POST |
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests |
||||
* Called from board_init_f(). |
||||
*/ |
||||
int post_hotkeys_pressed(void) |
||||
{ |
||||
|
||||
return (ctrlc()); |
||||
} |
||||
#endif |
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@ -0,0 +1,44 @@ |
||||
#
|
||||
# (C) Copyright 2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# AMCC 440GX Reference Platform (Ocotea) board
|
||||
#
|
||||
|
||||
#TEXT_BASE = 0xFFFE0000
|
||||
|
||||
ifeq ($(ramsym),1) |
||||
TEXT_BASE = 0x07FD0000
|
||||
else |
||||
TEXT_BASE = 0xFFFC0000
|
||||
endif |
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1) |
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif |
||||
|
||||
ifeq ($(dbcr),1) |
||||
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
|
||||
endif |
||||
@ -0,0 +1,257 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
/*
|
||||
* Altera FPGA configuration support for the ALPR computer from prodrive |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <altera.h> |
||||
#include <ACEX1K.h> |
||||
#include <command.h> |
||||
#include <asm-ppc/processor.h> |
||||
#include <ppc440.h> |
||||
#include "fpga.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#if defined(CONFIG_FPGA) |
||||
|
||||
#ifdef FPGA_DEBUG |
||||
#define PRINTF(fmt,args...) printf (fmt ,##args) |
||||
#else |
||||
#define PRINTF(fmt,args...) |
||||
#endif |
||||
|
||||
static unsigned long regval; |
||||
|
||||
#define SET_GPIO_REG_0(reg, bit) { \ |
||||
regval = in32(reg); \
|
||||
regval &= ~(0x80000000 >> bit); \
|
||||
out32(reg, regval); \
|
||||
} |
||||
|
||||
#define SET_GPIO_REG_1(reg, bit) { \ |
||||
regval = in32(reg); \
|
||||
regval |= (0x80000000 >> bit); \
|
||||
out32(reg, regval); \
|
||||
} |
||||
|
||||
#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit) |
||||
#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit) |
||||
|
||||
#define FPGA_PRG (0x80000000 >> CFG_GPIO_PROG_EN) |
||||
#define FPGA_CONFIG (0x80000000 >> CFG_GPIO_CONFIG) |
||||
#define FPGA_DATA (0x80000000 >> CFG_GPIO_DATA) |
||||
#define FPGA_CLK (0x80000000 >> CFG_GPIO_CLK) |
||||
#define OLD_VAL (FPGA_PRG | FPGA_CONFIG) |
||||
|
||||
#define SET_FPGA(data) out32(GPIO0_OR, data) |
||||
|
||||
#define FPGA_WRITE_1 { \ |
||||
SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \
|
||||
SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ |
||||
|
||||
#define FPGA_WRITE_0 { \ |
||||
SET_FPGA(OLD_VAL | 0 | 0 ); /* set data to 0 */ \
|
||||
SET_FPGA(OLD_VAL | FPGA_CLK | 0 );} /* set data to 1 */ |
||||
|
||||
/* Plattforminitializations */ |
||||
/* Here we have to set the FPGA Chain */ |
||||
/* PROGRAM_PROG_EN = HIGH */ |
||||
/* PROGRAM_SEL_DPR = LOW */ |
||||
int fpga_pre_fn (int cookie) |
||||
{ |
||||
unsigned long reg; |
||||
|
||||
reg = in32(GPIO0_IR); |
||||
/* Enable the FPGA Chain */ |
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_PROG_EN); |
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_PROG_EN); |
||||
SET_GPIO_1(CFG_GPIO_PROG_EN); |
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_SEL_DPR); |
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR); |
||||
SET_GPIO_0((CFG_GPIO_SEL_DPR)); |
||||
|
||||
/* initialize the GPIO Pins */ |
||||
/* output */ |
||||
SET_GPIO_0(CFG_GPIO_CLK); |
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK); |
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CLK); |
||||
|
||||
/* output */ |
||||
SET_GPIO_0(CFG_GPIO_DATA); |
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_DATA); |
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_DATA); |
||||
|
||||
/* First we set STATUS to 0 then as an input */ |
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_STATUS); |
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); |
||||
SET_GPIO_0(CFG_GPIO_STATUS); |
||||
SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_STATUS); |
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); |
||||
|
||||
/* output */ |
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CONFIG); |
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CONFIG); |
||||
SET_GPIO_0(CFG_GPIO_CONFIG); |
||||
|
||||
/* input */ |
||||
SET_GPIO_0(CFG_GPIO_CON_DON); |
||||
SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_CON_DON); |
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CON_DON); |
||||
|
||||
/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ |
||||
SET_GPIO_0(CFG_GPIO_CONFIG); |
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
/* Set the state of CONFIG Pin */ |
||||
int fpga_config_fn (int assert_config, int flush, int cookie) |
||||
{ |
||||
if (assert_config) { |
||||
SET_GPIO_1(CFG_GPIO_CONFIG); |
||||
} else { |
||||
SET_GPIO_0(CFG_GPIO_CONFIG); |
||||
} |
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
/* Returns the state of STATUS Pin */ |
||||
int fpga_status_fn (int cookie) |
||||
{ |
||||
unsigned long reg; |
||||
|
||||
reg = in32(GPIO0_IR); |
||||
if (reg &= (0x80000000 >> CFG_GPIO_STATUS)) { |
||||
PRINTF("STATUS = HIGH\n"); |
||||
return FPGA_FAIL; |
||||
} |
||||
PRINTF("STATUS = LOW\n"); |
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
/* Returns the state of CONF_DONE Pin */ |
||||
int fpga_done_fn (int cookie) |
||||
{ |
||||
unsigned long reg; |
||||
reg = in32(GPIO0_IR); |
||||
if (reg &= (0x80000000 >> CFG_GPIO_CON_DON)) { |
||||
PRINTF("CONF_DON = HIGH\n"); |
||||
return FPGA_FAIL; |
||||
} |
||||
PRINTF("CONF_DON = LOW\n"); |
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
/* writes the complete buffer to the FPGA
|
||||
writing the complete buffer in one function is much faster, |
||||
then calling it for every bit */ |
||||
int fpga_write_fn (void *buf, size_t len, int flush, int cookie) |
||||
{ |
||||
size_t bytecount = 0; |
||||
unsigned char *data = (unsigned char *) buf; |
||||
unsigned char val=0; |
||||
int i; |
||||
int len_40 = len / 40; |
||||
|
||||
while (bytecount < len) { |
||||
val = data[bytecount++]; |
||||
i = 8; |
||||
do { |
||||
if (val & 0x01) { |
||||
FPGA_WRITE_1; |
||||
} else { |
||||
FPGA_WRITE_0; |
||||
} |
||||
val >>= 1; |
||||
i --; |
||||
} while (i > 0); |
||||
|
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
if (bytecount % len_40 == 0) { |
||||
putc ('.'); /* let them know we are alive */ |
||||
#ifdef CFG_FPGA_CHECK_CTRLC |
||||
if (ctrlc ()) |
||||
return FPGA_FAIL; |
||||
#endif |
||||
} |
||||
#endif |
||||
} |
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
/* called, when programming is aborted */ |
||||
int fpga_abort_fn (int cookie) |
||||
{ |
||||
SET_GPIO_1((CFG_GPIO_SEL_DPR)); |
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
/* called, when programming was succesful */ |
||||
int fpga_post_fn (int cookie) |
||||
{ |
||||
return fpga_abort_fn (cookie); |
||||
} |
||||
|
||||
/* Note that these are pointers to code that is in Flash. They will be
|
||||
* relocated at runtime. |
||||
*/ |
||||
Altera_CYC2_Passive_Serial_fns fpga_fns = { |
||||
fpga_pre_fn, |
||||
fpga_config_fn, |
||||
fpga_status_fn, |
||||
fpga_done_fn, |
||||
fpga_write_fn, |
||||
fpga_abort_fn, |
||||
fpga_post_fn |
||||
}; |
||||
|
||||
Altera_desc fpga[CONFIG_FPGA_COUNT] = { |
||||
{Altera_CYC2, |
||||
passive_serial, |
||||
Altera_EP2C35_SIZE, |
||||
(void *) &fpga_fns, |
||||
NULL, |
||||
0} |
||||
}; |
||||
|
||||
/*
|
||||
* Initialize the fpga. Return 1 on success, 0 on failure. |
||||
*/ |
||||
int alpr_fpga_init (void) |
||||
{ |
||||
int i; |
||||
|
||||
PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off); |
||||
fpga_init (gd->reloc_off); |
||||
|
||||
for (i = 0; i < CONFIG_FPGA_COUNT; i++) { |
||||
PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); |
||||
fpga_add (fpga_altera, &fpga[i]); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
#endif |
||||
@ -0,0 +1,103 @@ |
||||
/* |
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <config.h> |
||||
|
||||
/* General */ |
||||
#define TLB_VALID 0x00000200 |
||||
|
||||
/* Supported page sizes */ |
||||
#define SZ_1K 0x00000000 |
||||
#define SZ_4K 0x00000010 |
||||
#define SZ_16K 0x00000020 |
||||
#define SZ_64K 0x00000030 |
||||
#define SZ_256K 0x00000040 |
||||
#define SZ_1M 0x00000050 |
||||
#define SZ_16M 0x00000070 |
||||
#define SZ_256M 0x00000090 |
||||
|
||||
/* Storage attributes */ |
||||
#define SA_W 0x00000800 /* Write-through */ |
||||
#define SA_I 0x00000400 /* Caching inhibited */ |
||||
#define SA_M 0x00000200 /* Memory coherence */ |
||||
#define SA_G 0x00000100 /* Guarded */ |
||||
#define SA_E 0x00000080 /* Endian */ |
||||
|
||||
/* Access control */ |
||||
#define AC_X 0x00000024 /* Execute */ |
||||
#define AC_W 0x00000012 /* Write */ |
||||
#define AC_R 0x00000009 /* Read */ |
||||
|
||||
/* Some handy macros */ |
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00) |
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) |
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) |
||||
#define TLB2(a) ( (a)&0x00000fbf ) |
||||
|
||||
#define tlbtab_start\ |
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\ |
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\ |
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) |
||||
|
||||
|
||||
/************************************************************************** |
||||
* TLB TABLE |
||||
* |
||||
* This table is used by the cpu boot code to setup the initial tlb |
||||
* entries. Rather than make broad assumptions in the cpu source tree, |
||||
* this table lets each board set things up however they like. |
||||
* |
||||
* Pointer to the table is returned in r1 |
||||
* |
||||
*************************************************************************/ |
||||
|
||||
.section .bootpg,"ax" |
||||
.globl tlbtab
|
||||
|
||||
tlbtab: |
||||
tlbtab_start |
||||
tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) |
||||
tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) |
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) |
||||
|
||||
/* PCI */ |
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) |
||||
|
||||
/* NAND */ |
||||
tlbentry( CFG_NAND_BASE, SZ_4K, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
tlbtab_end |
||||
@ -0,0 +1,173 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de |
||||
* |
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
||||
|
||||
#include <asm/processor.h> |
||||
#include <nand.h> |
||||
|
||||
struct alpr_ndfc_regs { |
||||
u8 cmd[4]; |
||||
u8 addr_wait; |
||||
u8 term; |
||||
u8 dummy; |
||||
u8 dummy2; |
||||
u8 data; |
||||
}; |
||||
|
||||
static u8 hwctl; |
||||
static struct alpr_ndfc_regs *alpr_ndfc = NULL; |
||||
|
||||
#define readb(addr) (u8)(*(volatile u8 *)(addr)) |
||||
#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d)) |
||||
|
||||
/*
|
||||
* The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to |
||||
* the NAND devices. The NDFC has command, address and data registers that |
||||
* when accessed will set up the NAND flash pins appropriately. We'll use the |
||||
* hwcontrol function to save the configuration in a global variable. |
||||
* We can then use this information in the read and write functions to |
||||
* determine which NDFC register to access. |
||||
* |
||||
* There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte). |
||||
*/ |
||||
static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd) |
||||
{ |
||||
switch (cmd) { |
||||
case NAND_CTL_SETCLE: |
||||
hwctl |= 0x1; |
||||
break; |
||||
case NAND_CTL_CLRCLE: |
||||
hwctl &= ~0x1; |
||||
break; |
||||
case NAND_CTL_SETALE: |
||||
hwctl |= 0x2; |
||||
break; |
||||
case NAND_CTL_CLRALE: |
||||
hwctl &= ~0x2; |
||||
break; |
||||
case NAND_CTL_SETNCE: |
||||
break; |
||||
case NAND_CTL_CLRNCE: |
||||
writeb(0x00, &(alpr_ndfc->term)); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte) |
||||
{ |
||||
struct nand_chip *nand = mtd->priv; |
||||
|
||||
if (hwctl & 0x1) |
||||
/*
|
||||
* IO_ADDR_W used as CMD[i] reg to support multiple NAND |
||||
* chips. |
||||
*/ |
||||
writeb(byte, nand->IO_ADDR_W); |
||||
else if (hwctl & 0x2) { |
||||
writeb(byte, &(alpr_ndfc->addr_wait)); |
||||
} else |
||||
writeb(byte, &(alpr_ndfc->data)); |
||||
} |
||||
|
||||
static u_char alpr_nand_read_byte(struct mtd_info *mtd) |
||||
{ |
||||
return readb(&(alpr_ndfc->data)); |
||||
} |
||||
|
||||
static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
||||
{ |
||||
struct nand_chip *nand = mtd->priv; |
||||
int i; |
||||
|
||||
for (i = 0; i < len; i++) { |
||||
if (hwctl & 0x1) |
||||
/*
|
||||
* IO_ADDR_W used as CMD[i] reg to support multiple NAND |
||||
* chips. |
||||
*/ |
||||
writeb(buf[i], nand->IO_ADDR_W); |
||||
else if (hwctl & 0x2) |
||||
writeb(buf[i], &(alpr_ndfc->addr_wait)); |
||||
else |
||||
writeb(buf[i], &(alpr_ndfc->data)); |
||||
} |
||||
} |
||||
|
||||
static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < len; i++) { |
||||
buf[i] = readb(&(alpr_ndfc->data)); |
||||
} |
||||
} |
||||
|
||||
static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < len; i++) |
||||
if (buf[i] != readb(&(alpr_ndfc->data))) |
||||
return i; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int alpr_nand_dev_ready(struct mtd_info *mtd) |
||||
{ |
||||
volatile u_char val; |
||||
|
||||
/*
|
||||
* Blocking read to wait for NAND to be ready |
||||
*/ |
||||
val = readb(&(alpr_ndfc->addr_wait)); |
||||
|
||||
/*
|
||||
* Return always true |
||||
*/ |
||||
return 1; |
||||
} |
||||
|
||||
void board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE; |
||||
|
||||
nand->eccmode = NAND_ECC_SOFT; |
||||
|
||||
/* Reference hardware control function */ |
||||
nand->hwcontrol = alpr_nand_hwcontrol; |
||||
/* Set command delay time */ |
||||
nand->write_byte = alpr_nand_write_byte; |
||||
nand->read_byte = alpr_nand_read_byte; |
||||
nand->write_buf = alpr_nand_write_buf; |
||||
nand->read_buf = alpr_nand_read_buf; |
||||
nand->verify_buf = alpr_nand_verify_buf; |
||||
nand->dev_ready = alpr_nand_dev_ready; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,157 @@ |
||||
/* |
||||
* (C) Copyright 2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/ppc4xx/start.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
board/prodrive/alpr/init.o (.text) |
||||
cpu/ppc4xx/kgdb.o (.text) |
||||
cpu/ppc4xx/traps.o (.text) |
||||
cpu/ppc4xx/interrupts.o (.text) |
||||
cpu/ppc4xx/serial.o (.text) |
||||
cpu/ppc4xx/cpu_init.o (.text) |
||||
cpu/ppc4xx/speed.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
/* . = env_offset;*/ |
||||
/* common/environment.o(.text)*/ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,305 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Heiko Schocher, hs@denx.de |
||||
* Based on ACE1XK.c |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> /* core U-Boot definitions */ |
||||
#include <altera.h> |
||||
#include <ACEX1K.h> /* ACEX device family */ |
||||
|
||||
#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) |
||||
|
||||
/* Define FPGA_DEBUG to get debug printf's */ |
||||
#ifdef FPGA_DEBUG |
||||
#define PRINTF(fmt,args...) printf (fmt ,##args) |
||||
#else |
||||
#define PRINTF(fmt,args...) |
||||
#endif |
||||
|
||||
/* Note: The assumption is that we cannot possibly run fast enough to
|
||||
* overrun the device (the Slave Parallel mode can free run at 50MHz). |
||||
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in |
||||
* the board config file to slow things down. |
||||
*/ |
||||
#ifndef CONFIG_FPGA_DELAY |
||||
#define CONFIG_FPGA_DELAY() |
||||
#endif |
||||
|
||||
#ifndef CFG_FPGA_WAIT |
||||
#define CFG_FPGA_WAIT CFG_HZ/10 /* 100 ms */ |
||||
#endif |
||||
|
||||
static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize ); |
||||
static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); |
||||
/* static int CYC2_ps_info( Altera_desc *desc ); */ |
||||
static int CYC2_ps_reloc( Altera_desc *desc, ulong reloc_offset ); |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
/* CYCLON2 Generic Implementation */ |
||||
int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; |
||||
|
||||
switch (desc->iface) { |
||||
case passive_serial: |
||||
PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); |
||||
ret_val = CYC2_ps_load (desc, buf, bsize); |
||||
break; |
||||
|
||||
/* Add new interface types here */ |
||||
|
||||
default: |
||||
printf ("%s: Unsupported interface type, %d\n", |
||||
__FUNCTION__, desc->iface); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; |
||||
|
||||
switch (desc->iface) { |
||||
case passive_serial: |
||||
PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); |
||||
ret_val = CYC2_ps_dump (desc, buf, bsize); |
||||
break; |
||||
|
||||
/* Add new interface types here */ |
||||
|
||||
default: |
||||
printf ("%s: Unsupported interface type, %d\n", |
||||
__FUNCTION__, desc->iface); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
int CYC2_info( Altera_desc *desc ) |
||||
{ |
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
int CYC2_reloc (Altera_desc * desc, ulong reloc_offset) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume a failure */ |
||||
|
||||
if (desc->family != Altera_CYC2) { |
||||
printf ("%s: Unsupported family type, %d\n", |
||||
__FUNCTION__, desc->family); |
||||
return FPGA_FAIL; |
||||
} else |
||||
switch (desc->iface) { |
||||
case passive_serial: |
||||
ret_val = CYC2_ps_reloc (desc, reloc_offset); |
||||
break; |
||||
|
||||
/* Add new interface types here */ |
||||
|
||||
default: |
||||
printf ("%s: Unsupported interface type, %d\n", |
||||
__FUNCTION__, desc->iface); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
/* CYCLON2 Passive Serial Generic Implementation */ |
||||
static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume the worst */ |
||||
Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; |
||||
int ret = 0; |
||||
|
||||
PRINTF ("%s: start with interface functions @ 0x%p\n", |
||||
__FUNCTION__, fn); |
||||
|
||||
if (fn) { |
||||
int cookie = desc->cookie; /* make a local copy */ |
||||
unsigned long ts; /* timestamp */ |
||||
|
||||
PRINTF ("%s: Function Table:\n" |
||||
"ptr:\t0x%p\n" |
||||
"struct: 0x%p\n" |
||||
"config:\t0x%p\n" |
||||
"status:\t0x%p\n" |
||||
"write:\t0x%p\n" |
||||
"done:\t0x%p\n\n", |
||||
__FUNCTION__, &fn, fn, fn->config, fn->status, |
||||
fn->write, fn->done); |
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
printf ("Loading FPGA Device %d...", cookie); |
||||
#endif |
||||
|
||||
/*
|
||||
* Run the pre configuration function if there is one. |
||||
*/ |
||||
if (*fn->pre) { |
||||
(*fn->pre) (cookie); |
||||
} |
||||
|
||||
/* Establish the initial state */ |
||||
(*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ |
||||
|
||||
udelay(2); /* T_cfg > 2us */ |
||||
|
||||
/* Wait for nSTATUS to be asserted */ |
||||
ts = get_timer (0); /* get current time */ |
||||
do { |
||||
CONFIG_FPGA_DELAY (); |
||||
if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ |
||||
puts ("** Timeout waiting for STATUS to go high.\n"); |
||||
(*fn->abort) (cookie); |
||||
return FPGA_FAIL; |
||||
} |
||||
} while (!(*fn->status) (cookie)); |
||||
|
||||
/* Get ready for the burn */ |
||||
CONFIG_FPGA_DELAY (); |
||||
|
||||
ret = (*fn->write) (buf, bsize, TRUE, cookie); |
||||
if (ret) { |
||||
puts ("** Write failed.\n"); |
||||
(*fn->abort) (cookie); |
||||
return FPGA_FAIL; |
||||
} |
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
puts(" OK? ..."); |
||||
#endif |
||||
|
||||
CONFIG_FPGA_DELAY (); |
||||
|
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
putc (' '); /* terminate the dotted line */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Checking FPGA's CONF_DONE signal - correctly booted ? |
||||
*/ |
||||
|
||||
if ( ! (*fn->done) (cookie) ) { |
||||
puts ("** Booting failed! CONF_DONE is still deasserted.\n"); |
||||
(*fn->abort) (cookie); |
||||
return (FPGA_FAIL); |
||||
} |
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
puts(" OK\n"); |
||||
#endif |
||||
|
||||
ret_val = FPGA_SUCCESS; |
||||
|
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
if (ret_val == FPGA_SUCCESS) { |
||||
puts ("Done.\n"); |
||||
} |
||||
else { |
||||
puts ("Fail.\n"); |
||||
} |
||||
#endif |
||||
(*fn->post) (cookie); |
||||
|
||||
} else { |
||||
printf ("%s: NULL Interface function table!\n", __FUNCTION__); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
/* Readback is only available through the Slave Parallel and */ |
||||
/* boundary-scan interfaces. */ |
||||
printf ("%s: Passive Serial Dumping is unavailable\n", |
||||
__FUNCTION__); |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume the worst */ |
||||
Altera_CYC2_Passive_Serial_fns *fn_r, *fn = |
||||
(Altera_CYC2_Passive_Serial_fns *) (desc->iface_fns); |
||||
|
||||
if (fn) { |
||||
ulong addr; |
||||
|
||||
/* Get the relocated table address */ |
||||
addr = (ulong) fn + reloc_offset; |
||||
fn_r = (Altera_CYC2_Passive_Serial_fns *) addr; |
||||
|
||||
if (!fn_r->relocated) { |
||||
|
||||
if (memcmp (fn_r, fn, |
||||
sizeof (Altera_CYC2_Passive_Serial_fns)) |
||||
== 0) { |
||||
/* good copy of the table, fix the descriptor pointer */ |
||||
desc->iface_fns = fn_r; |
||||
} else { |
||||
PRINTF ("%s: Invalid function table at 0x%p\n", |
||||
__FUNCTION__, fn_r); |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, |
||||
desc); |
||||
|
||||
addr = (ulong) (fn->pre) + reloc_offset; |
||||
fn_r->pre = (Altera_pre_fn) addr; |
||||
|
||||
addr = (ulong) (fn->config) + reloc_offset; |
||||
fn_r->config = (Altera_config_fn) addr; |
||||
|
||||
addr = (ulong) (fn->status) + reloc_offset; |
||||
fn_r->status = (Altera_status_fn) addr; |
||||
|
||||
addr = (ulong) (fn->done) + reloc_offset; |
||||
fn_r->done = (Altera_done_fn) addr; |
||||
|
||||
addr = (ulong) (fn->write) + reloc_offset; |
||||
fn_r->write = (Altera_write_fn) addr; |
||||
|
||||
addr = (ulong) (fn->abort) + reloc_offset; |
||||
fn_r->abort = (Altera_abort_fn) addr; |
||||
|
||||
addr = (ulong) (fn->post) + reloc_offset; |
||||
fn_r->post = (Altera_post_fn) addr; |
||||
|
||||
fn_r->relocated = TRUE; |
||||
|
||||
} else { |
||||
/* this table has already been moved */ |
||||
/* XXX - should check to see if the descriptor is correct */ |
||||
desc->iface_fns = fn_r; |
||||
} |
||||
|
||||
ret_val = FPGA_SUCCESS; |
||||
} else { |
||||
printf ("%s: NULL Interface function table!\n", __FUNCTION__); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */ |
||||
@ -0,0 +1,346 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_ALPR 1 /* Board is ebony */ |
||||
#define CONFIG_440GX 1 /* Specifc GX support */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ |
||||
#undef CFG_DRAM_TEST /* Disable-takes long time! */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */ |
||||
#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ |
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
||||
#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ |
||||
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ |
||||
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
||||
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ |
||||
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 |
||||
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 |
||||
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 |
||||
|
||||
|
||||
#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) |
||||
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_TEMP_STACK_OCM 1 |
||||
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE |
||||
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) |
||||
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#undef CFG_EXT_SERIAL_CLOCK |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_FLASH_CFI 1 /* The flash is CFI compatible */ |
||||
#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
||||
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ |
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ |
||||
#undef CONFIG_SDRAM_ECC /* enable ECC support */ |
||||
#define CFG_SDRAM_TABLE { \ |
||||
{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
|
||||
{(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (PCF8594C) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ |
||||
/* 8 byte page write mode using */ |
||||
/* last 3 bits of the address */ |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth3\0" \
|
||||
"hostname=alpr\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
|
||||
"mem=193M\0" \
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/projects/alpr/nfs_root\0" \
|
||||
"bootfile=/alpr/uImage\0" \
|
||||
"kernel_addr=fff00000\0" \
|
||||
"ramdisk_addr=fff10000\0" \
|
||||
"load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */ |
||||
#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */ |
||||
#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */ |
||||
#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */ |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_HAS_ETH2 |
||||
#define CONFIG_HAS_ETH3 |
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
||||
#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/ |
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
||||
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */ |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_FPGA | \
|
||||
CFG_CMD_NAND | \
|
||||
CFG_CMD_REGINFO) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ |
||||
#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ |
||||
#define CFG_PCI_TARGET_INIT /* let board init pci target */ |
||||
#define CFG_PCI_MASTER_INIT |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FPGA stuff |
||||
*-----------------------------------------------------------------------*/ |
||||
#define CONFIG_FPGA CFG_ALTERA_CYCLON2 |
||||
#define CFG_FPGA_CHECK_CTRLC |
||||
#define CFG_FPGA_PROG_FEEDBACK |
||||
#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in |
||||
Reihe geschaltet -> sollte gehen, |
||||
aufpassen mit Datasize ist jetzt |
||||
halt doppelt so gross ... Seite 306 |
||||
ist das mit den multiple Device in PS |
||||
Mode erklaert ...*/ |
||||
|
||||
/* FPGA program pin configuration */ |
||||
#define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ |
||||
#define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */ |
||||
#define CFG_GPIO_STATUS 20 /* FPGA status pin (cpu input) */ |
||||
#define CFG_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */ |
||||
#define CFG_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */ |
||||
|
||||
#define CFG_GPIO_SEL_DPR 14 /* cpu output */ |
||||
#define CFG_GPIO_SEL_AVR 15 /* cpu output */ |
||||
#define CFG_GPIO_PROG_EN 23 /* cpu output */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup |
||||
*-----------------------------------------------------------------------*/ |
||||
#define CFG_GPIO_EREADY (0x80000000 >> 26) |
||||
#define CFG_GPIO_REV0 (0x80000000 >> 14) |
||||
#define CFG_GPIO_REV1 (0x80000000 >> 15) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND-FLASH stuff |
||||
*-----------------------------------------------------------------------*/ |
||||
#define CFG_MAX_NAND_DEVICE 4 |
||||
#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE |
||||
#define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ |
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \ |
||||
CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 } |
||||
#define CFG_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_FLASH CFG_FLASH_BASE |
||||
|
||||
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
||||
#define CFG_EBC_PB0AP 0x92015480 |
||||
#define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 1 (NAND-FLASH) initialization */ |
||||
#define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */ |
||||
#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue