Tom Rini
7 years ago
commit
6bf634223a
@ -0,0 +1,44 @@ |
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CONFIG_ARM=y |
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CONFIG_TARGET_LS1088ARDB=y |
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CONFIG_SPL_LIBCOMMON_SUPPORT=y |
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CONFIG_SPL_LIBGENERIC_SUPPORT=y |
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CONFIG_SECURE_BOOT=y |
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CONFIG_FSL_LS_PPA=y |
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CONFIG_SPL_MMC_SUPPORT=y |
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CONFIG_SPL_SERIAL_SUPPORT=y |
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CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
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CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" |
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CONFIG_DISTRO_DEFAULTS=y |
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# CONFIG_SYS_MALLOC_F is not set |
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CONFIG_FIT_VERBOSE=y |
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CONFIG_OF_BOARD_SETUP=y |
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CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI" |
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CONFIG_SD_BOOT=y |
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# CONFIG_USE_BOOTCOMMAND is not set |
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# CONFIG_DISPLAY_BOARDINFO is not set |
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CONFIG_SPL=y |
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y |
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 |
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CONFIG_SPL_CRYPTO_SUPPORT=y |
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CONFIG_SPL_HASH_SUPPORT=y |
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CONFIG_SPL_ENV_SUPPORT=y |
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CONFIG_SPL_I2C_SUPPORT=y |
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CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y |
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CONFIG_CMD_I2C=y |
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CONFIG_CMD_MMC=y |
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CONFIG_CMD_SF=y |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_OF_CONTROL=y |
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CONFIG_NET_RANDOM_ETHADDR=y |
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CONFIG_DM=y |
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CONFIG_SPL_DM=y |
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CONFIG_SCSI_AHCI=y |
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CONFIG_DM_SPI_FLASH=y |
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CONFIG_SPI_FLASH=y |
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CONFIG_NETDEVICES=y |
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CONFIG_E1000=y |
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CONFIG_SYS_NS16550=y |
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CONFIG_DM_SPI=y |
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CONFIG_FSL_DSPI=y |
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CONFIG_RSA=y |
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CONFIG_SPL_RSA=y |
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@ -0,0 +1,305 @@ |
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/*
|
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* Copyright 2008-2011 Freescale Semiconductor, Inc. |
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* Copyright 2017 NXP |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <libfdt.h> |
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#include <fdt_support.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#ifdef CONFIG_PPC |
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#include <asm/fsl_portals.h> |
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#include <asm/fsl_liodn.h> |
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#endif |
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#include <fsl_qbman.h> |
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|
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#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE) |
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#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE) |
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void setup_qbman_portals(void) |
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{ |
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void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE + |
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CONFIG_SYS_BMAN_SWP_ISDR_REG; |
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void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE + |
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CONFIG_SYS_QMAN_SWP_ISDR_REG; |
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#ifdef CONFIG_PPC |
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struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; |
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|
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/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ |
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#ifdef CONFIG_PHYS_64BIT |
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out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); |
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#endif |
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out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); |
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#endif |
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#ifdef CONFIG_FSL_CORENET |
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int i; |
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for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { |
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u8 sdest = qp_info[i].sdest; |
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u16 fliodn = qp_info[i].fliodn; |
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u16 dliodn = qp_info[i].dliodn; |
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u16 liodn_off = qp_info[i].liodn_offset; |
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out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) | |
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dliodn); |
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/* set frame liodn */ |
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out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn); |
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} |
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#endif |
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/* Change default state of BMan ISDR portals to all 1s */ |
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inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS, |
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CONFIG_SYS_BMAN_SP_CINH_SIZE); |
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inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS, |
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CONFIG_SYS_QMAN_SP_CINH_SIZE); |
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} |
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void inhibit_portals(void __iomem *addr, int max_portals, |
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int arch_max_portals, int portal_cinh_size) |
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{ |
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u32 val; |
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int i; |
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/* arch_max_portals is the maximum based on memory size. This includes
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* the reserved memory in the SoC. max_portals the number of physical |
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* portals in the SoC |
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*/ |
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if (max_portals > arch_max_portals) { |
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printf("ERROR: portal config error\n"); |
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max_portals = arch_max_portals; |
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} |
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for (i = 0; i < max_portals; i++) { |
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out_be32(addr, -1); |
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val = in_be32(addr); |
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if (!val) { |
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printf("ERROR: Stopped after %d portals\n", i); |
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return; |
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} |
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addr += portal_cinh_size; |
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} |
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debug("Cleared %d portals\n", i); |
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} |
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|
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#ifdef CONFIG_PPC |
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static int fdt_qportal(void *blob, int off, int id, char *name, |
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enum fsl_dpaa_dev dev, int create) |
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{ |
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int childoff, dev_off, ret = 0; |
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u32 dev_handle; |
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#ifdef CONFIG_FSL_CORENET |
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int num; |
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u32 liodns[2]; |
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#endif |
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childoff = fdt_subnode_offset(blob, off, name); |
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if (create) { |
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char handle[64], *p; |
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strncpy(handle, name, sizeof(handle)); |
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p = strchr(handle, '@'); |
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if (!strncmp(name, "fman", 4)) { |
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*p = *(p + 1); |
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p++; |
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} |
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*p = '\0'; |
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dev_off = fdt_path_offset(blob, handle); |
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/* skip this node if alias is not found */ |
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if (dev_off == -FDT_ERR_BADPATH) |
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return 0; |
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if (dev_off < 0) |
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return dev_off; |
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if (childoff <= 0) |
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childoff = fdt_add_subnode(blob, off, name); |
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/* need to update the dev_off after adding a subnode */ |
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dev_off = fdt_path_offset(blob, handle); |
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if (dev_off < 0) |
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return dev_off; |
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if (childoff > 0) { |
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dev_handle = fdt_get_phandle(blob, dev_off); |
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if (dev_handle <= 0) { |
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dev_handle = fdt_alloc_phandle(blob); |
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ret = fdt_set_phandle(blob, dev_off, |
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dev_handle); |
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if (ret < 0) |
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return ret; |
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} |
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ret = fdt_setprop(blob, childoff, "dev-handle", |
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&dev_handle, sizeof(dev_handle)); |
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if (ret < 0) |
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return ret; |
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|
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#ifdef CONFIG_FSL_CORENET |
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num = get_dpaa_liodn(dev, &liodns[0], id); |
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ret = fdt_setprop(blob, childoff, "fsl,liodn", |
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&liodns[0], sizeof(u32) * num); |
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if (!strncmp(name, "pme", 3)) { |
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u32 pme_rev1, pme_rev2; |
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ccsr_pme_t *pme_regs = |
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(void *)CONFIG_SYS_FSL_CORENET_PME_ADDR; |
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pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1); |
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pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2); |
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ret = fdt_setprop(blob, childoff, |
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"fsl,pme-rev1", &pme_rev1, |
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sizeof(u32)); |
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if (ret < 0) |
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return ret; |
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ret = fdt_setprop(blob, childoff, |
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"fsl,pme-rev2", &pme_rev2, |
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sizeof(u32)); |
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} |
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#endif |
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} else { |
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return childoff; |
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} |
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} else { |
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if (childoff > 0) |
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ret = fdt_del_node(blob, childoff); |
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} |
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return ret; |
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} |
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#endif /* CONFIG_PPC */ |
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void fdt_fixup_qportals(void *blob) |
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{ |
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int off, err; |
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unsigned int maj, min; |
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unsigned int ip_cfg; |
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struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; |
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u32 rev_1 = in_be32(&qman->ip_rev_1); |
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u32 rev_2 = in_be32(&qman->ip_rev_2); |
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char compat[64]; |
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int compat_len; |
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maj = (rev_1 >> 8) & 0xff; |
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min = rev_1 & 0xff; |
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ip_cfg = rev_2 & 0xff; |
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compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u", |
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maj, min, ip_cfg) + 1; |
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compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1; |
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off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); |
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while (off != -FDT_ERR_NOTFOUND) { |
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#ifdef CONFIG_PPC |
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#ifdef CONFIG_FSL_CORENET |
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u32 liodns[2]; |
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#endif |
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const int *ci = fdt_getprop(blob, off, "cell-index", &err); |
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int i; |
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if (!ci) |
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goto err; |
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i = *ci; |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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int j; |
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#endif |
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#endif /* CONFIG_PPC */ |
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err = fdt_setprop(blob, off, "compatible", compat, compat_len); |
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if (err < 0) |
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goto err; |
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#ifdef CONFIG_PPC |
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#ifdef CONFIG_FSL_CORENET |
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liodns[0] = qp_info[i].dliodn; |
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liodns[1] = qp_info[i].fliodn; |
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err = fdt_setprop(blob, off, "fsl,liodn", |
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&liodns, sizeof(u32) * 2); |
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if (err < 0) |
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goto err; |
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#endif |
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i++; |
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err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC, |
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IS_E_PROCESSOR(get_svr())); |
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if (err < 0) |
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goto err; |
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#ifdef CONFIG_FSL_CORENET |
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#ifdef CONFIG_SYS_DPAA_PME |
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err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1); |
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if (err < 0) |
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goto err; |
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#else |
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fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0); |
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#endif |
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#endif |
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|
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#ifdef CONFIG_SYS_DPAA_FMAN |
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for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { |
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char name[] = "fman@0"; |
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name[sizeof(name) - 2] = '0' + j; |
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err = fdt_qportal(blob, off, i, name, |
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FSL_HW_PORTAL_FMAN1 + j, 1); |
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if (err < 0) |
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goto err; |
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} |
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#endif |
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#ifdef CONFIG_SYS_DPAA_RMAN |
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err = fdt_qportal(blob, off, i, "rman@0", |
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FSL_HW_PORTAL_RMAN, 1); |
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if (err < 0) |
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goto err; |
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#endif |
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#endif /* CONFIG_PPC */ |
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|
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err: |
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if (err < 0) { |
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printf("ERROR: unable to create props for %s: %s\n", |
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fdt_get_name(blob, off, NULL), |
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fdt_strerror(err)); |
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return; |
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} |
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off = fdt_node_offset_by_compatible(blob, off, |
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"fsl,qman-portal"); |
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} |
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} |
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|
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void fdt_fixup_bportals(void *blob) |
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{ |
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int off, err; |
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unsigned int maj, min; |
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unsigned int ip_cfg; |
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struct ccsr_bman *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR; |
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u32 rev_1 = in_be32(&bman->ip_rev_1); |
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u32 rev_2 = in_be32(&bman->ip_rev_2); |
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char compat[64]; |
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int compat_len; |
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maj = (rev_1 >> 8) & 0xff; |
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min = rev_1 & 0xff; |
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ip_cfg = rev_2 & 0xff; |
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compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u", |
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maj, min, ip_cfg) + 1; |
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compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1; |
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|
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off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal"); |
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while (off != -FDT_ERR_NOTFOUND) { |
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err = fdt_setprop(blob, off, "compatible", compat, compat_len); |
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if (err < 0) { |
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printf("ERROR: unable to create props for %s: %s\n", |
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fdt_get_name(blob, off, NULL), |
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fdt_strerror(err)); |
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return; |
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} |
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|
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off = fdt_node_offset_by_compatible(blob, off, |
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"fsl,bman-portal"); |
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} |
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} |
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@ -0,0 +1,75 @@ |
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/*
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* Copyright 2017 NXP |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef __FSL_QBMAN_H__ |
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#define __FSL_QBMAN_H__ |
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void fdt_fixup_qportals(void *blob); |
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void fdt_fixup_bportals(void *blob); |
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void inhibit_portals(void __iomem *addr, int max_portals, |
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int arch_max_portals, int portal_cinh_size); |
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void setup_qbman_portals(void); |
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|
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struct ccsr_qman { |
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#ifdef CONFIG_SYS_FSL_QMAN_V3 |
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u8 res0[0x200]; |
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#else |
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struct { |
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u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ |
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u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ |
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u32 res; |
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u32 qcsp_dd_cfg; /* 0xc - SW Portal Dynamic Debug cfg */ |
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} qcsp[32]; |
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#endif |
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/* Not actually reserved, but irrelevant to u-boot */ |
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u8 res[0xbf8 - 0x200]; |
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u32 ip_rev_1; |
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u32 ip_rev_2; |
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u32 fqd_bare; /* FQD Extended Base Addr Register */ |
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u32 fqd_bar; /* FQD Base Addr Register */ |
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u8 res1[0x8]; |
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u32 fqd_ar; /* FQD Attributes Register */ |
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u8 res2[0xc]; |
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u32 pfdr_bare; /* PFDR Extended Base Addr Register */ |
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u32 pfdr_bar; /* PFDR Base Addr Register */ |
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u8 res3[0x8]; |
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u32 pfdr_ar; /* PFDR Attributes Register */ |
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u8 res4[0x4c]; |
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u32 qcsp_bare; /* QCSP Extended Base Addr Register */ |
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u32 qcsp_bar; /* QCSP Base Addr Register */ |
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u8 res5[0x78]; |
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u32 ci_sched_cfg; /* Initiator Scheduling Configuration */ |
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u32 srcidr; /* Source ID Register */ |
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u32 liodnr; /* LIODN Register */ |
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u8 res6[4]; |
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u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ |
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u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ |
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u8 res7[0x2e8]; |
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#ifdef CONFIG_SYS_FSL_QMAN_V3 |
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struct { |
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u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ |
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u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ |
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u32 res; |
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u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/ |
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} qcsp[50]; |
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#endif |
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}; |
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|
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struct ccsr_bman { |
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/* Not actually reserved, but irrelevant to u-boot */ |
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u8 res[0xbf8]; |
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u32 ip_rev_1; |
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u32 ip_rev_2; |
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u32 fbpr_bare; /* FBPR Extended Base Addr Register */ |
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u32 fbpr_bar; /* FBPR Base Addr Register */ |
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u8 res1[0x8]; |
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u32 fbpr_ar; /* FBPR Attributes Register */ |
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u8 res2[0xf0]; |
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u32 srcidr; /* Source ID Register */ |
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u32 liodnr; /* LIODN Register */ |
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u8 res7[0x2f4]; |
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}; |
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|
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#endif /* __FSL_QBMAN_H__ */ |
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