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ARM64: zynqmp: Add support for zc1751 with DC cards

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Support ZynqMP zc1751 with DC cards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
master
Michal Simek 9 years ago
parent da81db61d5
commit 6c0c958de8
10 changed files with 748 additions and 1 deletions
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  1. 5
      arch/arm/dts/Makefile
  2. 211
      arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
  3. 236
      arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
  4. 121
      arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
  5. 34
      configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
  6. 32
      configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
  7. 21
      configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
  8. 31
      include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
  9. 28
      include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
  10. 30
      include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h

5
arch/arm/dts/Makefile
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@ -83,7 +83,10 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb \
zynqmp-zcu102.dtb \
zynqmp-zcu102-revB.dtb
zynqmp-zcu102-revB.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb

211
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
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@ -0,0 +1,211 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
/ {
model = "ZynqMP zc1751-xm015-dc1 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
rtc0 = &rtc;
serial0 = &uart0;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem3 {
status = "okay";
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
reg = <0>;
};
};
&gpio {
status = "okay";
};
&gpu {
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
eeprom@55 {
compatible = "at,24c64"; /* 24AA64 */
reg = <0x55>;
};
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
};
};
&rtc {
status = "okay";
};
&sata {
status = "okay";
/* SATA phy OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
};
/* eMMC */
&sdhci0 {
status = "okay";
bus-width = <8>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
no-1-8-v; /* for 1.0 silicon */
};
&uart0 {
status = "okay";
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
dr_mode = "host";
};
&xilinx_drm {
status = "okay";
};
&xlnx_dp {
status = "okay";
};
&xlnx_dp_sub {
status = "okay";
xlnx,vid-clk-pl;
};
&xlnx_dp_snd_pcm0 {
status = "okay";
};
&xlnx_dp_snd_pcm1 {
status = "okay";
};
&xlnx_dp_snd_card {
status = "okay";
};
&xlnx_dp_snd_codec0 {
status = "okay";
};
&xlnx_dpdma {
status = "okay";
};

236
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
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@ -0,0 +1,236 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
/ {
model = "ZynqMP zc1751-xm016-dc2 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
can0 = &can0;
can1 = &can1;
ethernet0 = &gem2;
gpio0 = &gpio;
i2c0 = &i2c0;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &spi0;
spi1 = &spi1;
usb0 = &usb1;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem2 {
status = "okay";
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
};
};
&gpio {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
tca6416_u26: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/* IRQ not connected */
};
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&nand0 {
status = "okay";
arasan,has-mdma;
num-cs = <2>;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand-rootfs";
reg = <0x0 0x1C00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand-misc";
reg = <0x0 0x3400000 0xFCC00000>;
};
partition@6 { /* for testing purpose */
label = "nand1-fsbl-uboot";
reg = <0x1 0x0 0x400000>;
};
partition@7 { /* for testing purpose */
label = "nand1-linux";
reg = <0x1 0x400000 0x1400000>;
};
partition@8 { /* for testing purpose */
label = "nand1-device-tree";
reg = <0x1 0x1800000 0x400000>;
};
partition@9 { /* for testing purpose */
label = "nand1-rootfs";
reg = <0x1 0x1C00000 0x1400000>;
};
partition@10 { /* for testing purpose */
label = "nand1-bitstream";
reg = <0x1 0x3000000 0x400000>;
};
partition@11 { /* for testing purpose */
label = "nand1-misc";
reg = <0x1 0x3400000 0xFCC00000>;
};
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
num-cs = <1>;
spi0_flash0: spi0_flash0@0 {
compatible = "m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
spi0_flash0@00000000 {
label = "spi0_flash0";
reg = <0x0 0x100000>;
};
};
};
&spi1 {
status = "okay";
num-cs = <1>;
spi1_flash0: spi1_flash0@0 {
compatible = "mtd_dataflash";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
spi1_flash0@00000000 {
label = "spi1_flash0";
reg = <0x0 0x84000>;
};
};
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
dr_mode = "host";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};

121
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
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@ -0,0 +1,121 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
/ {
model = "ZynqMP zc1751-xm019-dc5 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
ethernet0 = &gem1;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem1 {
status = "okay";
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
reg = <0>;
};
};
&gpio {
status = "okay";
};
/* FIXME: Add device */
&i2c0 {
status = "okay";
};
/* FIXME: Add device */
&i2c1 {
status = "okay";
};
&sdhci0 {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&watchdog0 {
status = "okay";
};

34
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
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@ -0,0 +1,34 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
CONFIG_ARCH_ZYNQMP=y
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y

32
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
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@ -0,0 +1,32 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2"
CONFIG_ARCH_ZYNQMP=y
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_MMC=y
CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y

21
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
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@ -0,0 +1,21 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
CONFIG_ARCH_ZYNQMP=y
CONFIG_DM_GPIO=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_OF_EMBED=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_DM_ETH=y

31
include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
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@ -0,0 +1,31 @@
/*
* Configuration for Xilinx ZynqMP zc1751 XM015 DC1
*
* (C) Copyright 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
#define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_SDHCI1
#define CONFIG_ZYNQ_I2C1
#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_AHCI
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1"
#define CONFIG_KERNEL_FDT_OFST_SIZE \
"kernel_offset=0x400000\0" \
"fdt_offset=0x2400000\0" \
"kernel_size=0x2000000\0" \
"fdt_size=0x80000\0" \
"board=zc1751-dc1\0"
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */

28
include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
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@ -0,0 +1,28 @@
/*
* Configuration for Xilinx ZynqMP zc1751 XM016 DC2
*
* (C) Copyright 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
#define CONFIG_ZYNQ_I2C0
#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR}
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2"
#define CONFIG_KERNEL_FDT_OFST_SIZE \
"kernel_offset=0x400000\0" \
"fdt_offset=0x2400000\0" \
"kernel_size=0x2000000\0" \
"fdt_size=0x80000\0" \
"board=zc1751-dc2\0"
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */

30
include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
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/*
* Configuration for Xilinx ZynqMP zc1751 XM019 DC5
*
* (C) Copyright 2015 Xilinx, Inc.
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
#define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_I2C0
#define CONFIG_ZYNQ_I2C1
#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5"
#define CONFIG_KERNEL_FDT_OFST_SIZE \
"kernel_offset=0x400000\0" \
"fdt_offset=0x2400000\0" \
"kernel_size=0x2000000\0" \
"fdt_size=0x80000\0" \
"board=zc1751-dc5\0"
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */
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