parent
bb105f24cc
commit
6c5879f380
@ -0,0 +1,47 @@ |
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#
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# (C) Copyright 2006
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o cmd_yucca.o
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SOBJS = init.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend *~
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,288 @@ |
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/*
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* (C) Copyright 2001 |
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* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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* hacked for evb440spe |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include "yucca.h" |
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#include <i2c.h> |
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#include <asm/byteorder.h> |
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extern void print_evb440spe_info(void); |
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static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
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int flag, int argc, char *argv[]); |
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extern int cmd_get_data_size(char* arg, int default_size); |
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/* ------------------------------------------------------------------------- */ |
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int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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return setBootStrapClock (cmdtp, 1, flag, argc, argv); |
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} |
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|
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/* ------------------------------------------------------------------------- */ |
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/* Modify memory.
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* |
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* Syntax: |
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* evb440spe wrclk prom0,prom1 |
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*/ |
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static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, |
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int argc, char *argv[]) |
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{ |
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uchar chip; |
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ulong data; |
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int nbytes; |
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extern char console_buffer[]; |
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char sysClock[4]; |
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char cpuClock[4]; |
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char plbClock[4]; |
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char pcixClock[4]; |
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if (argc < 3) { |
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printf ("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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if (strcmp(argv[2], "prom0") == 0) |
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chip = IIC0_BOOTPROM_ADDR; |
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else |
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chip = IIC0_ALT_BOOTPROM_ADDR; |
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do { |
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printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n"); |
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nbytes = readline (" ? "); |
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if (strcmp(console_buffer, "quit") == 0) |
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return 0; |
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if ((strcmp(console_buffer, "33") != 0) & |
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(strcmp(console_buffer, "66") != 0)) |
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nbytes=0; |
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strcpy(sysClock, console_buffer); |
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} while (nbytes == 0); |
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do { |
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if (strcmp(sysClock, "66") == 0) { |
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printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n"); |
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} else { |
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#ifdef CONFIG_STRESS |
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printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n"); |
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#else |
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printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n"); |
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#endif |
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} |
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nbytes = readline (" ? "); |
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if (strcmp(console_buffer, "quit") == 0) |
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return 0; |
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if (strcmp(sysClock, "66") == 0) { |
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if ((strcmp(console_buffer, "400") != 0) & |
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(strcmp(console_buffer, "533") != 0) |
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#ifdef CONFIG_STRESS |
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& (strcmp(console_buffer, "667") != 0) |
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#endif |
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) { |
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nbytes = 0; |
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} |
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} else { |
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if ((strcmp(console_buffer, "400") != 0) & |
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(strcmp(console_buffer, "500") != 0) & |
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(strcmp(console_buffer, "533") != 0) |
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#ifdef CONFIG_STRESS |
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& (strcmp(console_buffer, "667") != 0) |
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#endif |
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) { |
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nbytes = 0; |
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} |
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} |
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strcpy(cpuClock, console_buffer); |
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} while (nbytes == 0); |
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if (strcmp(cpuClock, "500") == 0){ |
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strcpy(plbClock, "166"); |
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} else if (strcmp(cpuClock, "533") == 0){ |
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strcpy(plbClock, "133"); |
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} else { |
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do { |
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if (strcmp(cpuClock, "400") == 0) |
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printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n"); |
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#ifdef CONFIG_STRESS |
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if (strcmp(cpuClock, "667") == 0) |
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printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n"); |
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#endif |
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nbytes = readline (" ? "); |
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if (strcmp(console_buffer, "quit") == 0) |
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return 0; |
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if (strcmp(cpuClock, "400") == 0) { |
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if ((strcmp(console_buffer, "100") != 0) & |
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(strcmp(console_buffer, "133") != 0)) |
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nbytes = 0; |
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} |
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#ifdef CONFIG_STRESS |
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if (strcmp(cpuClock, "667") == 0) { |
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if ((strcmp(console_buffer, "133") != 0) & |
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(strcmp(console_buffer, "166") != 0)) |
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nbytes = 0; |
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} |
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#endif |
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strcpy(plbClock, console_buffer); |
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} while (nbytes == 0); |
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} |
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do { |
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printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n"); |
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nbytes = readline (" ? "); |
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if (strcmp(console_buffer, "quit") == 0) |
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return 0; |
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if ((strcmp(console_buffer, "33") != 0) & |
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(strcmp(console_buffer, "66") != 0) & |
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(strcmp(console_buffer, "100") != 0) & |
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(strcmp(console_buffer, "133") != 0)) { |
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nbytes = 0; |
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} |
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strcpy(pcixClock, console_buffer); |
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} while (nbytes == 0); |
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printf("\nsys clk = %sMhz\n", sysClock); |
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printf("cpu clk = %sMhz\n", cpuClock); |
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printf("plb clk = %sMhz\n", plbClock); |
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printf("Pci-X clk = %sMhz\n", pcixClock); |
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do { |
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printf("\npress [y] to write I2C bootstrap \n"); |
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printf("or [n] to abort. \n"); |
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printf("Don't forget to set board switches \n"); |
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printf("according to your choice before re-starting \n"); |
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printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n"); |
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nbytes = readline (" ? "); |
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if (strcmp(console_buffer, "n") == 0) |
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return 0; |
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} while (nbytes == 0); |
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if (strcmp(sysClock, "33") == 0) { |
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if ((strcmp(cpuClock, "400") == 0) & |
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(strcmp(plbClock, "100") == 0)) |
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data = 0x8678c206; |
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if ((strcmp(cpuClock, "400") == 0) & |
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(strcmp(plbClock, "133") == 0)) |
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data = 0x8678c2c6; |
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if ((strcmp(cpuClock, "500") == 0)) |
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data = 0x8778f2c6; |
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if ((strcmp(cpuClock, "533") == 0)) |
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data = 0x87790252; |
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#ifdef CONFIG_STRESS |
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if ((strcmp(cpuClock, "667") == 0) & |
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(strcmp(plbClock, "133") == 0)) |
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data = 0x87794256; |
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if ((strcmp(cpuClock, "667") == 0) & |
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(strcmp(plbClock, "166") == 0)) |
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data = 0x87794206; |
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#endif |
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} |
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if (strcmp(sysClock, "66") == 0) { |
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if ((strcmp(cpuClock, "400") == 0) & |
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(strcmp(plbClock, "100") == 0)) |
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data = 0x84706206; |
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if ((strcmp(cpuClock, "400") == 0) & |
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(strcmp(plbClock, "133") == 0)) |
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data = 0x847062c6; |
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if ((strcmp(cpuClock, "533") == 0)) |
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data = 0x85708206; |
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#ifdef CONFIG_STRESS |
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if ((strcmp(cpuClock, "667") == 0) & |
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(strcmp(plbClock, "133") == 0)) |
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data = 0x8570a256; |
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if ((strcmp(cpuClock, "667") == 0) & |
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(strcmp(plbClock, "166") == 0)) |
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data = 0x8570a206; |
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#endif |
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} |
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#ifdef DEBUG |
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printf(" pin strap0 to write in i2c = %x\n", data); |
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#endif /* DEBUG */ |
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if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0) |
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printf("Error writing strap0 in %s\n", argv[2]); |
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if (strcmp(pcixClock, "33") == 0) |
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data = 0x00000701; |
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if (strcmp(pcixClock, "66") == 0) |
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data = 0x00000601; |
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if (strcmp(pcixClock, "100") == 0) |
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data = 0x00000501; |
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if (strcmp(pcixClock, "133") == 0) |
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data = 0x00000401; |
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if (strcmp(plbClock, "166") == 0) |
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data = data | 0x05950000; |
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else |
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data = data | 0x05A50000; |
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#ifdef DEBUG |
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printf(" pin strap1 to write in i2c = %x\n", data); |
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#endif /* DEBUG */ |
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udelay(1000); |
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if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0) |
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printf("Error writing strap1 in %s\n", argv[2]); |
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return 0; |
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} |
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U_BOOT_CMD( |
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evb440spe, 3, 1, do_evb440spe, |
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"evb440spe - program the serial device strap\n", |
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"wrclk [prom0|prom1] - program the serial device strap\n" |
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); |
@ -0,0 +1,42 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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|
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#
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# AMCC 440SPe Reference Platform (yucca) board
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#
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ifeq ($(ramsym),1) |
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TEXT_BASE = 0x07FD0000
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else |
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TEXT_BASE = 0xfffb0000
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endif |
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|
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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|
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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|
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
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endif |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,105 @@ |
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/* |
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
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* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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/* port to AMCC 440SPE evaluatioon board - SG April 12,2005 */ |
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|
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#include <ppc_asm.tmpl> |
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#include <config.h> |
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|
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/* General */ |
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#define TLB_VALID 0x00000200 |
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|
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/* Supported page sizes */ |
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|
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#define SZ_1K 0x00000000 |
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#define SZ_4K 0x00000010 |
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#define SZ_16K 0x00000020 |
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#define SZ_64K 0x00000030 |
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#define SZ_256K 0x00000040 |
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#define SZ_1M 0x00000050 |
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#define SZ_16M 0x00000070 |
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#define SZ_256M 0x00000090 |
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|
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/* Storage attributes */ |
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#define SA_W 0x00000800 /* Write-through */ |
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#define SA_I 0x00000400 /* Caching inhibited */ |
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#define SA_M 0x00000200 /* Memory coherence */ |
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#define SA_G 0x00000100 /* Guarded */ |
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#define SA_E 0x00000080 /* Endian */ |
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|
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/* Access control */ |
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#define AC_X 0x00000024 /* Execute */ |
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#define AC_W 0x00000012 /* Write */ |
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#define AC_R 0x00000009 /* Read */ |
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|
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/* Some handy macros */ |
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|
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#define EPN(e) ((e) & 0xfffffc00) |
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#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID )) |
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#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn)) |
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#define TLB2(a) ((a) & 0x00000fbf) |
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|
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#define tlbtab_start\ |
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mflr r1 ;\
|
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bl 0f ;
|
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|
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#define tlbtab_end\ |
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.long 0, 0, 0 ;\
|
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0: mflr r0 ;\
|
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mtlr r1 ;\
|
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blr ;
|
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|
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#define tlbentry(epn,sz,rpn,erpn,attr)\ |
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.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) |
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|
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/************************************************************************** |
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* TLB TABLE |
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* |
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* This table is used by the cpu boot code to setup the initial tlb |
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* entries. Rather than make broad assumptions in the cpu source tree, |
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* this table lets each board set things up however they like. |
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* |
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* Pointer to the table is returned in r1 |
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* |
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*************************************************************************/ |
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|
||||
.section .bootpg,"ax" |
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.globl tlbtab
|
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|
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tlbtab: |
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tlbtab_start |
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tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G) |
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|
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tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) |
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tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) |
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tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) |
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tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) |
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|
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tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) |
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tlbentry(CFG_FPGA_BASE,SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) |
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|
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tlbentry(CFG_OPER_FLASH,SZ_16M,0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) |
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tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) |
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|
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tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbtab_end |
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|
@ -0,0 +1,157 @@ |
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/* |
||||
* (C) Copyright 2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/ppc4xx/start.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
board/amcc/yucca/init.o (.text) |
||||
cpu/ppc4xx/kgdb.o (.text) |
||||
cpu/ppc4xx/traps.o (.text) |
||||
cpu/ppc4xx/interrupts.o (.text) |
||||
cpu/ppc4xx/serial.o (.text) |
||||
cpu/ppc4xx/cpu_init.o (.text) |
||||
cpu/ppc4xx/speed.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
/* . = env_offset;*/ |
||||
/* common/environment.o(.text)*/ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,146 @@ |
||||
/* |
||||
* (C) Copyright 2002-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
board/amcc/yucca/init.o (.text) |
||||
cpu/ppc4xx/kgdb.o (.text) |
||||
cpu/ppc4xx/traps.o (.text) |
||||
cpu/ppc4xx/interrupts.o (.text) |
||||
cpu/ppc4xx/serial.o (.text) |
||||
cpu/ppc4xx/cpu_init.o (.text) |
||||
cpu/ppc4xx/speed.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
/* common/environment.o(.text) */ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,382 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __YUCCA_H_ |
||||
#define __YUCCA_H_ |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| Defines |
||||
+----------------------------------------------------------------------------*/ |
||||
|
||||
#define TMR_FREQ_EXT 25000000 |
||||
#define BOARD_UART_CLOCK 11059200 |
||||
|
||||
#define BOARD_OPTION_SELECTED 1 |
||||
#define BOARD_OPTION_NOT_SELECTED 0 |
||||
|
||||
#define ENGINEERING_CLOCK_CHECKING "clk_chk" |
||||
#define ENGINEERING_EXTERNAL_CLOCK "ext_clk" |
||||
|
||||
#define ENGINEERING_CLOCK_CHECKING_DATA 1 |
||||
#define ENGINEERING_EXTERNAL_CLOCK_DATA 2 |
||||
|
||||
/* ethernet definition */ |
||||
#define MAX_ENETMODE_PARM 3 |
||||
#define ENETMODE_NEG 0 |
||||
#define ENETMODE_SPEED 1 |
||||
#define ENETMODE_DUPLEX 2 |
||||
|
||||
#define ENETMODE_AUTONEG 0 |
||||
#define ENETMODE_NO_AUTONEG 1 |
||||
#define ENETMODE_10 2 |
||||
#define ENETMODE_100 3 |
||||
#define ENETMODE_1000 4 |
||||
#define ENETMODE_HALF 5 |
||||
#define ENETMODE_FULL 6 |
||||
|
||||
#define NUM_TLB_ENTRIES 64 |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| TLB specific defines. |
||||
+----------------------------------------------------------------------------*/ |
||||
#define TLB_256MB_ALIGN_MASK 0xF0000000 |
||||
#define TLB_16MB_ALIGN_MASK 0xFF000000 |
||||
#define TLB_1MB_ALIGN_MASK 0xFFF00000 |
||||
#define TLB_256KB_ALIGN_MASK 0xFFFC0000 |
||||
#define TLB_64KB_ALIGN_MASK 0xFFFF0000 |
||||
#define TLB_16KB_ALIGN_MASK 0xFFFFC000 |
||||
#define TLB_4KB_ALIGN_MASK 0xFFFFF000 |
||||
#define TLB_1KB_ALIGN_MASK 0xFFFFFC00 |
||||
#define TLB_256MB_SIZE 0x10000000 |
||||
#define TLB_16MB_SIZE 0x01000000 |
||||
#define TLB_1MB_SIZE 0x00100000 |
||||
#define TLB_256KB_SIZE 0x00040000 |
||||
#define TLB_64KB_SIZE 0x00010000 |
||||
#define TLB_16KB_SIZE 0x00004000 |
||||
#define TLB_4KB_SIZE 0x00001000 |
||||
#define TLB_1KB_SIZE 0x00000400 |
||||
|
||||
#define TLB_WORD0_EPN_MASK 0xFFFFFC00 |
||||
#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) |
||||
#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) |
||||
#define TLB_WORD0_V_MASK 0x00000200 |
||||
#define TLB_WORD0_V_ENABLE 0x00000200 |
||||
#define TLB_WORD0_V_DISABLE 0x00000000 |
||||
#define TLB_WORD0_TS_MASK 0x00000100 |
||||
#define TLB_WORD0_TS_1 0x00000100 |
||||
#define TLB_WORD0_TS_0 0x00000000 |
||||
#define TLB_WORD0_SIZE_MASK 0x000000F0 |
||||
#define TLB_WORD0_SIZE_1KB 0x00000000 |
||||
#define TLB_WORD0_SIZE_4KB 0x00000010 |
||||
#define TLB_WORD0_SIZE_16KB 0x00000020 |
||||
#define TLB_WORD0_SIZE_64KB 0x00000030 |
||||
#define TLB_WORD0_SIZE_256KB 0x00000040 |
||||
#define TLB_WORD0_SIZE_1MB 0x00000050 |
||||
#define TLB_WORD0_SIZE_16MB 0x00000070 |
||||
#define TLB_WORD0_SIZE_256MB 0x00000090 |
||||
#define TLB_WORD0_TPAR_MASK 0x0000000F |
||||
#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) |
||||
#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) |
||||
|
||||
#define TLB_WORD1_RPN_MASK 0xFFFFFC00 |
||||
#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) |
||||
#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) |
||||
#define TLB_WORD1_PAR1_MASK 0x00000300 |
||||
#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) |
||||
#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03) |
||||
#define TLB_WORD1_PAR1_0 0x00000000 |
||||
#define TLB_WORD1_PAR1_1 0x00000100 |
||||
#define TLB_WORD1_PAR1_2 0x00000200 |
||||
#define TLB_WORD1_PAR1_3 0x00000300 |
||||
#define TLB_WORD1_ERPN_MASK 0x0000000F |
||||
#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) |
||||
#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) |
||||
|
||||
#define TLB_WORD2_PAR2_MASK 0xC0000000 |
||||
#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30) |
||||
#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03) |
||||
#define TLB_WORD2_PAR2_0 0x00000000 |
||||
#define TLB_WORD2_PAR2_1 0x40000000 |
||||
#define TLB_WORD2_PAR2_2 0x80000000 |
||||
#define TLB_WORD2_PAR2_3 0xC0000000 |
||||
#define TLB_WORD2_U0_MASK 0x00008000 |
||||
#define TLB_WORD2_U0_ENABLE 0x00008000 |
||||
#define TLB_WORD2_U0_DISABLE 0x00000000 |
||||
#define TLB_WORD2_U1_MASK 0x00004000 |
||||
#define TLB_WORD2_U1_ENABLE 0x00004000 |
||||
#define TLB_WORD2_U1_DISABLE 0x00000000 |
||||
#define TLB_WORD2_U2_MASK 0x00002000 |
||||
#define TLB_WORD2_U2_ENABLE 0x00002000 |
||||
#define TLB_WORD2_U2_DISABLE 0x00000000 |
||||
#define TLB_WORD2_U3_MASK 0x00001000 |
||||
#define TLB_WORD2_U3_ENABLE 0x00001000 |
||||
#define TLB_WORD2_U3_DISABLE 0x00000000 |
||||
#define TLB_WORD2_W_MASK 0x00000800 |
||||
#define TLB_WORD2_W_ENABLE 0x00000800 |
||||
#define TLB_WORD2_W_DISABLE 0x00000000 |
||||
#define TLB_WORD2_I_MASK 0x00000400 |
||||
#define TLB_WORD2_I_ENABLE 0x00000400 |
||||
#define TLB_WORD2_I_DISABLE 0x00000000 |
||||
#define TLB_WORD2_M_MASK 0x00000200 |
||||
#define TLB_WORD2_M_ENABLE 0x00000200 |
||||
#define TLB_WORD2_M_DISABLE 0x00000000 |
||||
#define TLB_WORD2_G_MASK 0x00000100 |
||||
#define TLB_WORD2_G_ENABLE 0x00000100 |
||||
#define TLB_WORD2_G_DISABLE 0x00000000 |
||||
#define TLB_WORD2_E_MASK 0x00000080 |
||||
#define TLB_WORD2_E_ENABLE 0x00000080 |
||||
#define TLB_WORD2_E_DISABLE 0x00000000 |
||||
#define TLB_WORD2_UX_MASK 0x00000020 |
||||
#define TLB_WORD2_UX_ENABLE 0x00000020 |
||||
#define TLB_WORD2_UX_DISABLE 0x00000000 |
||||
#define TLB_WORD2_UW_MASK 0x00000010 |
||||
#define TLB_WORD2_UW_ENABLE 0x00000010 |
||||
#define TLB_WORD2_UW_DISABLE 0x00000000 |
||||
#define TLB_WORD2_UR_MASK 0x00000008 |
||||
#define TLB_WORD2_UR_ENABLE 0x00000008 |
||||
#define TLB_WORD2_UR_DISABLE 0x00000000 |
||||
#define TLB_WORD2_SX_MASK 0x00000004 |
||||
#define TLB_WORD2_SX_ENABLE 0x00000004 |
||||
#define TLB_WORD2_SX_DISABLE 0x00000000 |
||||
#define TLB_WORD2_SW_MASK 0x00000002 |
||||
#define TLB_WORD2_SW_ENABLE 0x00000002 |
||||
#define TLB_WORD2_SW_DISABLE 0x00000000 |
||||
#define TLB_WORD2_SR_MASK 0x00000001 |
||||
#define TLB_WORD2_SR_ENABLE 0x00000001 |
||||
#define TLB_WORD2_SR_DISABLE 0x00000000 |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| Board specific defines. |
||||
+----------------------------------------------------------------------------*/ |
||||
#define NONCACHE_MEMORY_SIZE (64*1024) |
||||
#define NONCACHE_AREA0_ENDOFFSET (64*1024) |
||||
#define NONCACHE_AREA1_ENDOFFSET (32*1024) |
||||
|
||||
#define FLASH_SECTORSIZE 0x00010000 |
||||
|
||||
/* SDRAM MICRON */ |
||||
#define SDRAM_MICRON 0x2C |
||||
|
||||
#define SDRAM_TRUE 1 |
||||
#define SDRAM_FALSE 0 |
||||
#define SDRAM_DDR1 1 |
||||
#define SDRAM_DDR2 2 |
||||
#define SDRAM_NONE 0 |
||||
#define MAXDIMMS 2 /* Changes le 12/01/05 pour 1.6 */ |
||||
#define MAXRANKS 4 /* Changes le 12/01/05 pour 1.6 */ |
||||
#define MAXBANKSPERDIMM 2 |
||||
#define MAXRANKSPERDIMM 2 |
||||
#define MAXBXCF 4 /* Changes le 12/01/05 pour 1.6 */ |
||||
#define MAXSDRAMMEMORY 0xFFFFFFFF /* 4GB */ |
||||
#define ERROR_STR_LENGTH 256 |
||||
#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */ |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| SDR Configuration registers |
||||
+----------------------------------------------------------------------------*/ |
||||
/* Serial Device Strap Reg 0 */ |
||||
#define sdr_pstrp0 0x0040 |
||||
|
||||
#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00000080 /* EBC Boot bus width Mask */ |
||||
#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00000080 /* EBC 16 Bits */ |
||||
#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */ |
||||
|
||||
#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00080000 /* Boot device Selection Mask */ |
||||
#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */ |
||||
#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00080000 /* PCI */ |
||||
|
||||
#define SDR0_SDSTP1_EBC_SIZE_MASK 0x00000060 /* Boot rom size Mask */ |
||||
#define SDR0_SDSTP1_BOOT_SIZE_16MB 0x00000060 /* 16 MB */ |
||||
#define SDR0_SDSTP1_BOOT_SIZE_8MB 0x00000040 /* 8 MB */ |
||||
#define SDR0_SDSTP1_BOOT_SIZE_4MB 0x00000020 /* 4 MB */ |
||||
#define SDR0_SDSTP1_BOOT_SIZE_2MB 0x00000000 /* 2 MB */ |
||||
|
||||
/* Serial Device Enabled - Addr = 0xA8 */ |
||||
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 |
||||
/* Serial Device Enabled - Addr = 0xA4 */ |
||||
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 |
||||
|
||||
/* Pin Straps Reg */ |
||||
#define SDR0_PSTRP0 0x0040 |
||||
#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ |
||||
|
||||
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ |
||||
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ |
||||
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ |
||||
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ |
||||
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ |
||||
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ |
||||
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ |
||||
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ |
||||
|
||||
/* fpgareg - defines are in include/config/YUCCA.h */ |
||||
|
||||
#define SDR0_CUST0_ENET3_MASK 0x00000080 |
||||
#define SDR0_CUST0_ENET3_COPPER 0x00000000 |
||||
#define SDR0_CUST0_ENET3_FIBER 0x00000080 |
||||
#define SDR0_CUST0_RGMII3_MASK 0x00000070 |
||||
#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) |
||||
#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) |
||||
#define SDR0_CUST0_RGMII3_DISAB 0x00000000 |
||||
#define SDR0_CUST0_RGMII3_RTBI 0x00000040 |
||||
#define SDR0_CUST0_RGMII3_RGMII 0x00000050 |
||||
#define SDR0_CUST0_RGMII3_TBI 0x00000060 |
||||
#define SDR0_CUST0_RGMII3_GMII 0x00000070 |
||||
#define SDR0_CUST0_ENET2_MASK 0x00000008 |
||||
#define SDR0_CUST0_ENET2_COPPER 0x00000000 |
||||
#define SDR0_CUST0_ENET2_FIBER 0x00000008 |
||||
#define SDR0_CUST0_RGMII2_MASK 0x00000007 |
||||
#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) |
||||
#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) |
||||
#define SDR0_CUST0_RGMII2_DISAB 0x00000000 |
||||
#define SDR0_CUST0_RGMII2_RTBI 0x00000004 |
||||
#define SDR0_CUST0_RGMII2_RGMII 0x00000005 |
||||
#define SDR0_CUST0_RGMII2_TBI 0x00000006 |
||||
#define SDR0_CUST0_RGMII2_GMII 0x00000007 |
||||
|
||||
#define ONE_MILLION 1000000 |
||||
#define ONE_BILLION 1000000000 |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| X |
||||
| XX |
||||
| XX XXX XXXXX XX XXX XXXXX |
||||
| XX XX X XXX XX XX |
||||
| XX XX XXXXXX XX XX |
||||
| XX XX X XX XX XX XX |
||||
| XXX XX XXXXX X XXXX XXX |
||||
+----------------------------------------------------------------------------*/ |
||||
/*----------------------------------------------------------------------------+
|
||||
| Declare Configuration values |
||||
+----------------------------------------------------------------------------*/ |
||||
|
||||
typedef enum config_selection { |
||||
CONFIG_NOT_SELECTED, |
||||
CONFIG_SELECTED |
||||
} config_selection_t; |
||||
|
||||
typedef enum config_list { |
||||
UART2_IN_SERVICE_MODE, |
||||
CPU_TRACE_MODE, |
||||
UART1_CTS_RTS, |
||||
CONFIG_NB |
||||
} config_list_t; |
||||
|
||||
#define MAX_CONFIG_SELECT_NB 3 |
||||
|
||||
#define BOARD_INFO_UART2_IN_SERVICE_MODE 1 |
||||
#define BOARD_INFO_CPU_TRACE_MODE 2 |
||||
#define BOARD_INFO_UART1_CTS_RTS_MODE 4 |
||||
|
||||
void force_bup_config_selection(config_selection_t *confgi_select_P); |
||||
void update_config_selection_table(config_selection_t *config_select_P); |
||||
void display_config_selection(config_selection_t *config_select_P); |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| XX |
||||
| |
||||
| XXXX XX XXX XXX XXXX |
||||
| XX XX XX XX XX XX |
||||
| XX XXX XX XX XX XX XX |
||||
| XX XX XXXXX XX XX XX |
||||
| XXXX XX XXXX XXXX |
||||
| XXXX |
||||
| |
||||
| |
||||
| |
||||
| +------------------------------------------------------------------+ |
||||
| | GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O | |
||||
| +----------------------+------------------+-----+------------+-----+ |
||||
| | | | | | | |
||||
| | GPIO0_0 | PCIX0REQ2_N | I/O | TRCCLK | | |
||||
| | GPIO0_1 | PCIX0REQ3_N | I/O | TRCBS0 | | |
||||
| | GPIO0_2 | PCIX0GNT2_N | I/O | TRCBS1 | | |
||||
| | GPIO0_3 | PCIX0GNT3_N | I/O | TRCBS2 | | |
||||
| | GPIO0_4 | PCIX1REQ2_N | I/O | TRCES0 | | |
||||
| | GPIO0_5 | PCIX1REQ3_N | I/O | TRCES1 | | |
||||
| | GPIO0_6 | PCIX1GNT2_N | I/O | TRCES2 | NA | |
||||
| | GPIO0_7 | PCIX1GNT3_N | I/O | TRCES3 | NA | |
||||
| | GPIO0_8 | PERREADY | I | TRCES4 | NA | |
||||
| | GPIO0_9 | PERCS1_N | O | TRCTS0 | NA | |
||||
| | GPIO0_10 | PERCS2_N | O | TRCTS1 | NA | |
||||
| | GPIO0_11 | IRQ0 | I | TRCTS2 | NA | |
||||
| | GPIO0_12 | IRQ1 | I | TRCTS3 | NA | |
||||
| | GPIO0_13 | IRQ2 | I | TRCTS4 | NA | |
||||
| | GPIO0_14 | IRQ3 | I | TRCTS5 | NA | |
||||
| | GPIO0_15 | IRQ4 | I | TRCTS6 | NA | |
||||
| | GPIO0_16 | IRQ5 | I | UART2RX | I | |
||||
| | GPIO0_17 | PERBE0_N | O | UART2TX | O | |
||||
| | GPIO0_18 | PCI0GNT0_N | I/O | NA | NA | |
||||
| | GPIO0_19 | PCI0GNT1_N | I/O | NA | NA | |
||||
| | GPIO0_20 | PCI0REQ0_N | I/O | NA | NA | |
||||
| | GPIO0_21 | PCI0REQ1_N | I/O | NA | NA | |
||||
| | GPIO0_22 | PCI1GNT0_N | I/O | NA | NA | |
||||
| | GPIO0_23 | PCI1GNT1_N | I/O | NA | NA | |
||||
| | GPIO0_24 | PCI1REQ0_N | I/O | NA | NA | |
||||
| | GPIO0_25 | PCI1REQ1_N | I/O | NA | NA | |
||||
| | GPIO0_26 | PCI2GNT0_N | I/O | NA | NA | |
||||
| | GPIO0_27 | PCI2GNT1_N | I/O | NA | NA | |
||||
| | GPIO0_28 | PCI2REQ0_N | I/O | NA | NA | |
||||
| | GPIO0_29 | PCI2REQ1_N | I/O | NA | NA | |
||||
| | GPIO0_30 | UART1RX | I | NA | NA | |
||||
| | GPIO0_31 | UART1TX | O | NA | NA | |
||||
| | | | | | | |
||||
| +----------------------+------------------+-----+------------+-----+ |
||||
| |
||||
+----------------------------------------------------------------------------*/ |
||||
|
||||
#define GPIO_MAX 32 |
||||
#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ |
||||
#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ |
||||
#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ |
||||
#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ |
||||
#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ |
||||
/* For the other GPIO number, you must shift */ |
||||
/*----------------------------------------------------------------------------+
|
||||
| Declare GPIO Configuration values |
||||
+----------------------------------------------------------------------------*/ |
||||
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; |
||||
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; |
||||
|
||||
typedef struct { |
||||
unsigned long add; /* gpio core base address */ |
||||
gpio_driver_t in_out; /* Driver Setting */ |
||||
gpio_select_t alt_nb; /* Selected Alternate */ |
||||
} gpio_param_s; |
||||
|
||||
unsigned long auto_calc_speed(void); |
||||
/*----------------------------------------------------------------------------+
|
||||
| Prototypes |
||||
+----------------------------------------------------------------------------*/ |
||||
void print_evb440spe_info(void); |
||||
|
||||
int onboard_pci_arbiter_selected(int core_pci); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
#endif /* __YUCCA_H_ */ |
@ -0,0 +1,518 @@ |
||||
/*
|
||||
* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* 1 january 2005 Alain Saurel <asaurel@amcc.com> |
||||
* Adapted to current Das U-Boot source |
||||
***********************************************************************/ |
||||
/************************************************************************
|
||||
* yucca.h - configuration for AMCC 440SPe Ref (yucca) |
||||
***********************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define DEBUG |
||||
#undef DEBUG |
||||
|
||||
#define CONFIG_IDENT_STRING "\nU_440SPe_V1R01 level06" |
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_440 1 /* ... PPC440 family */ |
||||
#define CONFIG_440SPE 1 /* Specifc SPe support */ |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
#undef CFG_DRAM_TEST /* Disable-takes long time */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
||||
#define EXTCLK_33_33 33333333 |
||||
#define EXTCLK_66_66 66666666 |
||||
#define EXTCLK_50 50000000 |
||||
#define EXTCLK_83 83333333 |
||||
|
||||
#define CONFIG_IBM_EMAC4_V4 1 |
||||
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
||||
#undef CONFIG_SHOW_BOOT_PROGRESS |
||||
#undef CONFIG_STRESS |
||||
#undef ENABLE_ECC |
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ |
||||
#define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */ |
||||
#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ |
||||
#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ |
||||
|
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
||||
#define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */ |
||||
#define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */ |
||||
#define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */ |
||||
|
||||
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ |
||||
#define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/ |
||||
|
||||
/* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */ |
||||
/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */ |
||||
/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */ |
||||
|
||||
#define CFG_FPGA_BASE 0xe2000000 /* epld */ |
||||
#define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ |
||||
|
||||
/* #define CFG_NVRAM_BASE_ADDR 0x08000000 */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_TEMP_STACK_OCM 1 |
||||
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE |
||||
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) |
||||
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR |
||||
|
||||
#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SERIAL_MULTI 1 |
||||
#undef CONFIG_UART1_CONSOLE |
||||
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#undef CFG_EXT_SERIAL_CLOCK |
||||
/* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ |
||||
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses */ |
||||
#define IIC0_DIMM0_ADDR 0x53 |
||||
#define IIC0_DIMM1_ADDR 0x52 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define IIC0_BOOTPROM_ADDR 0x50 |
||||
#define IIC0_ALT_BOOTPROM_ADDR 0x54 |
||||
|
||||
/* Don't probe these addrs */ |
||||
#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54} |
||||
|
||||
/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */ |
||||
/* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ |
||||
/* #endif */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
/* #define CFG_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */ |
||||
|
||||
#undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ |
||||
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ |
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200n8 root=/dev/nfs rw" |
||||
#define CONFIG_BOOTCOMMAND "bootm E7C00000" /* autoboot command */ |
||||
#define CONFIG_BOOTDELAY -1 /* -1 to disable autoboot */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#undef CONFIG_NET_MULTI |
||||
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
||||
#define CONFIG_PHY_RESET_DELAY 1000 |
||||
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ |
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
#define CONFIG_NETMASK 255.255.0.0 |
||||
#define CONFIG_IPADDR 192.168.80.10 |
||||
#define CONFIG_ETHADDR 00:04:AC:01:CA:FE |
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
||||
#define CONFIG_SERVERIP 192.168.1.1 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"loads_echo=1\0" \
|
||||
"netdev=eth0\0" \
|
||||
"hostname=yucca\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk-4.0/ppc_4xx\0" \
|
||||
"bootfile=yucca/uImage\0" \
|
||||
"kernel_addr=E7F10000\0" \
|
||||
"ramdisk_addr=E7F20000\0" \
|
||||
"load=tftp 100000 yuca/u-boot.bin\0" \
|
||||
"update=protect off 2:4-7;era 2:4-7;" \
|
||||
"cp.b ${fileaddr} fffc0000 ${filesize};" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_FLASH_ADDR0 0x5555 |
||||
#define CFG_FLASH_ADDR1 0x2aaa |
||||
#define CFG_FLASH_WORD_SIZE unsigned char |
||||
|
||||
#define CFG_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */ |
||||
#define CFG_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
||||
#define CFG_ENV_ADDR 0xfffa0000 |
||||
/* #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */ |
||||
#define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */ |
||||
#endif /* CFG_ENV_IS_IN_FLASH */ |
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW i /* show pci devices on startup */ |
||||
#undef CONFIG_PCI_CONFIG_HOST_BRIDGE |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ |
||||
#define CFG_PCI_TARGET_INIT /* let board init pci target */ |
||||
#undef CFG_PCI_MASTER_INIT |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
||||
/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */ |
||||
|
||||
/*
|
||||
* NETWORK Support (PCI): |
||||
*/ |
||||
/* Support for Intel 82557/82559/82559ER chips. */ |
||||
#define CONFIG_EEPRO100 |
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/* FB Divisor selection */ |
||||
#define FPGA_FB_DIV_6 6 |
||||
#define FPGA_FB_DIV_10 10 |
||||
#define FPGA_FB_DIV_12 12 |
||||
#define FPGA_FB_DIV_20 20 |
||||
|
||||
/* VCO Divisor selection */ |
||||
#define FPGA_VCO_DIV_4 4 |
||||
#define FPGA_VCO_DIV_6 6 |
||||
#define FPGA_VCO_DIV_8 8 |
||||
#define FPGA_VCO_DIV_10 10 |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| FPGA registers and bit definitions |
||||
+----------------------------------------------------------------------------*/ |
||||
/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */ |
||||
/* TLB initialization makes it correspond to logical address 0xE2000000. */ |
||||
/* => Done init_chip.s in bootlib */ |
||||
#define FPGA_REG_BASE_ADDR 0xE2000000 |
||||
#define FPGA_GPIO_BASE_ADDR 0xE2010000 |
||||
#define FPGA_INT_BASE_ADDR 0xE2020000 |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| Display |
||||
+----------------------------------------------------------------------------*/ |
||||
#define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR |
||||
|
||||
#define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06) |
||||
#define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04) |
||||
#define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02) |
||||
#define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00) |
||||
/*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/ |
||||
/*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/ |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| ethernet/reset/boot Register 1 |
||||
+----------------------------------------------------------------------------*/ |
||||
#define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10) |
||||
|
||||
#define FPGA_REG10_10MHZ_ENABLE 0x8000 |
||||
#define FPGA_REG10_100MHZ_ENABLE 0x4000 |
||||
#define FPGA_REG10_GIGABIT_ENABLE 0x2000 |
||||
#define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/ |
||||
#define FPGA_REG10_RESET_ETH 0x0800 |
||||
#define FPGA_REG10_AUTO_NEG_DIS 0x0400 |
||||
#define FPGA_REG10_INTP_ETH 0x0200 |
||||
|
||||
#define FPGA_REG10_RESET_HISR 0x0080 |
||||
#define FPGA_REG10_ENABLE_DISPLAY 0x0040 |
||||
#define FPGA_REG10_RESET_SDRAM 0x0020 |
||||
#define FPGA_REG10_OPER_BOOT 0x0010 |
||||
#define FPGA_REG10_SRAM_BOOT 0x0008 |
||||
#define FPGA_REG10_SMALL_BOOT 0x0004 |
||||
#define FPGA_REG10_FORCE_COLA 0x0002 |
||||
#define FPGA_REG10_COLA_MANUAL 0x0001 |
||||
|
||||
#define FPGA_REG10_SDRAM_ENABLE 0x0020 |
||||
|
||||
#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/ |
||||
#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/ |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| MUX control |
||||
+----------------------------------------------------------------------------*/ |
||||
#define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12) |
||||
|
||||
#define FPGA_REG12_EBC_CTL 0x8000 |
||||
#define FPGA_REG12_UART1_CTS_RTS 0x4000 |
||||
#define FPGA_REG12_UART0_RX_ENABLE 0x2000 |
||||
#define FPGA_REG12_UART1_RX_ENABLE 0x1000 |
||||
#define FPGA_REG12_UART2_RX_ENABLE 0x0800 |
||||
#define FPGA_REG12_EBC_OUT_ENABLE 0x0400 |
||||
#define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200 |
||||
#define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100 |
||||
#define FPGA_REG12_GPIO_SELECT 0x0010 |
||||
#define FPGA_REG12_GPIO_CHREG 0x0008 |
||||
#define FPGA_REG12_GPIO_CLK_CHREG 0x0004 |
||||
#define FPGA_REG12_GPIO_OETRI 0x0002 |
||||
#define FPGA_REG12_EBC_ERROR 0x0001 |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| PCI Clock control |
||||
+----------------------------------------------------------------------------*/ |
||||
#define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16) |
||||
|
||||
#define FPGA_REG16_PCI_CLK_CTL0 0x8000 |
||||
#define FPGA_REG16_PCI_CLK_CTL1 0x4000 |
||||
#define FPGA_REG16_PCI_CLK_CTL2 0x2000 |
||||
#define FPGA_REG16_PCI_CLK_CTL3 0x1000 |
||||
#define FPGA_REG16_PCI_CLK_CTL4 0x0800 |
||||
#define FPGA_REG16_PCI_CLK_CTL5 0x0400 |
||||
#define FPGA_REG16_PCI_CLK_CTL6 0x0200 |
||||
#define FPGA_REG16_PCI_CLK_CTL7 0x0100 |
||||
#define FPGA_REG16_PCI_CLK_CTL8 0x0080 |
||||
#define FPGA_REG16_PCI_CLK_CTL9 0x0040 |
||||
#define FPGA_REG16_PCI_EXT_ARB0 0x0020 |
||||
#define FPGA_REG16_PCI_MODE_1 0x0010 |
||||
#define FPGA_REG16_PCI_TARGET_MODE 0x0008 |
||||
#define FPGA_REG16_PCI_INTP_MODE 0x0004 |
||||
|
||||
/* FB1 Divisor selection */ |
||||
#define FPGA_REG16_FB2_DIV_MASK 0x1000 |
||||
#define FPGA_REG16_FB2_DIV_LOW 0x0000 |
||||
#define FPGA_REG16_FB2_DIV_HIGH 0x1000 |
||||
/* FB2 Divisor selection */ |
||||
/* S3 switch on Board */ |
||||
#define FPGA_REG16_FB1_DIV_MASK 0x2000 |
||||
#define FPGA_REG16_FB1_DIV_LOW 0x0000 |
||||
#define FPGA_REG16_FB1_DIV_HIGH 0x2000 |
||||
/* PCI0 Clock Selection */ |
||||
/* S3 switch on Board */ |
||||
#define FPGA_REG16_PCI0_CLK_MASK 0x0c00 |
||||
#define FPGA_REG16_PCI0_CLK_33_33 0x0000 |
||||
#define FPGA_REG16_PCI0_CLK_66_66 0x0800 |
||||
#define FPGA_REG16_PCI0_CLK_100 0x0400 |
||||
#define FPGA_REG16_PCI0_CLK_133_33 0x0c00 |
||||
/* VCO Divisor selection */ |
||||
/* S3 switch on Board */ |
||||
#define FPGA_REG16_VCO_DIV_MASK 0xc000 |
||||
#define FPGA_REG16_VCO_DIV_4 0x0000 |
||||
#define FPGA_REG16_VCO_DIV_8 0x4000 |
||||
#define FPGA_REG16_VCO_DIV_6 0x8000 |
||||
#define FPGA_REG16_VCO_DIV_10 0xc000 |
||||
/* Master Clock Selection */ |
||||
/* S3, S4 switches on Board */ |
||||
#define FPGA_REG16_MASTER_CLK_MASK 0x01c0 |
||||
#define FPGA_REG16_MASTER_CLK_EXT 0x0000 |
||||
#define FPGA_REG16_MASTER_CLK_66_66 0x0040 |
||||
#define FPGA_REG16_MASTER_CLK_50 0x0080 |
||||
#define FPGA_REG16_MASTER_CLK_33_33 0x00c0 |
||||
#define FPGA_REG16_MASTER_CLK_25 0x0100 |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| PCI Miscellaneous |
||||
+----------------------------------------------------------------------------*/ |
||||
#define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18) |
||||
|
||||
#define FPGA_REG18_PCI_PRSNT1 0x8000 |
||||
#define FPGA_REG18_PCI_PRSNT2 0x4000 |
||||
#define FPGA_REG18_PCI_INTA 0x2000 |
||||
#define FPGA_REG18_PCI_SLOT0_INTP 0x1000 |
||||
#define FPGA_REG18_PCI_SLOT1_INTP 0x0800 |
||||
#define FPGA_REG18_PCI_SLOT2_INTP 0x0400 |
||||
#define FPGA_REG18_PCI_SLOT3_INTP 0x0200 |
||||
#define FPGA_REG18_PCI_PCI0_VC 0x0100 |
||||
#define FPGA_REG18_PCI_PCI0_VTH1 0x0080 |
||||
#define FPGA_REG18_PCI_PCI0_VTH2 0x0040 |
||||
#define FPGA_REG18_PCI_PCI0_VTH3 0x0020 |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| PCIe Miscellaneous |
||||
+----------------------------------------------------------------------------*/ |
||||
#define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A) |
||||
|
||||
#define FPGA_REG1A_PE0_GLED 0x8000 |
||||
#define FPGA_REG1A_PE1_GLED 0x4000 |
||||
#define FPGA_REG1A_PE2_GLED 0x2000 |
||||
#define FPGA_REG1A_PE0_YLED 0x1000 |
||||
#define FPGA_REG1A_PE1_YLED 0x0800 |
||||
#define FPGA_REG1A_PE2_YLED 0x0400 |
||||
#define FPGA_REG1A_PE0_PWRON 0x0200 |
||||
#define FPGA_REG1A_PE1_PWRON 0x0100 |
||||
#define FPGA_REG1A_PE2_PWRON 0x0080 |
||||
#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040 |
||||
#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020 |
||||
#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010 |
||||
#define FPGA_REG1A_PE_SPREAD0 0x0008 |
||||
#define FPGA_REG1A_PE_SPREAD1 0x0004 |
||||
#define FPGA_REG1A_PE_SELSOURCE_0 0x0002 |
||||
#define FPGA_REG1A_PE_SELSOURCE_1 0x0001 |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| PCIe Miscellaneous |
||||
+----------------------------------------------------------------------------*/ |
||||
#define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C) |
||||
|
||||
#define FPGA_REG1C_PE0_ROOTPOINT 0x8000 |
||||
#define FPGA_REG1C_PE1_ENDPOINT 0x4000 |
||||
#define FPGA_REG1C_PE2_ENDPOINT 0x2000 |
||||
#define FPGA_REG1C_PE0_PRSNT 0x1000 |
||||
#define FPGA_REG1C_PE1_PRSNT 0x0800 |
||||
#define FPGA_REG1C_PE2_PRSNT 0x0400 |
||||
#define FPGA_REG1C_PE0_WAKE 0x0080 |
||||
#define FPGA_REG1C_PE1_WAKE 0x0040 |
||||
#define FPGA_REG1C_PE2_WAKE 0x0020 |
||||
#define FPGA_REG1C_PE0_PERST 0x0010 |
||||
#define FPGA_REG1C_PE1_PERST 0x0080 |
||||
#define FPGA_REG1C_PE2_PERST 0x0040 |
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| Defines |
||||
+----------------------------------------------------------------------------*/ |
||||
#define PERIOD_133_33MHZ 7500 /* 7,5ns */ |
||||
#define PERIOD_100_00MHZ 10000 /* 10ns */ |
||||
#define PERIOD_83_33MHZ 12000 /* 12ns */ |
||||
#define PERIOD_75_00MHZ 13333 /* 13,333ns */ |
||||
#define PERIOD_66_66MHZ 15000 /* 15ns */ |
||||
#define PERIOD_50_00MHZ 20000 /* 20ns */ |
||||
#define PERIOD_33_33MHZ 30000 /* 30ns */ |
||||
#define PERIOD_25_00MHZ 40000 /* 40ns */ |
||||
|
||||
/*---------------------------------------------------------------------------*/ |
||||
|
||||
#endif /* __CONFIG_H */ |
File diff suppressed because it is too large
Load Diff
Loading…
Reference in new issue