Vision Systems's Baltos is based on AM335x SoC from Texas Instruments. This patch adds support such Industrial PCs in mainline u-boot. [ balbi@ti.com: updated original patch to current u-boot ] Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Felipe Balbi <balbi@ti.com>master
Yegor Yefremov
10 years ago
committed by
Tom Rini
parent
c997da5c53
commit
6ce8932494
@ -0,0 +1,24 @@ |
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if TARGET_AM335X_BALTOS |
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config SYS_BOARD |
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default "baltos" |
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config SYS_VENDOR |
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default "vscom" |
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config SYS_SOC |
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default "am33xx" |
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config SYS_CONFIG_NAME |
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default "baltos" |
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config CONS_INDEX |
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int "UART used for console" |
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range 1 6 |
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default 1 |
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help |
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The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced |
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in documentation, etc) available to it. Depending on your specific |
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board you may want something other than UART0. |
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endif |
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@ -0,0 +1,13 @@ |
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#
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# Makefile
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#
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# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) |
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obj-y := mux.o
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endif |
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obj-y += board.o
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@ -0,0 +1 @@ |
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BSP for VScom OnRISC Balios family devices, like Balios iR 5221. |
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@ -0,0 +1,474 @@ |
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/*
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* board.c |
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* |
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* Board functions for TI AM335X based boards |
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* |
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <errno.h> |
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#include <spl.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/omap.h> |
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#include <asm/arch/ddr_defs.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/mmc_host_def.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/mem.h> |
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#include <asm/arch/mux.h> |
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#include <asm/io.h> |
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#include <asm/emif.h> |
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#include <asm/gpio.h> |
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#include <i2c.h> |
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#include <miiphy.h> |
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#include <cpsw.h> |
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#include <power/tps65217.h> |
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#include <power/tps65910.h> |
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#include <environment.h> |
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#include <watchdog.h> |
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#include "board.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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/* GPIO that controls power to DDR on EVM-SK */ |
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#define GPIO_DDR_VTT_EN 7 |
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#define DIP_S1 44 |
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
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static int baltos_set_console(void) |
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{ |
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int val, i, dips = 0; |
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char buf[7]; |
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for (i = 0; i < 4; i++) { |
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sprintf(buf, "dip_s%d", i + 1); |
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if (gpio_request(DIP_S1 + i, buf)) { |
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printf("failed to export GPIO %d\n", DIP_S1 + i); |
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return 0; |
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} |
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if (gpio_direction_input(DIP_S1 + i)) { |
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printf("failed to set GPIO %d direction\n", DIP_S1 + i); |
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return 0; |
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} |
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val = gpio_get_value(DIP_S1 + i); |
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dips |= val << i; |
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} |
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printf("DIPs: 0x%1x\n", (~dips) & 0xf); |
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if ((dips & 0xf) == 0xe) |
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setenv("console", "ttyUSB0,115200n8"); |
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return 0; |
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} |
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static int read_eeprom(BSP_VS_HWPARAM *header) |
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{ |
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i2c_set_bus_num(1); |
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/* Check if baseboard eeprom is available */ |
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { |
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puts("Could not probe the EEPROM; something fundamentally " |
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"wrong on the I2C bus.\n"); |
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return -ENODEV; |
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} |
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/* read the eeprom using i2c */ |
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, |
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sizeof(BSP_VS_HWPARAM))) { |
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puts("Could not read the EEPROM; something fundamentally" |
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" wrong on the I2C bus.\n"); |
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return -EIO; |
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} |
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if (header->Magic != 0xDEADBEEF) { |
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printf("Incorrect magic number (0x%x) in EEPROM\n", |
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header->Magic); |
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/* fill default values */ |
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header->SystemId = 211; |
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header->MAC1[0] = 0x00; |
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header->MAC1[1] = 0x00; |
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header->MAC1[2] = 0x00; |
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header->MAC1[3] = 0x00; |
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header->MAC1[4] = 0x00; |
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header->MAC1[5] = 0x01; |
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header->MAC2[0] = 0x00; |
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header->MAC2[1] = 0x00; |
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header->MAC2[2] = 0x00; |
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header->MAC2[3] = 0x00; |
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header->MAC2[4] = 0x00; |
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header->MAC2[5] = 0x02; |
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header->MAC3[0] = 0x00; |
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header->MAC3[1] = 0x00; |
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header->MAC3[2] = 0x00; |
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header->MAC3[3] = 0x00; |
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header->MAC3[4] = 0x00; |
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header->MAC3[5] = 0x03; |
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} |
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return 0; |
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} |
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#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) |
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static const struct ddr_data ddr3_baltos_data = { |
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.datardsratio0 = MT41K256M16HA125E_RD_DQS, |
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS, |
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, |
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, |
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}; |
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static const struct cmd_control ddr3_baltos_cmd_ctrl_data = { |
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.cmd0csratio = MT41K256M16HA125E_RATIO, |
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
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.cmd1csratio = MT41K256M16HA125E_RATIO, |
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
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.cmd2csratio = MT41K256M16HA125E_RATIO, |
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
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}; |
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static struct emif_regs ddr3_baltos_emif_reg_data = { |
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG, |
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, |
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, |
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, |
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, |
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.zq_config = MT41K256M16HA125E_ZQ_CFG, |
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, |
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}; |
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#ifdef CONFIG_SPL_OS_BOOT |
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int spl_start_uboot(void) |
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{ |
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/* break into full u-boot on 'c' */ |
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return (serial_tstc() && serial_getc() == 'c'); |
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} |
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#endif |
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#define OSC (V_OSCK/1000000) |
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const struct dpll_params dpll_ddr = { |
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266, OSC-1, 1, -1, -1, -1, -1}; |
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const struct dpll_params dpll_ddr_evm_sk = { |
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303, OSC-1, 1, -1, -1, -1, -1}; |
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const struct dpll_params dpll_ddr_baltos = { |
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400, OSC-1, 1, -1, -1, -1, -1}; |
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void am33xx_spl_board_init(void) |
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{ |
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int mpu_vdd; |
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int sil_rev; |
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/* Get the frequency */ |
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dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); |
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/*
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* The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all |
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* MPU frequencies we support we use a CORE voltage of |
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* 1.1375V. For MPU voltage we need to switch based on |
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* the frequency we are running at. |
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*/ |
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i2c_set_bus_num(1); |
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if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) { |
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puts("i2c: cannot access TPS65910\n"); |
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return; |
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} |
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/*
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* Depending on MPU clock and PG we will need a different |
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* VDD to drive at that speed. |
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*/ |
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sil_rev = readl(&cdev->deviceid) >> 28; |
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mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, |
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dpll_mpu_opp100.m); |
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/* Tell the TPS65910 to use i2c */ |
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tps65910_set_i2c_control(); |
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/* First update MPU voltage. */ |
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if (tps65910_voltage_update(MPU, mpu_vdd)) |
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return; |
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/* Second, update the CORE voltage. */ |
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if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) |
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return; |
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/* Set CORE Frequencies to OPP100 */ |
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); |
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/* Set MPU Frequency to what we detected now that voltages are set */ |
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); |
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writel(0x000010ff, PRM_DEVICE_INST + 4); |
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} |
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const struct dpll_params *get_dpll_ddr_params(void) |
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{ |
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enable_i2c1_pin_mux(); |
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i2c_set_bus_num(1); |
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return &dpll_ddr_baltos; |
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} |
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void set_uart_mux_conf(void) |
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{ |
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enable_uart0_pin_mux(); |
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} |
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void set_mux_conf_regs(void) |
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{ |
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enable_board_pin_mux(); |
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} |
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const struct ctrl_ioregs ioregs_baltos = { |
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
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}; |
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void sdram_init(void) |
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{ |
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gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); |
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gpio_direction_output(GPIO_DDR_VTT_EN, 1); |
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config_ddr(400, &ioregs_baltos, |
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&ddr3_baltos_data, |
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&ddr3_baltos_cmd_ctrl_data, |
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&ddr3_baltos_emif_reg_data, 0); |
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} |
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#endif |
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/*
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* Basic board specific setup. Pinmux has been handled already. |
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*/ |
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int board_init(void) |
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{ |
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#if defined(CONFIG_HW_WATCHDOG) |
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hw_watchdog_init(); |
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#endif |
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
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#if defined(CONFIG_NOR) || defined(CONFIG_NAND) |
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gpmc_init(); |
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#endif |
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return 0; |
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} |
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int ft_board_setup(void *blob, bd_t *bd) |
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{ |
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int node, ret; |
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unsigned char mac_addr[6]; |
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BSP_VS_HWPARAM header; |
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/* get production data */ |
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if (read_eeprom(&header)) |
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return 0; |
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/* setup MAC1 */ |
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mac_addr[0] = header.MAC1[0]; |
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mac_addr[1] = header.MAC1[1]; |
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mac_addr[2] = header.MAC1[2]; |
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mac_addr[3] = header.MAC1[3]; |
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mac_addr[4] = header.MAC1[4]; |
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mac_addr[5] = header.MAC1[5]; |
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node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200"); |
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if (node < 0) { |
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printf("no /soc/fman/ethernet path offset\n"); |
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return -ENODEV; |
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} |
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ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); |
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if (ret) { |
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printf("error setting local-mac-address property\n"); |
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return -ENODEV; |
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} |
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/* setup MAC2 */ |
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mac_addr[0] = header.MAC2[0]; |
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mac_addr[1] = header.MAC2[1]; |
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mac_addr[2] = header.MAC2[2]; |
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mac_addr[3] = header.MAC2[3]; |
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mac_addr[4] = header.MAC2[4]; |
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mac_addr[5] = header.MAC2[5]; |
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node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300"); |
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if (node < 0) { |
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printf("no /soc/fman/ethernet path offset\n"); |
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return -ENODEV; |
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} |
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ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); |
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if (ret) { |
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printf("error setting local-mac-address property\n"); |
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return -ENODEV; |
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} |
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printf("\nFDT was successfully setup\n"); |
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return 0; |
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} |
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static struct module_pin_mux dip_pin_mux[] = { |
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{OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */ |
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{OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */ |
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{OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */ |
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{OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */ |
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{-1}, |
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}; |
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#ifdef CONFIG_BOARD_LATE_INIT |
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int board_late_init(void) |
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{ |
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
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BSP_VS_HWPARAM header; |
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char model[4]; |
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/* get production data */ |
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if (read_eeprom(&header)) { |
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sprintf(model, "211"); |
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} else { |
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sprintf(model, "%d", header.SystemId); |
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if (header.SystemId == 215) { |
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configure_module_pin_mux(dip_pin_mux); |
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baltos_set_console(); |
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} |
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} |
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setenv("board_name", model); |
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#endif |
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return 0; |
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} |
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#endif |
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
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static void cpsw_control(int enabled) |
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{ |
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/* VTP can be added here */ |
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return; |
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} |
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static struct cpsw_slave_data cpsw_slaves[] = { |
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{ |
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.slave_reg_ofs = 0x208, |
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.sliver_reg_ofs = 0xd80, |
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.phy_addr = 0, |
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}, |
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{ |
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.slave_reg_ofs = 0x308, |
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.sliver_reg_ofs = 0xdc0, |
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.phy_addr = 7, |
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}, |
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}; |
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static struct cpsw_platform_data cpsw_data = { |
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.mdio_base = CPSW_MDIO_BASE, |
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.cpsw_base = CPSW_BASE, |
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.mdio_div = 0xff, |
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.channels = 8, |
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.cpdma_reg_ofs = 0x800, |
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.slaves = 2, |
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.slave_data = cpsw_slaves, |
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.active_slave = 1, |
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.ale_reg_ofs = 0xd00, |
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.ale_entries = 1024, |
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.host_port_reg_ofs = 0x108, |
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.hw_stats_reg_ofs = 0x900, |
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.bd_ram_ofs = 0x2000, |
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.mac_control = (1 << 5), |
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.control = cpsw_control, |
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.host_port_num = 0, |
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.version = CPSW_CTRL_VERSION_2, |
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}; |
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#endif |
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#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ |
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&& defined(CONFIG_SPL_BUILD)) || \
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((defined(CONFIG_DRIVER_TI_CPSW) || \
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defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
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!defined(CONFIG_SPL_BUILD)) |
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int board_eth_init(bd_t *bis) |
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{ |
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int rv, n = 0; |
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uint8_t mac_addr[6]; |
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uint32_t mac_hi, mac_lo; |
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__maybe_unused struct am335x_baseboard_id header; |
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/*
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* Note here that we're using CPSW1 since that has a 1Gbit PHY while |
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* CSPW0 has a 100Mbit PHY. |
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* |
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* On product, CPSW1 maps to port labeled WAN. |
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*/ |
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/* try reading mac address from efuse */ |
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mac_lo = readl(&cdev->macid1l); |
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mac_hi = readl(&cdev->macid1h); |
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mac_addr[0] = mac_hi & 0xFF; |
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mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
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mac_addr[4] = mac_lo & 0xFF; |
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mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
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if (!getenv("ethaddr")) { |
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printf("<ethaddr> not set. Validating first E-fuse MAC\n"); |
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if (is_valid_ethaddr(mac_addr)) |
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eth_setenv_enetaddr("ethaddr", mac_addr); |
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} |
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#ifdef CONFIG_DRIVER_TI_CPSW |
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writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel); |
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cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; |
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rv = cpsw_register(&cpsw_data); |
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if (rv < 0) |
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printf("Error %d registering CPSW switch\n", rv); |
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else |
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n += rv; |
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#endif |
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/*
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* |
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* CPSW RGMII Internal Delay Mode is not supported in all PVT |
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* operating points. So we must set the TX clock delay feature |
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* in the AR8051 PHY. Since we only support a single ethernet |
||||
* device in U-Boot, we only do this for the first instance. |
||||
*/ |
||||
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d |
||||
#define AR8051_PHY_DEBUG_DATA_REG 0x1e |
||||
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 |
||||
#define AR8051_RGMII_TX_CLK_DLY 0x100 |
||||
const char *devname; |
||||
devname = miiphy_get_current_dev(); |
||||
|
||||
miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG, |
||||
AR8051_DEBUG_RGMII_CLK_DLY_REG); |
||||
miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG, |
||||
AR8051_RGMII_TX_CLK_DLY); |
||||
#endif |
||||
return n; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,90 @@ |
||||
/*
|
||||
* board.h |
||||
* |
||||
* TI AM335x boards information header |
||||
* |
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _BOARD_H_ |
||||
#define _BOARD_H_ |
||||
|
||||
/*
|
||||
* TI AM335x parts define a system EEPROM that defines certain sub-fields. |
||||
* We use these fields to in turn see what board we are on, and what |
||||
* that might require us to set or not set. |
||||
*/ |
||||
#define HDR_NO_OF_MAC_ADDR 3 |
||||
#define HDR_ETH_ALEN 6 |
||||
#define HDR_NAME_LEN 8 |
||||
|
||||
struct am335x_baseboard_id { |
||||
unsigned int magic; |
||||
char name[HDR_NAME_LEN]; |
||||
char version[4]; |
||||
char serial[12]; |
||||
char config[32]; |
||||
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; |
||||
}; |
||||
|
||||
typedef struct _BSP_VS_HWPARAM // v1.0
|
||||
{ |
||||
uint32_t Magic; |
||||
uint32_t HwRev; |
||||
uint32_t SerialNumber; |
||||
char PrdDate[11]; // as a string ie. "01.01.2006"
|
||||
uint16_t SystemId; |
||||
uint8_t MAC1[6]; // internal EMAC
|
||||
uint8_t MAC2[6]; // SMSC9514
|
||||
uint8_t MAC3[6]; // WL1271 WLAN
|
||||
} __attribute__ ((packed)) BSP_VS_HWPARAM; |
||||
|
||||
static inline int board_is_bone(struct am335x_baseboard_id *header) |
||||
{ |
||||
return !strncmp(header->name, "A335BONE", HDR_NAME_LEN); |
||||
} |
||||
|
||||
static inline int board_is_bone_lt(struct am335x_baseboard_id *header) |
||||
{ |
||||
return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN); |
||||
} |
||||
|
||||
static inline int board_is_evm_sk(struct am335x_baseboard_id *header) |
||||
{ |
||||
return !strncmp("A335X_SK", header->name, HDR_NAME_LEN); |
||||
} |
||||
|
||||
static inline int board_is_idk(struct am335x_baseboard_id *header) |
||||
{ |
||||
return !strncmp(header->config, "SKU#02", 6); |
||||
} |
||||
|
||||
static inline int board_is_gp_evm(struct am335x_baseboard_id *header) |
||||
{ |
||||
return !strncmp("A33515BB", header->name, HDR_NAME_LEN); |
||||
} |
||||
|
||||
static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header) |
||||
{ |
||||
return (board_is_gp_evm(header) && |
||||
strncmp("1.5", header->version, 3) <= 0); |
||||
} |
||||
|
||||
/*
|
||||
* We have three pin mux functions that must exist. We must be able to enable |
||||
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a |
||||
* main pinmux function that can be overridden to enable all other pinmux that |
||||
* is required on the board. |
||||
*/ |
||||
void enable_uart0_pin_mux(void); |
||||
void enable_uart1_pin_mux(void); |
||||
void enable_uart2_pin_mux(void); |
||||
void enable_uart3_pin_mux(void); |
||||
void enable_uart4_pin_mux(void); |
||||
void enable_uart5_pin_mux(void); |
||||
void enable_i2c0_pin_mux(void); |
||||
void enable_i2c1_pin_mux(void); |
||||
void enable_board_pin_mux(void); |
||||
#endif |
||||
@ -0,0 +1,194 @@ |
||||
/*
|
||||
* mux.c |
||||
* |
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation version 2. |
||||
* |
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
||||
* kind, whether express or implied; without even the implied warranty |
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/mux.h> |
||||
#include <asm/io.h> |
||||
#include <i2c.h> |
||||
#include "board.h" |
||||
|
||||
static struct module_pin_mux uart0_pin_mux[] = { |
||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ |
||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ |
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux uart1_pin_mux[] = { |
||||
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ |
||||
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ |
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux uart2_pin_mux[] = { |
||||
{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ |
||||
{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ |
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux uart3_pin_mux[] = { |
||||
{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ |
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ |
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux uart4_pin_mux[] = { |
||||
{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ |
||||
{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ |
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux uart5_pin_mux[] = { |
||||
{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ |
||||
{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ |
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux mmc0_pin_mux[] = { |
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ |
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ |
||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ |
||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ |
||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ |
||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ |
||||
//{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
|
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux i2c0_pin_mux[] = { |
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | |
||||
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ |
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | |
||||
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ |
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux i2c1_pin_mux[] = { |
||||
{OFFSET(spi0_d1), (MODE(2) | RXACTIVE | |
||||
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ |
||||
{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | |
||||
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ |
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux gpio0_7_pin_mux[] = { |
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ |
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux rmii1_pin_mux[] = { |
||||
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ |
||||
{OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */ |
||||
{OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */ |
||||
{OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */ |
||||
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ |
||||
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ |
||||
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */ |
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ |
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ |
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux rgmii2_pin_mux[] = { |
||||
{OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */ |
||||
{OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ |
||||
{OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */ |
||||
{OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */ |
||||
{OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */ |
||||
{OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */ |
||||
{OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */ |
||||
{OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ |
||||
{OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ |
||||
{OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ |
||||
{OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ |
||||
{OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ |
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ |
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ |
||||
{-1}, |
||||
}; |
||||
|
||||
static struct module_pin_mux nand_pin_mux[] = { |
||||
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ |
||||
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ |
||||
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ |
||||
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ |
||||
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ |
||||
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ |
||||
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ |
||||
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ |
||||
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ |
||||
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ |
||||
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ |
||||
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ |
||||
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ |
||||
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ |
||||
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ |
||||
{-1}, |
||||
}; |
||||
|
||||
void enable_uart0_pin_mux(void) |
||||
{ |
||||
configure_module_pin_mux(uart0_pin_mux); |
||||
} |
||||
|
||||
void enable_uart1_pin_mux(void) |
||||
{ |
||||
configure_module_pin_mux(uart1_pin_mux); |
||||
} |
||||
|
||||
void enable_uart2_pin_mux(void) |
||||
{ |
||||
configure_module_pin_mux(uart2_pin_mux); |
||||
} |
||||
|
||||
void enable_uart3_pin_mux(void) |
||||
{ |
||||
configure_module_pin_mux(uart3_pin_mux); |
||||
} |
||||
|
||||
void enable_uart4_pin_mux(void) |
||||
{ |
||||
configure_module_pin_mux(uart4_pin_mux); |
||||
} |
||||
|
||||
void enable_uart5_pin_mux(void) |
||||
{ |
||||
configure_module_pin_mux(uart5_pin_mux); |
||||
} |
||||
|
||||
void enable_i2c0_pin_mux(void) |
||||
{ |
||||
configure_module_pin_mux(i2c0_pin_mux); |
||||
} |
||||
|
||||
void enable_i2c1_pin_mux(void) |
||||
{ |
||||
configure_module_pin_mux(i2c1_pin_mux); |
||||
} |
||||
|
||||
void enable_board_pin_mux() |
||||
{ |
||||
/* Baltos */ |
||||
configure_module_pin_mux(i2c1_pin_mux); |
||||
configure_module_pin_mux(gpio0_7_pin_mux); |
||||
configure_module_pin_mux(rgmii2_pin_mux); |
||||
configure_module_pin_mux(rmii1_pin_mux); |
||||
configure_module_pin_mux(mmc0_pin_mux); |
||||
|
||||
#if defined(CONFIG_NAND) |
||||
configure_module_pin_mux(nand_pin_mux); |
||||
#endif |
||||
} |
||||
@ -0,0 +1,128 @@ |
||||
/* |
||||
* Copyright (c) 2004-2008 Texas Instruments |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
*(.__image_copy_start) |
||||
*(.vectors) |
||||
CPUDIR/start.o (.text*) |
||||
board/vscom/baltos/built-in.o (.text*) |
||||
*(.text*) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { |
||||
*(.data*) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
|
||||
. = .; |
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
|
||||
.image_copy_end : |
||||
{ |
||||
*(.__image_copy_end) |
||||
} |
||||
|
||||
.rel_dyn_start : |
||||
{ |
||||
*(.__rel_dyn_start) |
||||
} |
||||
|
||||
.rel.dyn : { |
||||
*(.rel*) |
||||
} |
||||
|
||||
.rel_dyn_end : |
||||
{ |
||||
*(.__rel_dyn_end) |
||||
} |
||||
|
||||
.hash : { *(.hash*) } |
||||
|
||||
.end : |
||||
{ |
||||
*(.__end) |
||||
} |
||||
|
||||
_image_binary_end = .; |
||||
|
||||
/* |
||||
* Deprecated: this MMU section is used by pxa at present but |
||||
* should not be used by new boards/CPUs. |
||||
*/ |
||||
. = ALIGN(4096); |
||||
.mmutable : { |
||||
*(.mmutable) |
||||
} |
||||
|
||||
/* |
||||
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c |
||||
* __bss_base and __bss_limit are for linker only (overlay ordering) |
||||
*/ |
||||
|
||||
.bss_start __rel_dyn_start (OVERLAY) : { |
||||
KEEP(*(.__bss_start)); |
||||
__bss_base = .; |
||||
} |
||||
|
||||
.bss __bss_base (OVERLAY) : { |
||||
*(.bss*) |
||||
. = ALIGN(4); |
||||
__bss_limit = .; |
||||
} |
||||
|
||||
.bss_end __bss_limit (OVERLAY) : { |
||||
KEEP(*(.__bss_end)); |
||||
} |
||||
|
||||
.dynsym _image_binary_end : { *(.dynsym) } |
||||
.dynbss : { *(.dynbss) } |
||||
.dynstr : { *(.dynstr*) } |
||||
.dynamic : { *(.dynamic*) } |
||||
.gnu.hash : { *(.gnu.hash) } |
||||
.plt : { *(.plt*) } |
||||
.interp : { *(.interp*) } |
||||
.gnu : { *(.gnu*) } |
||||
.ARM.exidx : { *(.ARM.exidx*) } |
||||
} |
||||
@ -0,0 +1,7 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_STACK_R=y |
||||
CONFIG_SPL_STACK_R_ADDR=0x82000000 |
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND" |
||||
CONFIG_CONS_INDEX=1 |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_AM335X_BALTOS=y |
||||
@ -0,0 +1,340 @@ |
||||
/*
|
||||
* am335x_evm.h |
||||
* |
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation version 2. |
||||
* |
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
||||
* kind, whether express or implied; without even the implied warranty |
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_BALTOS_H |
||||
#define __CONFIG_BALTOS_H |
||||
|
||||
#include <configs/ti_am335x_common.h> |
||||
|
||||
#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
/* Clock Defines */ |
||||
#define V_OSCK 24000000 /* Clock output from T2 */ |
||||
#define V_SCLK (V_OSCK) |
||||
|
||||
/* Custom script for NOR */ |
||||
#define CONFIG_SYS_LDSCRIPT "board/vscom/baltos/u-boot.lds" |
||||
|
||||
/* Always 128 KiB env size */ |
||||
#define CONFIG_ENV_SIZE (128 << 10) |
||||
|
||||
/* Enhance our eMMC support / experience. */ |
||||
#define CONFIG_CMD_GPT |
||||
#define CONFIG_EFI_PARTITION |
||||
#define CONFIG_PARTITION_UUIDS |
||||
#define CONFIG_CMD_PART |
||||
|
||||
/* FIT support */ |
||||
#define CONFIG_FIT |
||||
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ |
||||
#define CONFIG_OF_BOARD_SETUP |
||||
|
||||
/* UBI Support */ |
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_MTD_PARTITIONS |
||||
#define CONFIG_MTD_DEVICE |
||||
#define CONFIG_RBTREE |
||||
#define CONFIG_LZO |
||||
#define CONFIG_CMD_UBI |
||||
#define CONFIG_CMD_UBIFS |
||||
|
||||
/* I2C configuration */ |
||||
#undef CONFIG_SYS_OMAP24_I2C_SPEED |
||||
#define CONFIG_SYS_OMAP24_I2C_SPEED 10000 |
||||
|
||||
#ifdef CONFIG_NAND |
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 |
||||
#ifdef CONFIG_SPL_OS_BOOT |
||||
#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */ |
||||
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ |
||||
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 |
||||
#endif |
||||
#define NANDARGS \ |
||||
"mtdids=" MTDIDS_DEFAULT "\0" \
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"${mtdparts} " \
|
||||
"root=${nandroot} " \
|
||||
"rootfstype=${nandrootfstype}\0" \
|
||||
"nandroot=ubi0:rootfs rw ubi.mtd=5\0" \
|
||||
"nandrootfstype=ubifs rootwait=1\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"setenv loadaddr 0x84000000; " \
|
||||
"ubi part UBI; " \
|
||||
"ubifsmount ubi0:kernel; " \
|
||||
"ubifsload $loadaddr kernel-fit.itb;" \
|
||||
"ubifsumount; " \
|
||||
"bootm ${loadaddr}#conf${board_name}\0" |
||||
#else |
||||
#define NANDARGS "" |
||||
#endif |
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
||||
|
||||
#ifndef CONFIG_SPL_BUILD |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
DEFAULT_LINUX_BOOT_ENV \
|
||||
"boot_fdt=try\0" \
|
||||
"bootpart=0:2\0" \
|
||||
"bootdir=/boot\0" \
|
||||
"bootfile=zImage\0" \
|
||||
"fdtfile=undefined\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"partitions=" \
|
||||
"uuid_disk=${uuid_gpt_disk};" \
|
||||
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
|
||||
"optargs=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 ro\0" \
|
||||
"mmcrootfstype=ext4 rootwait\0" \
|
||||
"rootpath=/export/rootfs\0" \
|
||||
"nfsopts=nolock\0" \
|
||||
"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
|
||||
"::off\0" \
|
||||
"ramroot=/dev/ram0 rw\0" \
|
||||
"ramrootfstype=ext2\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"${mtdparts} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"spiroot=/dev/mtdblock4 rw\0" \
|
||||
"spirootfstype=jffs2\0" \
|
||||
"spisrcaddr=0xe0000\0" \
|
||||
"spiimgsize=0x362000\0" \
|
||||
"spibusno=0\0" \
|
||||
"spiargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${spiroot} " \
|
||||
"rootfstype=${spirootfstype}\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=/dev/nfs " \
|
||||
"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
|
||||
"ip=dhcp\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
"env import -t $loadaddr $filesize\0" \
|
||||
"ramargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${ramroot} " \
|
||||
"rootfstype=${ramrootfstype}\0" \
|
||||
"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
|
||||
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
|
||||
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
|
||||
"mmcloados=run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"mmcboot=mmc dev ${mmcdev}; " \
|
||||
"if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"if run loadbootenv; then " \
|
||||
"echo Loaded environment from ${bootenv};" \
|
||||
"run importbootenv;" \
|
||||
"fi;" \
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...;" \
|
||||
"run uenvcmd;" \
|
||||
"fi;" \
|
||||
"if run loadimage; then " \
|
||||
"run mmcloados;" \
|
||||
"fi;" \
|
||||
"fi;\0" \
|
||||
"spiboot=echo Booting from spi ...; " \
|
||||
"run spiargs; " \
|
||||
"sf probe ${spibusno}:0; " \
|
||||
"sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
|
||||
"bootz ${loadaddr}\0" \
|
||||
"netboot=echo Booting from network ...; " \
|
||||
"setenv autoload no; " \
|
||||
"dhcp; " \
|
||||
"tftp ${loadaddr} ${bootfile}; " \
|
||||
"tftp ${fdtaddr} ${fdtfile}; " \
|
||||
"run netargs; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0" \
|
||||
"ramboot=echo Booting from ramdisk ...; " \
|
||||
"run ramargs; " \
|
||||
"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
|
||||
"findfdt=setenv fdtfile am335x-baltos.dtb\0" \
|
||||
NANDARGS |
||||
/*DFUARGS*/ |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"run findfdt; " \
|
||||
"run mmcboot;" \
|
||||
"setenv mmcdev 1; " \
|
||||
"setenv bootpart 1:2; " \
|
||||
"run mmcboot;" \
|
||||
"run nandboot;" |
||||
|
||||
#define CONFIG_CMD_SAVEENV |
||||
#define CONFIG_CMD_NFS |
||||
|
||||
/* NS16550 Configuration */ |
||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ |
||||
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ |
||||
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ |
||||
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ |
||||
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ |
||||
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_ENV_EEPROM_IS_ON_I2C |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS |
||||
|
||||
/* PMIC support */ |
||||
#define CONFIG_POWER_TPS65910 |
||||
|
||||
/* SPL */ |
||||
#ifndef CONFIG_NOR_BOOT |
||||
#define CONFIG_SPL_POWER_SUPPORT |
||||
#define CONFIG_SPL_YMODEM_SUPPORT |
||||
|
||||
/* Bootcount using the RTC block */ |
||||
#define CONFIG_BOOTCOUNT_LIMIT |
||||
#define CONFIG_BOOTCOUNT_AM33XX |
||||
|
||||
/* USB gadget RNDIS */ |
||||
/*#define CONFIG_SPL_MUSB_NEW_SUPPORT*/ |
||||
|
||||
/* General network SPL, both CPSW and USB gadget RNDIS */ |
||||
/*#define CONFIG_SPL_NET_SUPPORT
|
||||
#define CONFIG_SPL_ENV_SUPPORT |
||||
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"*/ |
||||
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" |
||||
|
||||
#ifdef CONFIG_NAND |
||||
#define CONFIG_NAND_OMAP_GPMC |
||||
#define CONFIG_NAND_OMAP_ELM |
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE |
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ |
||||
CONFIG_SYS_NAND_PAGE_SIZE) |
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 2048 |
||||
#define CONFIG_SYS_NAND_OOBSIZE 64 |
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) |
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS |
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ |
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
26, 27, 28, 29, 30, 31, 32, 33, \
|
||||
34, 35, 36, 37, 38, 39, 40, 41, \
|
||||
42, 43, 44, 45, 46, 47, 48, 49, \
|
||||
50, 51, 52, 53, 54, 55, 56, 57, } |
||||
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512 |
||||
#define CONFIG_SYS_NAND_ECCBYTES 14 |
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION |
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW |
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
||||
#endif |
||||
#endif |
||||
|
||||
/*
|
||||
* USB configuration. We enable MUSB support, both for host and for |
||||
* gadget. We set USB0 as peripheral and USB1 as host, based on the |
||||
* board schematic and physical port wired to each. Then for host we |
||||
* add mass storage support and for gadget we add both RNDIS ethernet |
||||
* and DFU. |
||||
*/ |
||||
#define CONFIG_USB_MUSB_DSPS |
||||
#define CONFIG_ARCH_MISC_INIT |
||||
#define CONFIG_MUSB_GADGET |
||||
#define CONFIG_MUSB_PIO_ONLY |
||||
#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT |
||||
#define CONFIG_USB_GADGET |
||||
#define CONFIG_USBDOWNLOAD_GADGET |
||||
#define CONFIG_USB_GADGET_DUALSPEED |
||||
#define CONFIG_USB_GADGET_VBUS_DRAW 2 |
||||
#define CONFIG_MUSB_HOST |
||||
#define CONFIG_AM335X_USB0 |
||||
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL |
||||
#define CONFIG_AM335X_USB1 |
||||
#define CONFIG_AM335X_USB1_MODE MUSB_HOST |
||||
|
||||
#ifdef CONFIG_MUSB_HOST |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_USB_STORAGE |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MUSB_GADGET |
||||
#define CONFIG_USB_ETHER |
||||
#define CONFIG_USB_ETH_RNDIS |
||||
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" |
||||
|
||||
/* USB TI's IDs */ |
||||
#define CONFIG_G_DNL_VENDOR_NUM 0x0403 |
||||
#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 |
||||
#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" |
||||
#endif /* CONFIG_MUSB_GADGET */ |
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) |
||||
/* disable host part of MUSB in SPL */ |
||||
#undef CONFIG_MUSB_HOST |
||||
/* disable EFI partitions and partition UUID support */ |
||||
#undef CONFIG_PARTITION_UUIDS |
||||
#undef CONFIG_EFI_PARTITION |
||||
/*
|
||||
* Disable CPSW SPL support so we fit within the 101KiB limit. |
||||
*/ |
||||
#undef CONFIG_SPL_ETH_SUPPORT |
||||
#endif |
||||
|
||||
/* Network. */ |
||||
#define CONFIG_PHY_GIGE |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_ADDR 0 |
||||
#define CONFIG_PHY_SMSC |
||||
#define CONFIG_MII |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_PHY_ATHEROS |
||||
|
||||
/* NAND support */ |
||||
#ifdef CONFIG_NAND |
||||
#define CONFIG_CMD_NAND |
||||
#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 |
||||
#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) |
||||
#define MTDIDS_DEFAULT "nand0=omap2-nand.0" |
||||
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ |
||||
"128k(SPL.backup1)," \
|
||||
"128k(SPL.backup2)," \
|
||||
"128k(SPL.backup3)," \
|
||||
"1920k(u-boot)," \
|
||||
"-(UBI)" |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
#endif |
||||
#endif |
||||
|
||||
#endif /* ! __CONFIG_BALTOS_H */ |
||||
Loading…
Reference in new issue