Tom Rini
6 years ago
commit
6d0409f256
@ -0,0 +1,477 @@ |
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/*
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* board/renesas/stout/stout_spl.c |
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* |
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <dm/platform_data/serial_sh.h> |
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#include <asm/processor.h> |
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#include <asm/mach-types.h> |
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#include <asm/io.h> |
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#include <linux/errno.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/rmobile.h> |
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#include <asm/arch/rcar-mstp.h> |
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#include <spl.h> |
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#define TMU0_MSTP125 BIT(25) |
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#define SCIFA0_MSTP204 BIT(4) |
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#define QSPI_MSTP917 BIT(17) |
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#define SD2CKCR 0xE615026C |
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#define SD_97500KHZ 0x7 |
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struct reg_config { |
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u16 off; |
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u32 val; |
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}; |
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static void dbsc_wait(u16 reg) |
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{ |
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static const u32 dbsc3_0_base = DBSC3_0_BASE; |
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static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; |
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while (!(readl(dbsc3_0_base + reg) & BIT(0))) |
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; |
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while (!(readl(dbsc3_1_base + reg) & BIT(0))) |
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; |
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} |
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static void spl_init_sys(void) |
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{ |
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u32 r0 = 0; |
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writel(0xa5a5a500, 0xe6020004); |
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writel(0xa5a5a500, 0xe6030004); |
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asm volatile( |
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/* ICIALLU - Invalidate I$ to PoU */ |
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"mcr 15, 0, %0, cr7, cr5, 0 \n" |
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/* BPIALL - Invalidate branch predictors */ |
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"mcr 15, 0, %0, cr7, cr5, 6 \n" |
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/* Set SCTLR[IZ] */ |
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"mrc 15, 0, %0, cr1, cr0, 0 \n" |
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"orr %0, #0x1800 \n" |
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"mcr 15, 0, %0, cr1, cr0, 0 \n" |
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"isb sy \n" |
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:"=r"(r0)); |
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} |
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static void spl_init_pfc(void) |
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{ |
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static const struct reg_config pfc_with_unlock[] = { |
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{ 0x0090, 0x00140300 }, |
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{ 0x0094, 0x09500000 }, |
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{ 0x0098, 0xc0000084 }, |
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{ 0x0020, 0x01a33492 }, |
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{ 0x0024, 0x10000000 }, |
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{ 0x0028, 0x08449252 }, |
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{ 0x002c, 0x2925b322 }, |
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{ 0x0030, 0x0c311249 }, |
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{ 0x0034, 0x10124000 }, |
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{ 0x0038, 0x00001295 }, |
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{ 0x003c, 0x50890000 }, |
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{ 0x0040, 0x0eaa56aa }, |
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{ 0x0044, 0x55550000 }, |
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{ 0x0048, 0x00000005 }, |
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{ 0x004c, 0x54800000 }, |
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{ 0x0050, 0x3736db55 }, |
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{ 0x0054, 0x29148da3 }, |
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{ 0x0058, 0x48c446e1 }, |
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{ 0x005c, 0x2a3a54dc }, |
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{ 0x0160, 0x00000023 }, |
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{ 0x0004, 0xfca0ffff }, |
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{ 0x0008, 0x3fbffbf0 }, |
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{ 0x000c, 0x3ffdffff }, |
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{ 0x0010, 0x00ffffff }, |
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{ 0x0014, 0xfc3ffff3 }, |
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{ 0x0018, 0xe4fdfff7 }, |
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}; |
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static const struct reg_config pfc_without_unlock[] = { |
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{ 0x0104, 0xffffbfff }, |
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{ 0x0108, 0xb1ffffe1 }, |
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{ 0x010c, 0xffffffff }, |
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{ 0x0110, 0xffffffff }, |
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{ 0x0114, 0xe047beab }, |
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{ 0x0118, 0x00000203 }, |
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}; |
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static const u32 pfc_base = 0xe6060000; |
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unsigned int i; |
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for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { |
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writel(~pfc_with_unlock[i].val, pfc_base); |
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writel(pfc_with_unlock[i].val, |
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pfc_base | pfc_with_unlock[i].off); |
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} |
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for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) |
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writel(pfc_without_unlock[i].val, |
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pfc_base | pfc_without_unlock[i].off); |
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} |
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static void spl_init_gpio(void) |
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{ |
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static const u16 gpio_offs[] = { |
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0x1000, 0x3000, 0x4000, 0x5000 |
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}; |
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static const struct reg_config gpio_set[] = { |
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{ 0x4000, 0x00c00000 }, |
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{ 0x5000, 0x63020000 }, |
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}; |
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static const struct reg_config gpio_clr[] = { |
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{ 0x1000, 0x00000000 }, |
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{ 0x3000, 0x00000000 }, |
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{ 0x4000, 0x00c00000 }, |
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{ 0x5000, 0xe3020000 }, |
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}; |
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static const u32 gpio_base = 0xe6050000; |
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unsigned int i; |
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for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) |
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writel(0, gpio_base | 0x20 | gpio_offs[i]); |
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for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) |
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writel(0, gpio_base | 0x00 | gpio_offs[i]); |
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for (i = 0; i < ARRAY_SIZE(gpio_set); i++) |
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writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); |
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for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) |
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writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); |
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} |
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static void spl_init_lbsc(void) |
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{ |
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static const struct reg_config lbsc_config[] = { |
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{ 0x00, 0x00000020 }, |
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{ 0x08, 0x00002020 }, |
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{ 0x30, 0x02150326 }, |
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{ 0x38, 0x077f077f }, |
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}; |
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static const u16 lbsc_offs[] = { |
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0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 |
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}; |
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static const u32 lbsc_base = 0xfec00200; |
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unsigned int i; |
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for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { |
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writel(lbsc_config[i].val, |
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lbsc_base | lbsc_config[i].off); |
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writel(lbsc_config[i].val, |
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lbsc_base | (lbsc_config[i].off + 4)); |
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} |
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for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) |
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writel(0, lbsc_base | lbsc_offs[i]); |
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} |
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static void spl_init_dbsc(void) |
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{ |
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static const struct reg_config dbsc_config1[] = { |
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{ 0x0280, 0x0000a55a }, |
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{ 0x0018, 0x21000000 }, |
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{ 0x0018, 0x11000000 }, |
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{ 0x0018, 0x10000000 }, |
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{ 0x0290, 0x00000001 }, |
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{ 0x02a0, 0x80000000 }, |
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{ 0x0290, 0x00000004 }, |
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}; |
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static const struct reg_config dbsc_config2[] = { |
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{ 0x0290, 0x00000006 }, |
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{ 0x02a0, 0x0001c000 }, |
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}; |
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static const struct reg_config dbsc_config3r0d0[] = { |
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{ 0x0290, 0x0000000f }, |
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{ 0x02a0, 0x00181885 }, |
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{ 0x0290, 0x00000070 }, |
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{ 0x02a0, 0x7c000887 }, |
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{ 0x0290, 0x00000080 }, |
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{ 0x02a0, 0x7c000887 }, |
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{ 0x0290, 0x00000090 }, |
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{ 0x02a0, 0x7c000887 }, |
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{ 0x0290, 0x000000a0 }, |
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{ 0x02a0, 0x7c000887 }, |
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{ 0x0290, 0x000000b0 }, |
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{ 0x02a0, 0x7c000880 }, |
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{ 0x0290, 0x000000c0 }, |
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{ 0x02a0, 0x7c000880 }, |
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{ 0x0290, 0x000000d0 }, |
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{ 0x02a0, 0x7c000880 }, |
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{ 0x0290, 0x000000e0 }, |
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{ 0x02a0, 0x7c000880 }, |
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}; |
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static const struct reg_config dbsc_config3r0d1[] = { |
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{ 0x0290, 0x0000000f }, |
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{ 0x02a0, 0x00181885 }, |
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{ 0x0290, 0x00000070 }, |
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{ 0x02a0, 0x7c000887 }, |
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{ 0x0290, 0x00000080 }, |
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{ 0x02a0, 0x7c000887 }, |
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{ 0x0290, 0x00000090 }, |
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{ 0x02a0, 0x7c000887 }, |
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{ 0x0290, 0x000000a0 }, |
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{ 0x02a0, 0x7c000887 }, |
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}; |
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static const struct reg_config dbsc_config3r2[] = { |
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{ 0x0290, 0x0000000f }, |
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{ 0x02a0, 0x00181224 }, |
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}; |
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static const struct reg_config dbsc_config4[] = { |
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{ 0x0290, 0x00000010 }, |
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{ 0x02a0, 0xf004649b }, |
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{ 0x0290, 0x00000061 }, |
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{ 0x02a0, 0x0000006d }, |
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{ 0x0290, 0x00000001 }, |
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{ 0x02a0, 0x00000073 }, |
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{ 0x0020, 0x00000007 }, |
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{ 0x0024, 0x0f030a02 }, |
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{ 0x0030, 0x00000001 }, |
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{ 0x00b0, 0x00000000 }, |
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{ 0x0040, 0x0000000b }, |
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{ 0x0044, 0x00000008 }, |
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{ 0x0048, 0x00000000 }, |
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{ 0x0050, 0x0000000b }, |
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{ 0x0054, 0x000c000b }, |
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{ 0x0058, 0x00000027 }, |
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{ 0x005c, 0x0000001c }, |
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{ 0x0060, 0x00000006 }, |
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{ 0x0064, 0x00000020 }, |
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{ 0x0068, 0x00000008 }, |
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{ 0x006c, 0x0000000c }, |
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{ 0x0070, 0x00000009 }, |
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{ 0x0074, 0x00000012 }, |
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{ 0x0078, 0x000000d0 }, |
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{ 0x007c, 0x00140005 }, |
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{ 0x0080, 0x00050004 }, |
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{ 0x0084, 0x70233005 }, |
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{ 0x0088, 0x000c0000 }, |
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{ 0x008c, 0x00000200 }, |
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{ 0x0090, 0x00000040 }, |
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{ 0x0100, 0x00000001 }, |
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{ 0x00c0, 0x00020001 }, |
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{ 0x00c8, 0x20042004 }, |
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{ 0x0380, 0x00020002 }, |
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{ 0x0390, 0x0000001f }, |
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}; |
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static const struct reg_config dbsc_config5[] = { |
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{ 0x0244, 0x00000011 }, |
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{ 0x0290, 0x00000003 }, |
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{ 0x02a0, 0x0300c4e1 }, |
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{ 0x0290, 0x00000023 }, |
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{ 0x02a0, 0x00fcdb60 }, |
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{ 0x0290, 0x00000011 }, |
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{ 0x02a0, 0x1000040b }, |
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{ 0x0290, 0x00000012 }, |
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{ 0x02a0, 0x9d9cbb66 }, |
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{ 0x0290, 0x00000013 }, |
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{ 0x02a0, 0x1a868400 }, |
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{ 0x0290, 0x00000014 }, |
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{ 0x02a0, 0x300214d8 }, |
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{ 0x0290, 0x00000015 }, |
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{ 0x02a0, 0x00000d70 }, |
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{ 0x0290, 0x00000016 }, |
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{ 0x02a0, 0x00000006 }, |
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{ 0x0290, 0x00000017 }, |
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{ 0x02a0, 0x00000018 }, |
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{ 0x0290, 0x0000001a }, |
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{ 0x02a0, 0x910035c7 }, |
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{ 0x0290, 0x00000004 }, |
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}; |
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static const struct reg_config dbsc_config6[] = { |
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{ 0x0290, 0x00000001 }, |
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{ 0x02a0, 0x00000181 }, |
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{ 0x0018, 0x11000000 }, |
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{ 0x0290, 0x00000004 }, |
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}; |
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static const struct reg_config dbsc_config7[] = { |
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{ 0x0290, 0x00000001 }, |
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{ 0x02a0, 0x0000fe01 }, |
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{ 0x0304, 0x00000000 }, |
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{ 0x00f4, 0x01004c20 }, |
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{ 0x00f8, 0x014000aa }, |
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{ 0x00e0, 0x00000140 }, |
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{ 0x00e4, 0x00081860 }, |
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{ 0x00e8, 0x00010000 }, |
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{ 0x0290, 0x00000004 }, |
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}; |
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static const struct reg_config dbsc_config8[] = { |
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{ 0x0014, 0x00000001 }, |
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{ 0x0010, 0x00000001 }, |
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{ 0x0280, 0x00000000 }, |
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}; |
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static const u32 dbsc3_0_base = DBSC3_0_BASE; |
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static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; |
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static const u32 prr_base = 0xff000044; |
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const u16 prr_rev = readl(prr_base) & 0x7fff; |
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unsigned int i; |
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for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) { |
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writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); |
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writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off); |
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} |
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dbsc_wait(0x2a0); |
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for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) { |
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writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off); |
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writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off); |
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} |
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if (prr_rev == 0x4500) { |
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for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) { |
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writel(dbsc_config3r0d0[i].val, |
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dbsc3_0_base | dbsc_config3r0d0[i].off); |
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} |
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for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) { |
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writel(dbsc_config3r0d1[i].val, |
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dbsc3_1_base | dbsc_config3r0d1[i].off); |
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} |
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} else if (prr_rev != 0x4510) { |
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for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) { |
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writel(dbsc_config3r2[i].val, |
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dbsc3_0_base | dbsc_config3r2[i].off); |
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writel(dbsc_config3r2[i].val, |
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dbsc3_1_base | dbsc_config3r2[i].off); |
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} |
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} |
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for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) { |
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writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); |
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writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off); |
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} |
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dbsc_wait(0x240); |
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for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) { |
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writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); |
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writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off); |
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} |
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dbsc_wait(0x2a0); |
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for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) { |
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writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); |
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writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off); |
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} |
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dbsc_wait(0x2a0); |
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for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) { |
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writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); |
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writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off); |
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} |
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dbsc_wait(0x2a0); |
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for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) { |
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writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); |
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writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off); |
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} |
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} |
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static void spl_init_qspi(void) |
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{ |
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mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); |
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static const u32 qspi_base = 0xe6b10000; |
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writeb(0x08, qspi_base + 0x00); |
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writeb(0x00, qspi_base + 0x01); |
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writeb(0x06, qspi_base + 0x02); |
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writeb(0x01, qspi_base + 0x0a); |
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writeb(0x00, qspi_base + 0x0b); |
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writeb(0x00, qspi_base + 0x0c); |
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writeb(0x00, qspi_base + 0x0d); |
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writeb(0x00, qspi_base + 0x0e); |
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writew(0xe080, qspi_base + 0x10); |
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writeb(0xc0, qspi_base + 0x18); |
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writeb(0x00, qspi_base + 0x18); |
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writeb(0x00, qspi_base + 0x08); |
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writeb(0x48, qspi_base + 0x00); |
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} |
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void board_init_f(ulong dummy) |
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{ |
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); |
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mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204); |
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/*
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* SD0 clock is set to 97.5MHz by default. |
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* Set SD2 to the 97.5MHz as well. |
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*/ |
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writel(SD_97500KHZ, SD2CKCR); |
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spl_init_sys(); |
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spl_init_pfc(); |
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spl_init_gpio(); |
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spl_init_lbsc(); |
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spl_init_dbsc(); |
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spl_init_qspi(); |
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} |
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void spl_board_init(void) |
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{ |
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/* UART clocks enabled and gd valid - init serial console */ |
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preloader_console_init(); |
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} |
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void board_boot_order(u32 *spl_boot_list) |
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{ |
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const u32 jtag_magic = 0x1337c0de; |
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const u32 load_magic = 0xb33fc0de; |
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/*
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* If JTAG probe sets special word at 0xe6300020, then it must |
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* put U-Boot into RAM and SPL will start it from RAM. |
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*/ |
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if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { |
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printf("JTAG boot detected!\n"); |
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while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) |
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; |
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spl_boot_list[0] = BOOT_DEVICE_RAM; |
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spl_boot_list[1] = BOOT_DEVICE_NONE; |
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return; |
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} |
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|
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/* Boot from SPI NOR with YMODEM UART fallback. */ |
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spl_boot_list[0] = BOOT_DEVICE_SPI; |
||||
spl_boot_list[1] = BOOT_DEVICE_UART; |
||||
spl_boot_list[2] = BOOT_DEVICE_NONE; |
||||
} |
||||
|
||||
void reset_cpu(ulong addr) |
||||
{ |
||||
} |
||||
@ -1,151 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __MATSUSHITA_COMMON_H__ |
||||
#define __MATSUSHITA_COMMON_H__ |
||||
|
||||
#define MATSU_SD_CMD 0x000 /* command */ |
||||
#define MATSU_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */ |
||||
#define MATSU_SD_CMD_MULTI BIT(13) /* multiple block transfer */ |
||||
#define MATSU_SD_CMD_RD BIT(12) /* 1: read, 0: write */ |
||||
#define MATSU_SD_CMD_DATA BIT(11) /* data transfer */ |
||||
#define MATSU_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */ |
||||
#define MATSU_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */ |
||||
#define MATSU_SD_CMD_RSP_NONE (3 << 8)/* response: none */ |
||||
#define MATSU_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */ |
||||
#define MATSU_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */ |
||||
#define MATSU_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */ |
||||
#define MATSU_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */ |
||||
#define MATSU_SD_ARG 0x008 /* command argument */ |
||||
#define MATSU_SD_STOP 0x010 /* stop action control */ |
||||
#define MATSU_SD_STOP_SEC BIT(8) /* use sector count */ |
||||
#define MATSU_SD_STOP_STP BIT(0) /* issue CMD12 */ |
||||
#define MATSU_SD_SECCNT 0x014 /* sector counter */ |
||||
#define MATSU_SD_RSP10 0x018 /* response[39:8] */ |
||||
#define MATSU_SD_RSP32 0x020 /* response[71:40] */ |
||||
#define MATSU_SD_RSP54 0x028 /* response[103:72] */ |
||||
#define MATSU_SD_RSP76 0x030 /* response[127:104] */ |
||||
#define MATSU_SD_INFO1 0x038 /* IRQ status 1 */ |
||||
#define MATSU_SD_INFO1_CD BIT(5) /* state of card detect */ |
||||
#define MATSU_SD_INFO1_INSERT BIT(4) /* card inserted */ |
||||
#define MATSU_SD_INFO1_REMOVE BIT(3) /* card removed */ |
||||
#define MATSU_SD_INFO1_CMP BIT(2) /* data complete */ |
||||
#define MATSU_SD_INFO1_RSP BIT(0) /* response complete */ |
||||
#define MATSU_SD_INFO2 0x03c /* IRQ status 2 */ |
||||
#define MATSU_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */ |
||||
#define MATSU_SD_INFO2_CBSY BIT(14) /* command busy */ |
||||
#define MATSU_SD_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */ |
||||
#define MATSU_SD_INFO2_BWE BIT(9) /* write buffer ready */ |
||||
#define MATSU_SD_INFO2_BRE BIT(8) /* read buffer ready */ |
||||
#define MATSU_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */ |
||||
#define MATSU_SD_INFO2_ERR_RTO BIT(6) /* response time out */ |
||||
#define MATSU_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */ |
||||
#define MATSU_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */ |
||||
#define MATSU_SD_INFO2_ERR_TO BIT(3) /* time out error */ |
||||
#define MATSU_SD_INFO2_ERR_END BIT(2) /* END bit error */ |
||||
#define MATSU_SD_INFO2_ERR_CRC BIT(1) /* CRC error */ |
||||
#define MATSU_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */ |
||||
#define MATSU_SD_INFO1_MASK 0x040 |
||||
#define MATSU_SD_INFO2_MASK 0x044 |
||||
#define MATSU_SD_CLKCTL 0x048 /* clock divisor */ |
||||
#define MATSU_SD_CLKCTL_DIV_MASK 0x104ff |
||||
#define MATSU_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */ |
||||
#define MATSU_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */ |
||||
#define MATSU_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */ |
||||
#define MATSU_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */ |
||||
#define MATSU_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */ |
||||
#define MATSU_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */ |
||||
#define MATSU_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */ |
||||
#define MATSU_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */ |
||||
#define MATSU_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ |
||||
#define MATSU_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ |
||||
#define MATSU_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ |
||||
#define MATSU_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */ |
||||
#define MATSU_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ |
||||
#define MATSU_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ |
||||
#define MATSU_SD_SIZE 0x04c /* block size */ |
||||
#define MATSU_SD_OPTION 0x050 |
||||
#define MATSU_SD_OPTION_WIDTH_MASK (5 << 13) |
||||
#define MATSU_SD_OPTION_WIDTH_1 (4 << 13) |
||||
#define MATSU_SD_OPTION_WIDTH_4 (0 << 13) |
||||
#define MATSU_SD_OPTION_WIDTH_8 (1 << 13) |
||||
#define MATSU_SD_BUF 0x060 /* read/write buffer */ |
||||
#define MATSU_SD_EXTMODE 0x1b0 |
||||
#define MATSU_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */ |
||||
#define MATSU_SD_SOFT_RST 0x1c0 |
||||
#define MATSU_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */ |
||||
#define MATSU_SD_VERSION 0x1c4 /* version register */ |
||||
#define MATSU_SD_VERSION_IP 0xff /* IP version */ |
||||
#define MATSU_SD_HOST_MODE 0x1c8 |
||||
#define MATSU_SD_IF_MODE 0x1cc |
||||
#define MATSU_SD_IF_MODE_DDR BIT(0) /* DDR mode */ |
||||
#define MATSU_SD_VOLT 0x1e4 /* voltage switch */ |
||||
#define MATSU_SD_VOLT_MASK (3 << 0) |
||||
#define MATSU_SD_VOLT_OFF (0 << 0) |
||||
#define MATSU_SD_VOLT_330 (1 << 0)/* 3.3V signal */ |
||||
#define MATSU_SD_VOLT_180 (2 << 0)/* 1.8V signal */ |
||||
#define MATSU_SD_DMA_MODE 0x410 |
||||
#define MATSU_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ |
||||
#define MATSU_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ |
||||
#define MATSU_SD_DMA_CTL 0x414 |
||||
#define MATSU_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ |
||||
#define MATSU_SD_DMA_RST 0x418 |
||||
#define MATSU_SD_DMA_RST_RD BIT(9) |
||||
#define MATSU_SD_DMA_RST_WR BIT(8) |
||||
#define MATSU_SD_DMA_INFO1 0x420 |
||||
#define MATSU_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */ |
||||
#define MATSU_SD_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */ |
||||
#define MATSU_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */ |
||||
#define MATSU_SD_DMA_INFO1_MASK 0x424 |
||||
#define MATSU_SD_DMA_INFO2 0x428 |
||||
#define MATSU_SD_DMA_INFO2_ERR_RD BIT(17) |
||||
#define MATSU_SD_DMA_INFO2_ERR_WR BIT(16) |
||||
#define MATSU_SD_DMA_INFO2_MASK 0x42c |
||||
#define MATSU_SD_DMA_ADDR_L 0x440 |
||||
#define MATSU_SD_DMA_ADDR_H 0x444 |
||||
|
||||
/* alignment required by the DMA engine of this controller */ |
||||
#define MATSU_SD_DMA_MINALIGN 0x10 |
||||
|
||||
struct matsu_sd_plat { |
||||
struct mmc_config cfg; |
||||
struct mmc mmc; |
||||
}; |
||||
|
||||
struct matsu_sd_priv { |
||||
void __iomem *regbase; |
||||
unsigned long mclk; |
||||
unsigned int version; |
||||
u32 caps; |
||||
#define MATSU_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ |
||||
#define MATSU_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ |
||||
#define MATSU_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ |
||||
#define MATSU_SD_CAP_64BIT BIT(3) /* Controller is 64bit */ |
||||
#define MATSU_SD_CAP_16BIT BIT(4) /* Controller is 16bit */ |
||||
#define MATSU_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */ |
||||
#define MATSU_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */ |
||||
#define MATSU_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */ |
||||
#define MATSU_SD_CAP_RCAR \ |
||||
(MATSU_SD_CAP_RCAR_GEN2 | MATSU_SD_CAP_RCAR_GEN3) |
||||
#ifdef CONFIG_DM_REGULATOR |
||||
struct udevice *vqmmc_dev; |
||||
#endif |
||||
}; |
||||
|
||||
int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
||||
struct mmc_data *data); |
||||
int matsu_sd_set_ios(struct udevice *dev); |
||||
int matsu_sd_get_cd(struct udevice *dev); |
||||
|
||||
int matsu_sd_bind(struct udevice *dev); |
||||
int matsu_sd_probe(struct udevice *dev, u32 quirks); |
||||
|
||||
u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg); |
||||
void matsu_sd_writel(struct matsu_sd_priv *priv, |
||||
u32 val, unsigned int reg); |
||||
|
||||
#endif /* __MATSUSHITA_COMMON_H__ */ |
||||
@ -0,0 +1,151 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __TMIO_COMMON_H__ |
||||
#define __TMIO_COMMON_H__ |
||||
|
||||
#define TMIO_SD_CMD 0x000 /* command */ |
||||
#define TMIO_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */ |
||||
#define TMIO_SD_CMD_MULTI BIT(13) /* multiple block transfer */ |
||||
#define TMIO_SD_CMD_RD BIT(12) /* 1: read, 0: write */ |
||||
#define TMIO_SD_CMD_DATA BIT(11) /* data transfer */ |
||||
#define TMIO_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */ |
||||
#define TMIO_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */ |
||||
#define TMIO_SD_CMD_RSP_NONE (3 << 8)/* response: none */ |
||||
#define TMIO_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */ |
||||
#define TMIO_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */ |
||||
#define TMIO_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */ |
||||
#define TMIO_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */ |
||||
#define TMIO_SD_ARG 0x008 /* command argument */ |
||||
#define TMIO_SD_STOP 0x010 /* stop action control */ |
||||
#define TMIO_SD_STOP_SEC BIT(8) /* use sector count */ |
||||
#define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */ |
||||
#define TMIO_SD_SECCNT 0x014 /* sector counter */ |
||||
#define TMIO_SD_RSP10 0x018 /* response[39:8] */ |
||||
#define TMIO_SD_RSP32 0x020 /* response[71:40] */ |
||||
#define TMIO_SD_RSP54 0x028 /* response[103:72] */ |
||||
#define TMIO_SD_RSP76 0x030 /* response[127:104] */ |
||||
#define TMIO_SD_INFO1 0x038 /* IRQ status 1 */ |
||||
#define TMIO_SD_INFO1_CD BIT(5) /* state of card detect */ |
||||
#define TMIO_SD_INFO1_INSERT BIT(4) /* card inserted */ |
||||
#define TMIO_SD_INFO1_REMOVE BIT(3) /* card removed */ |
||||
#define TMIO_SD_INFO1_CMP BIT(2) /* data complete */ |
||||
#define TMIO_SD_INFO1_RSP BIT(0) /* response complete */ |
||||
#define TMIO_SD_INFO2 0x03c /* IRQ status 2 */ |
||||
#define TMIO_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */ |
||||
#define TMIO_SD_INFO2_CBSY BIT(14) /* command busy */ |
||||
#define TMIO_SD_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */ |
||||
#define TMIO_SD_INFO2_BWE BIT(9) /* write buffer ready */ |
||||
#define TMIO_SD_INFO2_BRE BIT(8) /* read buffer ready */ |
||||
#define TMIO_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */ |
||||
#define TMIO_SD_INFO2_ERR_RTO BIT(6) /* response time out */ |
||||
#define TMIO_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */ |
||||
#define TMIO_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */ |
||||
#define TMIO_SD_INFO2_ERR_TO BIT(3) /* time out error */ |
||||
#define TMIO_SD_INFO2_ERR_END BIT(2) /* END bit error */ |
||||
#define TMIO_SD_INFO2_ERR_CRC BIT(1) /* CRC error */ |
||||
#define TMIO_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */ |
||||
#define TMIO_SD_INFO1_MASK 0x040 |
||||
#define TMIO_SD_INFO2_MASK 0x044 |
||||
#define TMIO_SD_CLKCTL 0x048 /* clock divisor */ |
||||
#define TMIO_SD_CLKCTL_DIV_MASK 0x104ff |
||||
#define TMIO_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */ |
||||
#define TMIO_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */ |
||||
#define TMIO_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */ |
||||
#define TMIO_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */ |
||||
#define TMIO_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */ |
||||
#define TMIO_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */ |
||||
#define TMIO_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */ |
||||
#define TMIO_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */ |
||||
#define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ |
||||
#define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ |
||||
#define TMIO_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ |
||||
#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */ |
||||
#define TMIO_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ |
||||
#define TMIO_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ |
||||
#define TMIO_SD_SIZE 0x04c /* block size */ |
||||
#define TMIO_SD_OPTION 0x050 |
||||
#define TMIO_SD_OPTION_WIDTH_MASK (5 << 13) |
||||
#define TMIO_SD_OPTION_WIDTH_1 (4 << 13) |
||||
#define TMIO_SD_OPTION_WIDTH_4 (0 << 13) |
||||
#define TMIO_SD_OPTION_WIDTH_8 (1 << 13) |
||||
#define TMIO_SD_BUF 0x060 /* read/write buffer */ |
||||
#define TMIO_SD_EXTMODE 0x1b0 |
||||
#define TMIO_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */ |
||||
#define TMIO_SD_SOFT_RST 0x1c0 |
||||
#define TMIO_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */ |
||||
#define TMIO_SD_VERSION 0x1c4 /* version register */ |
||||
#define TMIO_SD_VERSION_IP 0xff /* IP version */ |
||||
#define TMIO_SD_HOST_MODE 0x1c8 |
||||
#define TMIO_SD_IF_MODE 0x1cc |
||||
#define TMIO_SD_IF_MODE_DDR BIT(0) /* DDR mode */ |
||||
#define TMIO_SD_VOLT 0x1e4 /* voltage switch */ |
||||
#define TMIO_SD_VOLT_MASK (3 << 0) |
||||
#define TMIO_SD_VOLT_OFF (0 << 0) |
||||
#define TMIO_SD_VOLT_330 (1 << 0)/* 3.3V signal */ |
||||
#define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */ |
||||
#define TMIO_SD_DMA_MODE 0x410 |
||||
#define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ |
||||
#define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ |
||||
#define TMIO_SD_DMA_CTL 0x414 |
||||
#define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ |
||||
#define TMIO_SD_DMA_RST 0x418 |
||||
#define TMIO_SD_DMA_RST_RD BIT(9) |
||||
#define TMIO_SD_DMA_RST_WR BIT(8) |
||||
#define TMIO_SD_DMA_INFO1 0x420 |
||||
#define TMIO_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */ |
||||
#define TMIO_SD_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */ |
||||
#define TMIO_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */ |
||||
#define TMIO_SD_DMA_INFO1_MASK 0x424 |
||||
#define TMIO_SD_DMA_INFO2 0x428 |
||||
#define TMIO_SD_DMA_INFO2_ERR_RD BIT(17) |
||||
#define TMIO_SD_DMA_INFO2_ERR_WR BIT(16) |
||||
#define TMIO_SD_DMA_INFO2_MASK 0x42c |
||||
#define TMIO_SD_DMA_ADDR_L 0x440 |
||||
#define TMIO_SD_DMA_ADDR_H 0x444 |
||||
|
||||
/* alignment required by the DMA engine of this controller */ |
||||
#define TMIO_SD_DMA_MINALIGN 0x10 |
||||
|
||||
struct tmio_sd_plat { |
||||
struct mmc_config cfg; |
||||
struct mmc mmc; |
||||
}; |
||||
|
||||
struct tmio_sd_priv { |
||||
void __iomem *regbase; |
||||
unsigned long mclk; |
||||
unsigned int version; |
||||
u32 caps; |
||||
#define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ |
||||
#define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ |
||||
#define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ |
||||
#define TMIO_SD_CAP_64BIT BIT(3) /* Controller is 64bit */ |
||||
#define TMIO_SD_CAP_16BIT BIT(4) /* Controller is 16bit */ |
||||
#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */ |
||||
#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */ |
||||
#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */ |
||||
#define TMIO_SD_CAP_RCAR \ |
||||
(TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3) |
||||
#ifdef CONFIG_DM_REGULATOR |
||||
struct udevice *vqmmc_dev; |
||||
#endif |
||||
}; |
||||
|
||||
int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
||||
struct mmc_data *data); |
||||
int tmio_sd_set_ios(struct udevice *dev); |
||||
int tmio_sd_get_cd(struct udevice *dev); |
||||
|
||||
int tmio_sd_bind(struct udevice *dev); |
||||
int tmio_sd_probe(struct udevice *dev, u32 quirks); |
||||
|
||||
u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg); |
||||
void tmio_sd_writel(struct tmio_sd_priv *priv, |
||||
u32 val, unsigned int reg); |
||||
|
||||
#endif /* __TMIO_COMMON_H__ */ |
||||
Loading…
Reference in new issue