Replace AT91CAP9.h file with several splitted header files coming from the Linux kernel. This is part 1 of the replacement: pristine header files import. Signed-off-by: Stelian Pop <stelian@popies.net>master
Stelian Pop
17 years ago
committed by
Jean-Christophe PLAGNIOL-VILLARD
parent
a8a78f2d99
commit
6d1dbbbf9f
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/*
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* include/asm-arm/arch-at91/at91_pio.h |
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* |
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* Copyright (C) 2005 Ivan Kokshaysky |
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* Copyright (C) SAN People |
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* |
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* Parallel I/O Controller (PIO) - System peripherals registers. |
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* Based on AT91RM9200 datasheet revision E. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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*/ |
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#ifndef AT91_PIO_H |
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#define AT91_PIO_H |
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#define PIO_PER 0x00 /* Enable Register */ |
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#define PIO_PDR 0x04 /* Disable Register */ |
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#define PIO_PSR 0x08 /* Status Register */ |
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#define PIO_OER 0x10 /* Output Enable Register */ |
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#define PIO_ODR 0x14 /* Output Disable Register */ |
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#define PIO_OSR 0x18 /* Output Status Register */ |
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#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ |
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#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ |
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#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ |
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#define PIO_SODR 0x30 /* Set Output Data Register */ |
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#define PIO_CODR 0x34 /* Clear Output Data Register */ |
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#define PIO_ODSR 0x38 /* Output Data Status Register */ |
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#define PIO_PDSR 0x3c /* Pin Data Status Register */ |
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#define PIO_IER 0x40 /* Interrupt Enable Register */ |
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#define PIO_IDR 0x44 /* Interrupt Disable Register */ |
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#define PIO_IMR 0x48 /* Interrupt Mask Register */ |
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#define PIO_ISR 0x4c /* Interrupt Status Register */ |
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#define PIO_MDER 0x50 /* Multi-driver Enable Register */ |
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#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ |
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#define PIO_MDSR 0x58 /* Multi-driver Status Register */ |
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#define PIO_PUDR 0x60 /* Pull-up Disable Register */ |
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#define PIO_PUER 0x64 /* Pull-up Enable Register */ |
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#define PIO_PUSR 0x68 /* Pull-up Status Register */ |
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#define PIO_ASR 0x70 /* Peripheral A Select Register */ |
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#define PIO_BSR 0x74 /* Peripheral B Select Register */ |
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#define PIO_ABSR 0x78 /* AB Status Register */ |
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#define PIO_OWER 0xa0 /* Output Write Enable Register */ |
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#define PIO_OWDR 0xa4 /* Output Write Disable Register */ |
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#define PIO_OWSR 0xa8 /* Output Write Status Register */ |
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#endif |
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@ -0,0 +1,29 @@ |
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/*
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* include/asm-arm/arch-at91/at91_pit.h |
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* |
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* Periodic Interval Timer (PIT) - System peripherals regsters. |
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* Based on AT91SAM9261 datasheet revision D. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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*/ |
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#ifndef AT91_PIT_H |
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#define AT91_PIT_H |
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#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ |
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#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ |
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#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ |
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#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ |
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#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ |
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#define AT91_PIT_PITS (1 << 0) /* Timer Status */ |
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#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ |
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#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ |
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#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ |
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#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ |
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#endif |
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@ -0,0 +1,99 @@ |
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/*
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* include/asm-arm/arch-at91/at91_pmc.h |
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* |
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* Copyright (C) 2005 Ivan Kokshaysky |
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* Copyright (C) SAN People |
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* |
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* Power Management Controller (PMC) - System peripherals registers. |
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* Based on AT91RM9200 datasheet revision E. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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*/ |
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#ifndef AT91_PMC_H |
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#define AT91_PMC_H |
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#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ |
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#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ |
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#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ |
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#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ |
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#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ |
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ |
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#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ |
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#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ |
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#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ |
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#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ |
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#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ |
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#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ |
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#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ |
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#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ |
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#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ |
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#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ |
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#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ |
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#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ |
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#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ |
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#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ |
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#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ |
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ |
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#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ |
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#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ |
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#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ |
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#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ |
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#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ |
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#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ |
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#define AT91_PMC_DIV (0xff << 0) /* Divider */ |
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#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ |
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#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ |
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#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ |
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#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ |
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#define AT91_PMC_USBDIV_1 (0 << 28) |
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#define AT91_PMC_USBDIV_2 (1 << 28) |
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#define AT91_PMC_USBDIV_4 (2 << 28) |
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#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ |
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#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ |
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#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ |
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#define AT91_PMC_CSS_SLOW (0 << 0) |
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#define AT91_PMC_CSS_MAIN (1 << 0) |
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#define AT91_PMC_CSS_PLLA (2 << 0) |
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#define AT91_PMC_CSS_PLLB (3 << 0) |
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#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ |
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#define AT91_PMC_PRES_1 (0 << 2) |
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#define AT91_PMC_PRES_2 (1 << 2) |
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#define AT91_PMC_PRES_4 (2 << 2) |
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#define AT91_PMC_PRES_8 (3 << 2) |
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#define AT91_PMC_PRES_16 (4 << 2) |
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#define AT91_PMC_PRES_32 (5 << 2) |
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#define AT91_PMC_PRES_64 (6 << 2) |
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#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ |
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#define AT91_PMC_MDIV_1 (0 << 8) |
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#define AT91_PMC_MDIV_2 (1 << 8) |
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#define AT91_PMC_MDIV_3 (2 << 8) |
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#define AT91_PMC_MDIV_4 (3 << 8) |
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#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ |
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#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ |
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#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ |
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#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ |
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#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ |
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#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ |
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#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ |
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#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ |
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#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ |
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#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ |
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#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ |
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#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ |
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#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ |
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#endif |
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@ -0,0 +1,38 @@ |
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/*
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* include/asm-arm/arch-at91/at91_rstc.h |
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* |
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* Reset Controller (RSTC) - System peripherals regsters. |
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* Based on AT91SAM9261 datasheet revision D. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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*/ |
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#ifndef AT91_RSTC_H |
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#define AT91_RSTC_H |
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#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ |
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#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ |
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#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ |
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#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ |
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#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ |
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#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ |
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#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ |
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#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ |
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#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) |
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#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) |
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#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) |
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#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) |
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#define AT91_RSTC_RSTTYP_USER (4 << 8) |
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#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ |
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#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ |
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#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ |
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#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ |
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#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ |
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#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ |
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#endif |
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@ -0,0 +1,81 @@ |
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/*
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* include/asm-arm/arch-at91/at91_spi.h |
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* |
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* Copyright (C) 2005 Ivan Kokshaysky |
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* Copyright (C) SAN People |
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* |
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* Serial Peripheral Interface (SPI) registers. |
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* Based on AT91RM9200 datasheet revision E. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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*/ |
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#ifndef AT91_SPI_H |
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#define AT91_SPI_H |
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#define AT91_SPI_CR 0x00 /* Control Register */ |
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#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ |
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#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ |
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#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ |
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#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ |
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#define AT91_SPI_MR 0x04 /* Mode Register */ |
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#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ |
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#define AT91_SPI_PS (1 << 1) /* Peripheral Select */ |
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#define AT91_SPI_PS_FIXED (0 << 1) |
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#define AT91_SPI_PS_VARIABLE (1 << 1) |
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#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ |
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#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ |
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#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ |
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#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ |
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ |
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#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ |
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#define AT91_SPI_RDR 0x08 /* Receive Data Register */ |
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#define AT91_SPI_RD (0xffff << 0) /* Receive Data */ |
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ |
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#define AT91_SPI_TDR 0x0c /* Transmit Data Register */ |
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#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ |
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ |
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#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ |
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#define AT91_SPI_SR 0x10 /* Status Register */ |
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#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ |
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#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ |
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#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ |
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#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ |
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#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ |
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#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ |
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#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ |
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#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ |
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#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ |
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#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ |
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#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ |
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#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ |
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#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ |
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#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ |
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#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ |
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#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ |
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#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ |
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#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ |
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#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ |
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#define AT91_SPI_BITS_8 (0 << 4) |
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#define AT91_SPI_BITS_9 (1 << 4) |
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#define AT91_SPI_BITS_10 (2 << 4) |
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#define AT91_SPI_BITS_11 (3 << 4) |
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#define AT91_SPI_BITS_12 (4 << 4) |
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#define AT91_SPI_BITS_13 (5 << 4) |
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#define AT91_SPI_BITS_14 (6 << 4) |
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#define AT91_SPI_BITS_15 (7 << 4) |
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#define AT91_SPI_BITS_16 (8 << 4) |
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#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ |
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#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ |
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#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ |
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#endif |
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@ -0,0 +1,126 @@ |
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/*
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* include/asm-arm/arch-at91/at91cap9.h |
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* |
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* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> |
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* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> |
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* Copyright (C) 2007 Atmel Corporation. |
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* |
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* Common definitions. |
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* Based on AT91CAP9 datasheet revision B (Preliminary). |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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*/ |
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#ifndef AT91CAP9_H |
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#define AT91CAP9_H |
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/*
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* Peripheral identifiers/interrupts. |
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*/ |
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#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
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#define AT91_ID_SYS 1 /* System Peripherals */ |
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#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */ |
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#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */ |
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#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */ |
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#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */ |
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#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */ |
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#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */ |
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#define AT91CAP9_ID_US0 8 /* USART 0 */ |
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#define AT91CAP9_ID_US1 9 /* USART 1 */ |
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#define AT91CAP9_ID_US2 10 /* USART 2 */ |
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#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */ |
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#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */ |
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#define AT91CAP9_ID_CAN 13 /* CAN */ |
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#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */ |
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#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */ |
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#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */ |
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#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */ |
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#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */ |
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#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */ |
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#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */ |
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#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */ |
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#define AT91CAP9_ID_EMAC 22 /* Ethernet */ |
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#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */ |
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#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */ |
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#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */ |
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#define AT91CAP9_ID_LCDC 26 /* LCD Controller */ |
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#define AT91CAP9_ID_DMA 27 /* DMA Controller */ |
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#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */ |
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#define AT91CAP9_ID_UHP 29 /* USB Host Port */ |
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#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ |
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#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ |
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/*
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* User Peripheral physical base addresses. |
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*/ |
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#define AT91CAP9_BASE_UDPHS 0xfff78000 |
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#define AT91CAP9_BASE_TCB0 0xfff7c000 |
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#define AT91CAP9_BASE_TC0 0xfff7c000 |
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#define AT91CAP9_BASE_TC1 0xfff7c040 |
||||
#define AT91CAP9_BASE_TC2 0xfff7c080 |
||||
#define AT91CAP9_BASE_MCI0 0xfff80000 |
||||
#define AT91CAP9_BASE_MCI1 0xfff84000 |
||||
#define AT91CAP9_BASE_TWI 0xfff88000 |
||||
#define AT91CAP9_BASE_US0 0xfff8c000 |
||||
#define AT91CAP9_BASE_US1 0xfff90000 |
||||
#define AT91CAP9_BASE_US2 0xfff94000 |
||||
#define AT91CAP9_BASE_SSC0 0xfff98000 |
||||
#define AT91CAP9_BASE_SSC1 0xfff9c000 |
||||
#define AT91CAP9_BASE_AC97C 0xfffa0000 |
||||
#define AT91CAP9_BASE_SPI0 0xfffa4000 |
||||
#define AT91CAP9_BASE_SPI1 0xfffa8000 |
||||
#define AT91CAP9_BASE_CAN 0xfffac000 |
||||
#define AT91CAP9_BASE_PWMC 0xfffb8000 |
||||
#define AT91CAP9_BASE_EMAC 0xfffbc000 |
||||
#define AT91CAP9_BASE_ADC 0xfffc0000 |
||||
#define AT91CAP9_BASE_ISI 0xfffc4000 |
||||
#define AT91_BASE_SYS 0xffffe200 |
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS) |
||||
*/ |
||||
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) |
||||
#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) |
||||
#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) |
||||
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) |
||||
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) |
||||
#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) |
||||
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) |
||||
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) |
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) |
||||
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) |
||||
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) |
||||
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) |
||||
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) |
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) |
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) |
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) |
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) |
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) |
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
||||
|
||||
#define AT91_USART0 AT91CAP9_BASE_US0 |
||||
#define AT91_USART1 AT91CAP9_BASE_US1 |
||||
#define AT91_USART2 AT91CAP9_BASE_US2 |
||||
|
||||
|
||||
/*
|
||||
* Internal Memory. |
||||
*/ |
||||
#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ |
||||
#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */ |
||||
|
||||
#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */ |
||||
#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ |
||||
|
||||
#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ |
||||
#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */ |
||||
#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ |
||||
|
||||
#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 |
||||
|
||||
#endif |
||||
@ -0,0 +1,132 @@ |
||||
/*
|
||||
* include/asm-arm/arch-at91/at91cap9_matrix.h |
||||
* |
||||
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> |
||||
* Copyright (C) 2006 Atmel Corporation. |
||||
* |
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers. |
||||
* Based on AT91CAP9 datasheet revision B (Preliminary). |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
|
||||
#ifndef AT91CAP9_MATRIX_H |
||||
#define AT91CAP9_MATRIX_H |
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ |
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ |
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ |
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ |
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ |
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ |
||||
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ |
||||
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ |
||||
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ |
||||
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ |
||||
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ |
||||
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ |
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ |
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0) |
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0) |
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0) |
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0) |
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) |
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ |
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ |
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ |
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ |
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ |
||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ |
||||
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ |
||||
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ |
||||
#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */ |
||||
#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */ |
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ |
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) |
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ |
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ |
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) |
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) |
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ |
||||
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ |
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ |
||||
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ |
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ |
||||
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ |
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ |
||||
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ |
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ |
||||
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ |
||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ |
||||
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ |
||||
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ |
||||
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ |
||||
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ |
||||
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ |
||||
#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */ |
||||
#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */ |
||||
#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */ |
||||
#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */ |
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ |
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ |
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ |
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ |
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ |
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ |
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ |
||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ |
||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ |
||||
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ |
||||
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ |
||||
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ |
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ |
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
||||
#define AT91_MATRIX_RCB2 (1 << 2) |
||||
#define AT91_MATRIX_RCB3 (1 << 3) |
||||
#define AT91_MATRIX_RCB4 (1 << 4) |
||||
#define AT91_MATRIX_RCB5 (1 << 5) |
||||
#define AT91_MATRIX_RCB6 (1 << 6) |
||||
#define AT91_MATRIX_RCB7 (1 << 7) |
||||
#define AT91_MATRIX_RCB8 (1 << 8) |
||||
#define AT91_MATRIX_RCB9 (1 << 9) |
||||
#define AT91_MATRIX_RCB10 (1 << 10) |
||||
#define AT91_MATRIX_RCB11 (1 << 11) |
||||
|
||||
#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */ |
||||
#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */ |
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ |
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) |
||||
#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1) |
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ |
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) |
||||
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) |
||||
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ |
||||
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) |
||||
#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4) |
||||
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ |
||||
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) |
||||
#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5) |
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
||||
#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */ |
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ |
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) |
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) |
||||
|
||||
#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */ |
||||
#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */ |
||||
#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */ |
||||
|
||||
#endif |
||||
@ -0,0 +1,141 @@ |
||||
/*
|
||||
* include/asm-arm/arch-at91/at91sam926x_mc.h |
||||
* |
||||
* Memory Controllers (SMC, SDRAMC) - System peripherals registers. |
||||
* Based on AT91SAM9261 datasheet revision D. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
|
||||
#ifndef AT91SAM926x_MC_H |
||||
#define AT91SAM926x_MC_H |
||||
|
||||
/* SDRAM Controller (SDRAMC) registers */ |
||||
#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ |
||||
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ |
||||
#define AT91_SDRAMC_MODE_NORMAL 0 |
||||
#define AT91_SDRAMC_MODE_NOP 1 |
||||
#define AT91_SDRAMC_MODE_PRECHARGE 2 |
||||
#define AT91_SDRAMC_MODE_LMR 3 |
||||
#define AT91_SDRAMC_MODE_REFRESH 4 |
||||
#define AT91_SDRAMC_MODE_EXT_LMR 5 |
||||
#define AT91_SDRAMC_MODE_DEEP 6 |
||||
|
||||
#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ |
||||
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ |
||||
|
||||
#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ |
||||
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ |
||||
#define AT91_SDRAMC_NC_8 (0 << 0) |
||||
#define AT91_SDRAMC_NC_9 (1 << 0) |
||||
#define AT91_SDRAMC_NC_10 (2 << 0) |
||||
#define AT91_SDRAMC_NC_11 (3 << 0) |
||||
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ |
||||
#define AT91_SDRAMC_NR_11 (0 << 2) |
||||
#define AT91_SDRAMC_NR_12 (1 << 2) |
||||
#define AT91_SDRAMC_NR_13 (2 << 2) |
||||
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ |
||||
#define AT91_SDRAMC_NB_2 (0 << 4) |
||||
#define AT91_SDRAMC_NB_4 (1 << 4) |
||||
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ |
||||
#define AT91_SDRAMC_CAS_1 (1 << 5) |
||||
#define AT91_SDRAMC_CAS_2 (2 << 5) |
||||
#define AT91_SDRAMC_CAS_3 (3 << 5) |
||||
#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ |
||||
#define AT91_SDRAMC_DBW_32 (0 << 7) |
||||
#define AT91_SDRAMC_DBW_16 (1 << 7) |
||||
#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ |
||||
#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ |
||||
#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ |
||||
#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ |
||||
#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ |
||||
#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ |
||||
|
||||
#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ |
||||
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ |
||||
#define AT91_SDRAMC_LPCB_DISABLE 0 |
||||
#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 |
||||
#define AT91_SDRAMC_LPCB_POWER_DOWN 2 |
||||
#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 |
||||
#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ |
||||
#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ |
||||
#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */ |
||||
#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ |
||||
#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) |
||||
#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) |
||||
#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) |
||||
|
||||
#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ |
||||
#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ |
||||
#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ |
||||
#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ |
||||
#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ |
||||
|
||||
#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ |
||||
#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ |
||||
#define AT91_SDRAMC_MD_SDRAM 0 |
||||
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 |
||||
|
||||
|
||||
/* Static Memory Controller (SMC) registers */ |
||||
#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ |
||||
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ |
||||
#define AT91_SMC_NWESETUP_(x) ((x) << 0) |
||||
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ |
||||
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) |
||||
#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ |
||||
#define AT91_SMC_NRDSETUP_(x) ((x) << 16) |
||||
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ |
||||
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) |
||||
|
||||
#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ |
||||
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ |
||||
#define AT91_SMC_NWEPULSE_(x) ((x) << 0) |
||||
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ |
||||
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) |
||||
#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ |
||||
#define AT91_SMC_NRDPULSE_(x) ((x) << 16) |
||||
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ |
||||
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) |
||||
|
||||
#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ |
||||
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ |
||||
#define AT91_SMC_NWECYCLE_(x) ((x) << 0) |
||||
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ |
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#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) |
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|
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#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ |
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#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ |
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#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ |
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#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ |
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#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) |
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#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) |
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#define AT91_SMC_EXNWMODE_READY (3 << 4) |
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#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ |
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#define AT91_SMC_BAT_SELECT (0 << 8) |
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#define AT91_SMC_BAT_WRITE (1 << 8) |
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#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ |
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#define AT91_SMC_DBW_8 (0 << 12) |
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#define AT91_SMC_DBW_16 (1 << 12) |
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#define AT91_SMC_DBW_32 (2 << 12) |
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#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ |
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#define AT91_SMC_TDF_(x) ((x) << 16) |
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#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ |
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#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ |
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#define AT91_SMC_PS (3 << 28) /* Page Size */ |
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#define AT91_SMC_PS_4 (0 << 28) |
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#define AT91_SMC_PS_8 (1 << 28) |
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#define AT91_SMC_PS_16 (2 << 28) |
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#define AT91_SMC_PS_32 (3 << 28) |
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|
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#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ |
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#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ |
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#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ |
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#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ |
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#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ |
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#endif |
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|
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#endif |
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Reference in new issue