commit
6d54868eeb
@ -0,0 +1,163 @@ |
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/*
|
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/acpi_table.h> |
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#include <asm/ioapic.h> |
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#include <asm/mpspec.h> |
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#include <asm/tables.h> |
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#include <asm/arch/iomap.h> |
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|
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void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, |
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void *dsdt) |
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{ |
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struct acpi_table_header *header = &(fadt->header); |
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u16 pmbase = ACPI_BASE_ADDRESS; |
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memset((void *)fadt, 0, sizeof(struct acpi_fadt)); |
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acpi_fill_header(header, "FACP"); |
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header->length = sizeof(struct acpi_fadt); |
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header->revision = 4; |
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fadt->firmware_ctrl = (u32)facs; |
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fadt->dsdt = (u32)dsdt; |
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fadt->preferred_pm_profile = ACPI_PM_MOBILE; |
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fadt->sci_int = 9; |
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fadt->smi_cmd = 0; |
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fadt->acpi_enable = 0; |
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fadt->acpi_disable = 0; |
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fadt->s4bios_req = 0; |
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fadt->pstate_cnt = 0; |
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fadt->pm1a_evt_blk = pmbase; |
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fadt->pm1b_evt_blk = 0x0; |
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fadt->pm1a_cnt_blk = pmbase + 0x4; |
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fadt->pm1b_cnt_blk = 0x0; |
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fadt->pm2_cnt_blk = pmbase + 0x50; |
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fadt->pm_tmr_blk = pmbase + 0x8; |
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fadt->gpe0_blk = pmbase + 0x20; |
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fadt->gpe1_blk = 0; |
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fadt->pm1_evt_len = 4; |
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fadt->pm1_cnt_len = 2; |
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fadt->pm2_cnt_len = 1; |
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fadt->pm_tmr_len = 4; |
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fadt->gpe0_blk_len = 8; |
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fadt->gpe1_blk_len = 0; |
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fadt->gpe1_base = 0; |
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fadt->cst_cnt = 0; |
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
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fadt->flush_size = 0; |
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fadt->flush_stride = 0; |
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fadt->duty_offset = 1; |
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fadt->duty_width = 0; |
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fadt->day_alrm = 0x0d; |
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fadt->mon_alrm = 0x00; |
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fadt->century = 0x00; |
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fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
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fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
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ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | |
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ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER | |
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ACPI_FADT_PLATFORM_CLOCK; |
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fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->reset_reg.bit_width = 8; |
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fadt->reset_reg.bit_offset = 0; |
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fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
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fadt->reset_reg.addrl = IO_PORT_RESET; |
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fadt->reset_reg.addrh = 0; |
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fadt->reset_value = SYS_RST | RST_CPU; |
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fadt->x_firmware_ctl_l = (u32)facs; |
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fadt->x_firmware_ctl_h = 0; |
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fadt->x_dsdt_l = (u32)dsdt; |
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fadt->x_dsdt_h = 0; |
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; |
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fadt->x_pm1a_evt_blk.bit_offset = 0; |
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
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fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; |
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fadt->x_pm1a_evt_blk.addrh = 0x0; |
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fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm1b_evt_blk.bit_width = 0; |
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fadt->x_pm1b_evt_blk.bit_offset = 0; |
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fadt->x_pm1b_evt_blk.access_size = 0; |
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fadt->x_pm1b_evt_blk.addrl = 0x0; |
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fadt->x_pm1b_evt_blk.addrh = 0x0; |
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fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; |
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fadt->x_pm1a_cnt_blk.bit_offset = 0; |
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
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fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; |
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fadt->x_pm1a_cnt_blk.addrh = 0x0; |
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fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm1b_cnt_blk.bit_width = 0; |
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fadt->x_pm1b_cnt_blk.bit_offset = 0; |
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fadt->x_pm1b_cnt_blk.access_size = 0; |
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fadt->x_pm1b_cnt_blk.addrl = 0x0; |
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fadt->x_pm1b_cnt_blk.addrh = 0x0; |
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fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; |
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fadt->x_pm2_cnt_blk.bit_offset = 0; |
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fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
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fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; |
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fadt->x_pm2_cnt_blk.addrh = 0x0; |
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
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fadt->x_pm_tmr_blk.bit_offset = 0; |
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
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fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; |
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fadt->x_pm_tmr_blk.addrh = 0x0; |
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; |
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fadt->x_gpe0_blk.bit_offset = 0; |
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
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fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; |
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fadt->x_gpe0_blk.addrh = 0x0; |
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fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
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fadt->x_gpe1_blk.bit_width = 0; |
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fadt->x_gpe1_blk.bit_offset = 0; |
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fadt->x_gpe1_blk.access_size = 0; |
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fadt->x_gpe1_blk.addrl = 0x0; |
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fadt->x_gpe1_blk.addrh = 0x0; |
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header->checksum = table_compute_checksum(fadt, header->length); |
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} |
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static int acpi_create_madt_irq_overrides(u32 current) |
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{ |
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struct acpi_madt_irqoverride *irqovr; |
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u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; |
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int length = 0; |
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irqovr = (void *)current; |
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length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); |
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irqovr = (void *)(current + length); |
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length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags); |
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return length; |
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} |
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u32 acpi_fill_madt(u32 current) |
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{ |
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current += acpi_create_madt_lapics(current); |
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current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current, |
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2, IO_APIC_ADDR, 0); |
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current += acpi_create_madt_irq_overrides(current); |
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return current; |
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} |
@ -0,0 +1,43 @@ |
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/*
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* (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/e820.h> |
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unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) |
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{ |
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entries[0].addr = 0; |
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entries[0].size = ISA_START_ADDRESS; |
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entries[0].type = E820_RAM; |
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entries[1].addr = ISA_START_ADDRESS; |
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entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; |
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entries[1].type = E820_RESERVED; |
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/*
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* since we use memalign(malloc) to allocate high memory for |
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* storing ACPI tables, we need to reserve them in e820 tables, |
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* otherwise kernel will reclaim them and data will be corrupted |
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*/ |
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entries[2].addr = ISA_END_ADDRESS; |
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entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS; |
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entries[2].type = E820_RAM; |
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/* for simplicity, reserve entire malloc space */ |
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entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN; |
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entries[3].size = TOTAL_MALLOC_LEN; |
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entries[3].type = E820_RESERVED; |
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entries[4].addr = gd->relocaddr; |
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entries[4].size = gd->ram_size - gd->relocaddr; |
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entries[4].type = E820_RESERVED; |
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entries[5].addr = CONFIG_PCIE_ECAM_BASE; |
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entries[5].size = CONFIG_PCIE_ECAM_SIZE; |
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entries[5].type = E820_RESERVED; |
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return 6; |
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} |
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@ -1,24 +0,0 @@ |
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/*
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* From coreboot |
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* |
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* Copyright (C) 2004 SUSE LINUX AG |
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* Copyright (C) 2004 Nick Barker |
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* Copyright (C) 2008-2009 coresystems GmbH |
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* (Written by Stefan Reinauer <stepan@coresystems.de>) |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef __ASM_ACPI_H |
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#define __ASM_ACPI_H |
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#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ |
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#define ACPI_TABLE_CREATOR "U-BootAC" /* Must be exactly 8 bytes long! */ |
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#define OEM_ID "U-Boot" /* Must be exactly 6 bytes long! */ |
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#define ASLC "U-Bo" /* Must be exactly 4 bytes long! */ |
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/* 0 = S0, 1 = S1 ...*/ |
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int acpi_get_slp_type(void); |
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void apci_set_slp_type(int type); |
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#endif |
@ -0,0 +1,136 @@ |
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/* |
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* Copyright (C) 2008 Advanced Micro Devices, Inc. |
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
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* |
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* Modified from coreboot src/arch/x86/acpi/debug.asl |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/* POST register region */ |
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OperationRegion(X80, SystemIO, 0x80, 1) |
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Field(X80, ByteAcc, NoLock, Preserve) |
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{ |
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P80, 8 |
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} |
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/* Legacy serial port register region */ |
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OperationRegion(CREG, SystemIO, 0x3F8, 8) |
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Field(CREG, ByteAcc, NoLock, Preserve) |
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{ |
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CDAT, 8, |
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CDLM, 8, |
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, 8, |
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CLCR, 8, |
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CMCR, 8, |
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CLSR, 8 |
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} |
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/* DINI - Initialize the serial port to 115200 8-N-1 */ |
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Method(DINI) |
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{ |
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Store(0x83, CLCR) |
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Store(0x01, CDAT) /* 115200 baud (low) */ |
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Store(0x00, CDLM) /* 115200 baud (high) */ |
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Store(0x03, CLCR) /* word=8 stop=1 parity=none */ |
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Store(0x03, CMCR) /* DTR=1 RTS=1 out1/2=Off loop=Off */ |
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Store(0x00, CDLM) /* turn off interrupts */ |
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} |
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/* THRE - Wait for serial port transmitter holding register to go empty */ |
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Method(THRE) |
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{ |
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And(CLSR, 0x20, Local0) |
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While (LEqual(Local0, Zero)) { |
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And(CLSR, 0x20, Local0) |
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} |
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} |
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/* OUTX - Send a single raw character */ |
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Method(OUTX, 1) |
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{ |
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THRE() |
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Store(Arg0, CDAT) |
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} |
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/* OUTC - Send a single character, expanding LF into CR/LF */ |
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Method(OUTC, 1) |
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{ |
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If (LEqual(Arg0, 0x0a)) { |
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OUTX(0x0d) |
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} |
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OUTX(Arg0) |
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} |
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/* DBGN - Send a single hex nibble */ |
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Method(DBGN, 1) |
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{ |
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And(Arg0, 0x0f, Local0) |
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If (LLess(Local0, 10)) { |
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Add(Local0, 0x30, Local0) |
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} Else { |
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Add(Local0, 0x37, Local0) |
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} |
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OUTC(Local0) |
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} |
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|
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/* DBGB - Send a hex byte */ |
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Method(DBGB, 1) |
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{ |
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ShiftRight(Arg0, 4, Local0) |
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DBGN(Local0) |
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DBGN(Arg0) |
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} |
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/* DBGW - Send a hex word */ |
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Method(DBGW, 1) |
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{ |
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ShiftRight(Arg0, 8, Local0) |
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DBGB(Local0) |
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DBGB(Arg0) |
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} |
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/* DBGD - Send a hex dword */ |
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Method(DBGD, 1) |
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{ |
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ShiftRight(Arg0, 16, Local0) |
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DBGW(Local0) |
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DBGW(Arg0) |
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} |
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/* Get a char from a string */ |
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Method(GETC, 2) |
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{ |
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CreateByteField(Arg0, Arg1, DBGC) |
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Return (DBGC) |
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} |
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|
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/* DBGO - Send either a string or an integer */ |
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Method(DBGO, 1, Serialized) |
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{ |
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If (LEqual(ObjectType(Arg0), 1)) { |
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If (LGreater(Arg0, 0xffff)) { |
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DBGD(Arg0) |
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} Else { |
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If (LGreater(Arg0, 0xff)) { |
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DBGW(Arg0) |
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} Else { |
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DBGB(Arg0) |
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} |
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} |
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} Else { |
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Name(BDBG, Buffer(80) {}) |
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Store(Arg0, BDBG) |
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Store(0, Local1) |
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While (One) { |
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Store(GETC(BDBG, Local1), Local0) |
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If (LEqual(Local0, 0)) { |
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Return (Zero) |
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} |
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OUTC(Local0) |
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Increment(Local1) |
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} |
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} |
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Return (Zero) |
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} |
@ -0,0 +1,113 @@ |
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/* |
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* Copyright (C) 2008 Advanced Micro Devices, Inc. |
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
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* |
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* Modified from coreboot src/arch/x86/acpi/globutil.asl |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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Method(MIN, 2) |
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{ |
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If (LLess(Arg0, Arg1)) { |
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Return (Arg0) |
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} Else { |
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Return (Arg1) |
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} |
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} |
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|
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Method(SLEN, 1) |
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{ |
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Store(Arg0, Local0) |
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Return (Sizeof(Local0)) |
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} |
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|
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Method(S2BF, 1, Serialized) |
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{ |
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Add(SLEN(Arg0), One, Local0) |
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Name(BUFF, Buffer(Local0) {}) |
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Store(Arg0, BUFF) |
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Return (BUFF) |
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} |
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|
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/* |
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* SCMP - Strong string compare |
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* |
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* Checks both length and content |
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*/ |
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Method(SCMP, 2) |
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{ |
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Store(S2BF(Arg0), Local0) |
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Store(S2BF(Arg1), Local1) |
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Store(Zero, Local4) |
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Store(SLEN(Arg0), Local5) |
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Store(SLEN(Arg1), Local6) |
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Store(MIN(Local5, Local6), Local7) |
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|
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While (LLess(Local4, Local7)) { |
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Store(Derefof(Index(Local0, Local4)), Local2) |
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Store(Derefof(Index(Local1, Local4)), Local3) |
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If (LGreater(Local2, Local3)) { |
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Return (One) |
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} Else { |
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If (LLess(Local2, Local3)) { |
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Return (Ones) |
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} |
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} |
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Increment(Local4) |
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} |
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|
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If (LLess(Local4, Local5)) { |
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Return (One) |
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} Else { |
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If (LLess(Local4, Local6)) { |
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Return (Ones) |
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} Else { |
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Return (Zero) |
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} |
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} |
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} |
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|
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/* |
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* WCMP - Weak string compare |
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* |
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* Checks to find Arg1 at beginning of Arg0. |
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* Fails if length(Arg0) < length(Arg1). |
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* Returns 0 on fail, 1 on pass. |
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*/ |
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Method(WCMP, 2) |
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{ |
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Store(S2BF(Arg0), Local0) |
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Store(S2BF(Arg1), Local1) |
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If (LLess(SLEN(Arg0), SLEN(Arg1))) { |
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Return (Zero) |
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} |
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Store(Zero, Local2) |
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Store(SLEN(Arg1), Local3) |
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|
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While (LLess(Local2, Local3)) { |
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If (LNotEqual(Derefof(Index(Local0, Local2)), |
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Derefof(Index(Local1, Local2)))) { |
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Return (Zero) |
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} |
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Increment(Local2) |
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} |
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|
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Return (One) |
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} |
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|
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/* |
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* I2BM - Returns Bit Map |
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* |
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* Arg0 = IRQ Number (0-15) |
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*/ |
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Method(I2BM, 1) |
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{ |
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Store(0, Local0) |
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If (LNotEqual(Arg0, 0)) { |
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Store(1, Local1) |
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ShiftLeft(Local1, Arg0, Local0) |
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} |
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|
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Return (Local0) |
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} |
@ -0,0 +1,82 @@ |
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/* |
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* Copyright (C) 2008 Advanced Micro Devices, Inc. |
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
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* |
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* Modified from coreboot src/arch/x86/acpi/statdef.asl |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* Status and notification definitions */ |
||||
|
||||
#define STA_MISSING 0x00 |
||||
#define STA_PRESENT 0x01 |
||||
#define STA_ENABLED 0x03 |
||||
#define STA_DISABLED 0x09 |
||||
#define STA_INVISIBLE 0x0b |
||||
#define STA_UNAVAILABLE 0x0d |
||||
#define STA_VISIBLE 0x0f |
||||
|
||||
/* SMBus status codes */ |
||||
#define SMB_OK 0x00 |
||||
#define SMB_UNKNOWN_FAIL 0x07 |
||||
#define SMB_DEV_ADDR_NAK 0x10 |
||||
#define SMB_DEVICE_ERROR 0x11 |
||||
#define SMB_DEV_CMD_DENIED 0x12 |
||||
#define SMB_UNKNOWN_ERR 0x13 |
||||
#define SMB_DEV_ACC_DENIED 0x17 |
||||
#define SMB_TIMEOUT 0x18 |
||||
#define SMB_HST_UNSUPP_PROTOCOL 0x19 |
||||
#define SMB_BUSY 0x1a |
||||
#define SMB_PKT_CHK_ERROR 0x1f |
||||
|
||||
/* Device Object Notification Values */ |
||||
#define NOTIFY_BUS_CHECK 0x00 |
||||
#define NOTIFY_DEVICE_CHECK 0x01 |
||||
#define NOTIFY_DEVICE_WAKE 0x02 |
||||
#define NOTIFY_EJECT_REQUEST 0x03 |
||||
#define NOTIFY_DEVICE_CHECK_JR 0x04 |
||||
#define NOTIFY_FREQUENCY_ERROR 0x05 |
||||
#define NOTIFY_BUS_MODE 0x06 |
||||
#define NOTIFY_POWER_FAULT 0x07 |
||||
#define NOTIFY_CAPABILITIES 0x08 |
||||
#define NOTIFY_PLD_CHECK 0x09 |
||||
#define NOTIFY_SLIT_UPDATE 0x0b |
||||
#define NOTIFY_SRA_UPDATE 0x0d |
||||
|
||||
/* Battery Device Notification Values */ |
||||
#define NOTIFY_BAT_STATUSCHG 0x80 |
||||
#define NOTIFY_BAT_INFOCHG 0x81 |
||||
#define NOTIFY_BAT_MAINTDATA 0x82 |
||||
|
||||
/* Power Source Object Notification Values */ |
||||
#define NOTIFY_PWR_STATUSCHG 0x80 |
||||
#define NOTIFY_PWR_INFOCHG 0x81 |
||||
|
||||
/* Thermal Zone Object Notification Values */ |
||||
#define NOTIFY_TZ_STATUSCHG 0x80 |
||||
#define NOTIFY_TZ_TRIPPTCHG 0x81 |
||||
#define NOTIFY_TZ_DEVLISTCHG 0x82 |
||||
#define NOTIFY_TZ_RELTBLCHG 0x83 |
||||
|
||||
/* Power Button Notification Values */ |
||||
#define NOTIFY_POWER_BUTTON 0x80 |
||||
|
||||
/* Sleep Button Notification Values */ |
||||
#define NOTIFY_SLEEP_BUTTON 0x80 |
||||
|
||||
/* Lid Notification Values */ |
||||
#define NOTIFY_LID_STATUSCHG 0x80 |
||||
|
||||
/* Processor Device Notification Values */ |
||||
#define NOTIFY_CPU_PPCCHG 0x80 |
||||
#define NOTIFY_CPU_CSTATECHG 0x81 |
||||
#define NOTIFY_CPU_THROTLCHG 0x82 |
||||
|
||||
/* User Presence Device Notification Values */ |
||||
#define NOTIFY_USR_PRESNCECHG 0x80 |
||||
|
||||
/* Ambient Light Sensor Notification Values */ |
||||
#define NOTIFY_ALS_ILLUMCHG 0x80 |
||||
#define NOTIFY_ALS_COLORTMPCHG 0x81 |
||||
#define NOTIFY_ALS_RESPCHG 0x82 |
@ -0,0 +1,95 @@ |
||||
/* |
||||
* Copyright (C) 2013 Google Inc. |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* SouthCluster GPIO */ |
||||
Device (GPSC) |
||||
{ |
||||
Name(_HID, "INT33FC") |
||||
Name(_CID, "INT33FC") |
||||
Name(_UID, 1) |
||||
|
||||
Name(RBUF, ResourceTemplate() |
||||
{ |
||||
Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) |
||||
Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) |
||||
{ |
||||
GPIO_SC_IRQ |
||||
} |
||||
}) |
||||
|
||||
Method(_CRS) |
||||
{ |
||||
CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) |
||||
Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) |
||||
Return (^RBUF) |
||||
} |
||||
|
||||
Method(_STA) |
||||
{ |
||||
Return (STA_VISIBLE) |
||||
} |
||||
} |
||||
|
||||
/* NorthCluster GPIO */ |
||||
Device (GPNC) |
||||
{ |
||||
Name(_HID, "INT33FC") |
||||
Name(_CID, "INT33FC") |
||||
Name(_UID, 2) |
||||
|
||||
Name(RBUF, ResourceTemplate() |
||||
{ |
||||
Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) |
||||
Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) |
||||
{ |
||||
GPIO_NC_IRQ |
||||
} |
||||
}) |
||||
|
||||
Method(_CRS) |
||||
{ |
||||
CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) |
||||
Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) |
||||
Return (^RBUF) |
||||
} |
||||
|
||||
Method(_STA) |
||||
{ |
||||
Return (STA_VISIBLE) |
||||
} |
||||
} |
||||
|
||||
/* SUS GPIO */ |
||||
Device (GPSS) |
||||
{ |
||||
Name(_HID, "INT33FC") |
||||
Name(_CID, "INT33FC") |
||||
Name(_UID, 3) |
||||
|
||||
Name(RBUF, ResourceTemplate() |
||||
{ |
||||
Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) |
||||
Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) |
||||
{ |
||||
GPIO_SUS_IRQ |
||||
} |
||||
}) |
||||
|
||||
Method(_CRS) |
||||
{ |
||||
CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) |
||||
Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) |
||||
Return (^RBUF) |
||||
} |
||||
|
||||
Method(_STA) |
||||
{ |
||||
Return (STA_VISIBLE) |
||||
} |
||||
} |
@ -0,0 +1,111 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Google Inc. |
||||
* Copyright (C) 2014 Sage Electronics Engineering, LLC. |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* This file intentionally gets included multiple times, to set pic and apic |
||||
* modes, so should not have guard statements added. |
||||
*/ |
||||
|
||||
/*
|
||||
* This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ |
||||
* routing for the platform being compiled. |
||||
* |
||||
* This method uses #defines in irqroute.h along with the macros contained |
||||
* in this file to generate an IRQ routing for each PCI device in the system. |
||||
*/ |
||||
|
||||
#undef PCI_DEV_PIRQ_ROUTES |
||||
#undef PCI_DEV_PIRQ_ROUTE |
||||
#undef ACPI_DEV_IRQ |
||||
#undef PCIE_BRIDGE_DEV |
||||
#undef RP_IRQ_ROUTES |
||||
#undef ROOTPORT_METHODS |
||||
#undef ROOTPORT_IRQ_ROUTES |
||||
#undef RP_METHOD |
||||
|
||||
#if defined(PIC_MODE) |
||||
|
||||
#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ |
||||
Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } |
||||
|
||||
#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ |
||||
Name(prefix_ ## func_ ## P, Package() \
|
||||
{ \
|
||||
ACPI_DEV_IRQ(0x0000, 0, a_), \
|
||||
ACPI_DEV_IRQ(0x0000, 1, b_), \
|
||||
ACPI_DEV_IRQ(0x0000, 2, c_), \
|
||||
ACPI_DEV_IRQ(0x0000, 3, d_), \
|
||||
}) |
||||
|
||||
/* define as blank so ROOTPORT_METHODS only gets inserted once */ |
||||
#define ROOTPORT_METHODS(prefix_, dev_) |
||||
|
||||
#else /* defined(PIC_MODE) */ |
||||
|
||||
#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ |
||||
Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } |
||||
|
||||
#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ |
||||
Name(prefix_ ## func_ ## A, Package() \
|
||||
{ \
|
||||
ACPI_DEV_IRQ(0x0000, 0, a_), \
|
||||
ACPI_DEV_IRQ(0x0000, 1, b_), \
|
||||
ACPI_DEV_IRQ(0x0000, 2, c_), \
|
||||
ACPI_DEV_IRQ(0x0000, 3, d_), \
|
||||
}) |
||||
|
||||
#define ROOTPORT_METHODS(prefix_, dev_) \ |
||||
RP_METHOD(prefix_, dev_, 0) \
|
||||
RP_METHOD(prefix_, dev_, 1) \
|
||||
RP_METHOD(prefix_, dev_, 2) \
|
||||
RP_METHOD(prefix_, dev_, 3) \
|
||||
RP_METHOD(prefix_, dev_, 4) \
|
||||
RP_METHOD(prefix_, dev_, 5) \
|
||||
RP_METHOD(prefix_, dev_, 6) \
|
||||
RP_METHOD(prefix_, dev_, 7) |
||||
|
||||
#endif /* defined(PIC_MODE) */ |
||||
|
||||
#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ |
||||
ACPI_DEV_IRQ(dev_, 0, a_), \
|
||||
ACPI_DEV_IRQ(dev_, 1, b_), \
|
||||
ACPI_DEV_IRQ(dev_, 2, c_), \
|
||||
ACPI_DEV_IRQ(dev_, 3, d_) |
||||
|
||||
#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \ |
||||
ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
|
||||
ROOTPORT_METHODS(prefix_, dev_) |
||||
|
||||
#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ |
||||
RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
|
||||
RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
|
||||
RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
|
||||
RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
|
||||
RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
|
||||
RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
|
||||
RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
|
||||
RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_) |
||||
|
||||
#define RP_METHOD(prefix_, dev_, func_)\ |
||||
Device (prefix_ ## 0 ## func_) \
|
||||
{ \
|
||||
Name(_ADR, dev_ ## 000 ## func_) \
|
||||
Name(_PRW, Package() { 0, 0 }) \
|
||||
Method(_PRT) { \
|
||||
If (PICM) { \
|
||||
Return (prefix_ ## func_ ## A) \
|
||||
} Else { \
|
||||
Return (prefix_ ## func_ ## P) \
|
||||
} \
|
||||
} \
|
||||
} |
||||
|
||||
/* SoC specific PIRQ route configuration */ |
||||
#include "irqroute.h" |
@ -0,0 +1,493 @@ |
||||
/* |
||||
* Copyright (C) 2007-2009 coresystems GmbH |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
Scope (\) |
||||
{ |
||||
/* Intel Legacy Block */ |
||||
OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) |
||||
Field(ILBS, AnyAcc, NoLock, Preserve) { |
||||
Offset (0x8), |
||||
PRTA, 8, |
||||
PRTB, 8, |
||||
PRTC, 8, |
||||
PRTD, 8, |
||||
PRTE, 8, |
||||
PRTF, 8, |
||||
PRTG, 8, |
||||
PRTH, 8, |
||||
Offset (0x88), |
||||
, 3, |
||||
UI3E, 1, |
||||
UI4E, 1 |
||||
} |
||||
} |
||||
|
||||
Device (LNKA) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0F")) |
||||
Name(_UID, 1) |
||||
|
||||
/* Disable method */ |
||||
Method(_DIS, 0, Serialized) |
||||
{ |
||||
Store(0x80, PRTA) |
||||
} |
||||
|
||||
/* Possible Resource Settings for this Link */ |
||||
Name(_PRS, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } |
||||
}) |
||||
|
||||
/* Current Resource Settings for this link */ |
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
Name(RTLA, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) {} |
||||
}) |
||||
CreateWordField(RTLA, 1, IRQ0) |
||||
|
||||
/* Clear the WordField */ |
||||
Store(Zero, IRQ0) |
||||
|
||||
/* Set the bit from PRTA */ |
||||
ShiftLeft(1, And(PRTA, 0x0f), IRQ0) |
||||
|
||||
Return (RTLA) |
||||
} |
||||
|
||||
/* Set Resource Setting for this IRQ link */ |
||||
Method(_SRS, 1, Serialized) |
||||
{ |
||||
CreateWordField(Arg0, 1, IRQ0) |
||||
|
||||
/* Which bit is set? */ |
||||
FindSetRightBit(IRQ0, Local0) |
||||
|
||||
Decrement(Local0) |
||||
Store(Local0, PRTA) |
||||
} |
||||
|
||||
/* Status */ |
||||
Method(_STA, 0, Serialized) |
||||
{ |
||||
If (And(PRTA, 0x80)) { |
||||
Return (STA_DISABLED) |
||||
} Else { |
||||
Return (STA_INVISIBLE) |
||||
} |
||||
} |
||||
} |
||||
|
||||
Device (LNKB) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0F")) |
||||
Name(_UID, 2) |
||||
|
||||
/* Disable method */ |
||||
Method(_DIS, 0, Serialized) |
||||
{ |
||||
Store(0x80, PRTB) |
||||
} |
||||
|
||||
/* Possible Resource Settings for this Link */ |
||||
Name(_PRS, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } |
||||
}) |
||||
|
||||
/* Current Resource Settings for this link */ |
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
Name(RTLB, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) {} |
||||
}) |
||||
CreateWordField(RTLB, 1, IRQ0) |
||||
|
||||
/* Clear the WordField */ |
||||
Store(Zero, IRQ0) |
||||
|
||||
/* Set the bit from PRTB */ |
||||
ShiftLeft(1, And(PRTB, 0x0f), IRQ0) |
||||
|
||||
Return (RTLB) |
||||
} |
||||
|
||||
/* Set Resource Setting for this IRQ link */ |
||||
Method(_SRS, 1, Serialized) |
||||
{ |
||||
CreateWordField(Arg0, 1, IRQ0) |
||||
|
||||
/* Which bit is set? */ |
||||
FindSetRightBit(IRQ0, Local0) |
||||
|
||||
Decrement(Local0) |
||||
Store(Local0, PRTB) |
||||
} |
||||
|
||||
/* Status */ |
||||
Method(_STA, 0, Serialized) |
||||
{ |
||||
If (And(PRTB, 0x80)) { |
||||
Return (STA_DISABLED) |
||||
} Else { |
||||
Return (STA_INVISIBLE) |
||||
} |
||||
} |
||||
} |
||||
|
||||
Device (LNKC) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0F")) |
||||
Name(_UID, 3) |
||||
|
||||
/* Disable method */ |
||||
Method(_DIS, 0, Serialized) |
||||
{ |
||||
Store(0x80, PRTC) |
||||
} |
||||
|
||||
/* Possible Resource Settings for this Link */ |
||||
Name(_PRS, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } |
||||
}) |
||||
|
||||
/* Current Resource Settings for this link */ |
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
Name(RTLC, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) {} |
||||
}) |
||||
CreateWordField(RTLC, 1, IRQ0) |
||||
|
||||
/* Clear the WordField */ |
||||
Store(Zero, IRQ0) |
||||
|
||||
/* Set the bit from PRTC */ |
||||
ShiftLeft(1, And(PRTC, 0x0f), IRQ0) |
||||
|
||||
Return (RTLC) |
||||
} |
||||
|
||||
/* Set Resource Setting for this IRQ link */ |
||||
Method(_SRS, 1, Serialized) |
||||
{ |
||||
CreateWordField(Arg0, 1, IRQ0) |
||||
|
||||
/* Which bit is set? */ |
||||
FindSetRightBit(IRQ0, Local0) |
||||
|
||||
Decrement(Local0) |
||||
Store(Local0, PRTC) |
||||
} |
||||
|
||||
/* Status */ |
||||
Method(_STA, 0, Serialized) |
||||
{ |
||||
If (And(PRTC, 0x80)) { |
||||
Return (STA_DISABLED) |
||||
} Else { |
||||
Return (STA_INVISIBLE) |
||||
} |
||||
} |
||||
} |
||||
|
||||
Device (LNKD) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0F")) |
||||
Name(_UID, 4) |
||||
|
||||
/* Disable method */ |
||||
Method(_DIS, 0, Serialized) |
||||
{ |
||||
Store(0x80, PRTD) |
||||
} |
||||
|
||||
/* Possible Resource Settings for this Link */ |
||||
Name(_PRS, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } |
||||
}) |
||||
|
||||
/* Current Resource Settings for this link */ |
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
Name(RTLD, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) {} |
||||
}) |
||||
CreateWordField(RTLD, 1, IRQ0) |
||||
|
||||
/* Clear the WordField */ |
||||
Store(Zero, IRQ0) |
||||
|
||||
/* Set the bit from PRTD */ |
||||
ShiftLeft(1, And(PRTD, 0x0f), IRQ0) |
||||
|
||||
Return (RTLD) |
||||
} |
||||
|
||||
/* Set Resource Setting for this IRQ link */ |
||||
Method(_SRS, 1, Serialized) |
||||
{ |
||||
CreateWordField(Arg0, 1, IRQ0) |
||||
|
||||
/* Which bit is set? */ |
||||
FindSetRightBit(IRQ0, Local0) |
||||
|
||||
Decrement(Local0) |
||||
Store(Local0, PRTD) |
||||
} |
||||
|
||||
/* Status */ |
||||
Method(_STA, 0, Serialized) |
||||
{ |
||||
If (And(PRTD, 0x80)) { |
||||
Return (STA_DISABLED) |
||||
} Else { |
||||
Return (STA_INVISIBLE) |
||||
} |
||||
} |
||||
} |
||||
|
||||
Device (LNKE) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0F")) |
||||
Name(_UID, 5) |
||||
|
||||
/* Disable method */ |
||||
Method(_DIS, 0, Serialized) |
||||
{ |
||||
Store(0x80, PRTE) |
||||
} |
||||
|
||||
/* Possible Resource Settings for this Link */ |
||||
Name(_PRS, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } |
||||
}) |
||||
|
||||
/* Current Resource Settings for this link */ |
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
Name(RTLE, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) {} |
||||
}) |
||||
CreateWordField(RTLE, 1, IRQ0) |
||||
|
||||
/* Clear the WordField */ |
||||
Store(Zero, IRQ0) |
||||
|
||||
/* Set the bit from PRTE */ |
||||
ShiftLeft(1, And(PRTE, 0x0f), IRQ0) |
||||
|
||||
Return (RTLE) |
||||
} |
||||
|
||||
/* Set Resource Setting for this IRQ link */ |
||||
Method(_SRS, 1, Serialized) |
||||
{ |
||||
CreateWordField(Arg0, 1, IRQ0) |
||||
|
||||
/* Which bit is set? */ |
||||
FindSetRightBit(IRQ0, Local0) |
||||
|
||||
Decrement(Local0) |
||||
Store(Local0, PRTE) |
||||
} |
||||
|
||||
/* Status */ |
||||
Method(_STA, 0, Serialized) |
||||
{ |
||||
If (And(PRTE, 0x80)) { |
||||
Return (STA_DISABLED) |
||||
} Else { |
||||
Return (STA_INVISIBLE) |
||||
} |
||||
} |
||||
} |
||||
|
||||
Device (LNKF) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0F")) |
||||
Name(_UID, 6) |
||||
|
||||
/* Disable method */ |
||||
Method(_DIS, 0, Serialized) |
||||
{ |
||||
Store(0x80, PRTF) |
||||
} |
||||
|
||||
/* Possible Resource Settings for this Link */ |
||||
Name(_PRS, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } |
||||
}) |
||||
|
||||
/* Current Resource Settings for this link */ |
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
Name(RTLF, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) {} |
||||
}) |
||||
CreateWordField(RTLF, 1, IRQ0) |
||||
|
||||
/* Clear the WordField */ |
||||
Store(Zero, IRQ0) |
||||
|
||||
/* Set the bit from PRTF */ |
||||
ShiftLeft(1, And(PRTF, 0x0f), IRQ0) |
||||
|
||||
Return (RTLF) |
||||
} |
||||
|
||||
/* Set Resource Setting for this IRQ link */ |
||||
Method(_SRS, 1, Serialized) |
||||
{ |
||||
CreateWordField(Arg0, 1, IRQ0) |
||||
|
||||
/* Which bit is set? */ |
||||
FindSetRightBit(IRQ0, Local0) |
||||
|
||||
Decrement(Local0) |
||||
Store(Local0, PRTF) |
||||
} |
||||
|
||||
/* Status */ |
||||
Method(_STA, 0, Serialized) |
||||
{ |
||||
If (And(PRTF, 0x80)) { |
||||
Return (STA_DISABLED) |
||||
} Else { |
||||
Return (STA_INVISIBLE) |
||||
} |
||||
} |
||||
} |
||||
|
||||
Device (LNKG) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0F")) |
||||
Name(_UID, 7) |
||||
|
||||
/* Disable method */ |
||||
Method(_DIS, 0, Serialized) |
||||
{ |
||||
Store(0x80, PRTG) |
||||
} |
||||
|
||||
/* Possible Resource Settings for this Link */ |
||||
Name(_PRS, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } |
||||
}) |
||||
|
||||
/* Current Resource Settings for this link */ |
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
Name(RTLG, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) {} |
||||
}) |
||||
CreateWordField(RTLG, 1, IRQ0) |
||||
|
||||
/* Clear the WordField */ |
||||
Store(Zero, IRQ0) |
||||
|
||||
/* Set the bit from PRTG */ |
||||
ShiftLeft(1, And(PRTG, 0x0f), IRQ0) |
||||
|
||||
Return (RTLG) |
||||
} |
||||
|
||||
/* Set Resource Setting for this IRQ link */ |
||||
Method(_SRS, 1, Serialized) |
||||
{ |
||||
CreateWordField(Arg0, 1, IRQ0) |
||||
|
||||
/* Which bit is set? */ |
||||
FindSetRightBit(IRQ0, Local0) |
||||
|
||||
Decrement(Local0) |
||||
Store(Local0, PRTG) |
||||
} |
||||
|
||||
/* Status */ |
||||
Method(_STA, 0, Serialized) |
||||
{ |
||||
If (And(PRTG, 0x80)) { |
||||
Return (STA_DISABLED) |
||||
} Else { |
||||
Return (STA_INVISIBLE) |
||||
} |
||||
} |
||||
} |
||||
|
||||
Device (LNKH) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0F")) |
||||
Name(_UID, 8) |
||||
|
||||
/* Disable method */ |
||||
Method(_DIS, 0, Serialized) |
||||
{ |
||||
Store(0x80, PRTH) |
||||
} |
||||
|
||||
/* Possible Resource Settings for this Link */ |
||||
Name(_PRS, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } |
||||
}) |
||||
|
||||
/* Current Resource Settings for this link */ |
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
Name(RTLH, ResourceTemplate() |
||||
{ |
||||
IRQ(Level, ActiveLow, Shared) {} |
||||
}) |
||||
CreateWordField(RTLH, 1, IRQ0) |
||||
|
||||
/* Clear the WordField */ |
||||
Store(Zero, IRQ0) |
||||
|
||||
/* Set the bit from PRTH */ |
||||
ShiftLeft(1, And(PRTH, 0x0f), IRQ0) |
||||
|
||||
Return (RTLH) |
||||
} |
||||
|
||||
/* Set Resource Setting for this IRQ link */ |
||||
Method(_SRS, 1, Serialized) |
||||
{ |
||||
CreateWordField(Arg0, 1, IRQ0) |
||||
|
||||
/* Which bit is set? */ |
||||
FindSetRightBit(IRQ0, Local0) |
||||
|
||||
Decrement(Local0) |
||||
Store(Local0, PRTH) |
||||
} |
||||
|
||||
/* Status */ |
||||
Method(_STA, 0, Serialized) |
||||
{ |
||||
If (And(PRTH, 0x80)) { |
||||
Return (STA_DISABLED) |
||||
} Else { |
||||
Return (STA_INVISIBLE) |
||||
} |
||||
} |
||||
} |
@ -0,0 +1,48 @@ |
||||
/* |
||||
* Copyright (C) 2007-2009 coresystems GmbH |
||||
* Copyright (C) 2013 Google Inc. |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
Name(\PICM, 0) |
||||
|
||||
/* |
||||
* The _PIC method is called by the OS to choose between interrupt |
||||
* routing via the i8259 interrupt controller or the APIC. |
||||
* |
||||
* _PIC is called with a parameter of 0 for i8259 configuration and |
||||
* with a parameter of 1 for Local APIC/IOAPIC configuration. |
||||
*/ |
||||
Method(\_PIC, 1) |
||||
{ |
||||
/* Remember the OS' IRQ routing choice */ |
||||
Store(Arg0, PICM) |
||||
} |
||||
|
||||
/* PCI interrupt routing */ |
||||
Method(_PRT) { |
||||
If (PICM) { |
||||
Return (Package() { |
||||
#undef PIC_MODE |
||||
#include "irq_helper.h" |
||||
PCI_DEV_PIRQ_ROUTES |
||||
}) |
||||
} Else { |
||||
Return (Package() { |
||||
#define PIC_MODE |
||||
#include "irq_helper.h" |
||||
PCI_DEV_PIRQ_ROUTES |
||||
}) |
||||
} |
||||
|
||||
} |
||||
|
||||
/* PCIe downstream ports interrupt routing */ |
||||
PCIE_BRIDGE_IRQ_ROUTES |
||||
#undef PIC_MODE |
||||
#include "irq_helper.h" |
||||
PCIE_BRIDGE_IRQ_ROUTES |
@ -0,0 +1,27 @@ |
||||
/*
|
||||
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm/arch/device.h> |
||||
|
||||
#define PCI_DEV_PIRQ_ROUTES \ |
||||
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(EMMC_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SD_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(MMC45_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
|
||||
PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
|
||||
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \
|
||||
PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) |
||||
|
||||
#define PCIE_BRIDGE_IRQ_ROUTES \ |
||||
PCIE_BRIDGE_DEV(RP, PCIE_DEV, A, B, C, D) |
@ -0,0 +1,181 @@ |
||||
/* |
||||
* Copyright (C) 2007-2009 coresystems GmbH |
||||
* Copyright (C) 2013 Google Inc. |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* Intel LPC Bus Device - 0:1f.0 */ |
||||
|
||||
Device (LPCB) |
||||
{ |
||||
Name(_ADR, 0x001f0000) |
||||
|
||||
OperationRegion(LPC0, PCI_Config, 0x00, 0x100) |
||||
Field(LPC0, AnyAcc, NoLock, Preserve) { |
||||
Offset(0x08), |
||||
SRID, 8, |
||||
Offset(0x80), |
||||
C1EN, 1, |
||||
Offset(0x84) |
||||
} |
||||
|
||||
#include "irqlinks.asl" |
||||
|
||||
/* Firmware Hub */ |
||||
Device (FWH) |
||||
{ |
||||
Name(_HID, EISAID("INT0800")) |
||||
Name(_CRS, ResourceTemplate() |
||||
{ |
||||
Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) |
||||
}) |
||||
} |
||||
|
||||
/* 8259 Interrupt Controller */ |
||||
Device (PIC) |
||||
{ |
||||
Name(_HID, EISAID("PNP0000")) |
||||
Name(_CRS, ResourceTemplate() |
||||
{ |
||||
IO(Decode16, 0x20, 0x20, 0x01, 0x02) |
||||
IO(Decode16, 0x24, 0x24, 0x01, 0x02) |
||||
IO(Decode16, 0x28, 0x28, 0x01, 0x02) |
||||
IO(Decode16, 0x2c, 0x2c, 0x01, 0x02) |
||||
IO(Decode16, 0x30, 0x30, 0x01, 0x02) |
||||
IO(Decode16, 0x34, 0x34, 0x01, 0x02) |
||||
IO(Decode16, 0x38, 0x38, 0x01, 0x02) |
||||
IO(Decode16, 0x3c, 0x3c, 0x01, 0x02) |
||||
IO(Decode16, 0xa0, 0xa0, 0x01, 0x02) |
||||
IO(Decode16, 0xa4, 0xa4, 0x01, 0x02) |
||||
IO(Decode16, 0xa8, 0xa8, 0x01, 0x02) |
||||
IO(Decode16, 0xac, 0xac, 0x01, 0x02) |
||||
IO(Decode16, 0xb0, 0xb0, 0x01, 0x02) |
||||
IO(Decode16, 0xb4, 0xb4, 0x01, 0x02) |
||||
IO(Decode16, 0xb8, 0xb8, 0x01, 0x02) |
||||
IO(Decode16, 0xbc, 0xbc, 0x01, 0x02) |
||||
IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02) |
||||
IRQNoFlags () { 2 } |
||||
}) |
||||
} |
||||
|
||||
/* 8254 timer */ |
||||
Device (TIMR) |
||||
{ |
||||
Name(_HID, EISAID("PNP0100")) |
||||
Name(_CRS, ResourceTemplate() |
||||
{ |
||||
IO(Decode16, 0x40, 0x40, 0x01, 0x04) |
||||
IO(Decode16, 0x50, 0x50, 0x10, 0x04) |
||||
IRQNoFlags() { 0 } |
||||
}) |
||||
} |
||||
|
||||
/* HPET */ |
||||
Device (HPET) |
||||
{ |
||||
Name(_HID, EISAID("PNP0103")) |
||||
Name(_CID, 0x010CD041) |
||||
Name(_CRS, ResourceTemplate() |
||||
{ |
||||
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE) |
||||
}) |
||||
|
||||
Method(_STA) |
||||
{ |
||||
Return (STA_VISIBLE) |
||||
} |
||||
} |
||||
|
||||
/* Internal UART */ |
||||
Device (IURT) |
||||
{ |
||||
Name(_HID, EISAID("PNP0501")) |
||||
Name(_UID, 1) |
||||
|
||||
Method(_STA, 0, Serialized) |
||||
{ |
||||
/* |
||||
* TODO: |
||||
* |
||||
* Need to hide the internal UART depending on whether |
||||
* internal UART is enabled or not so that external |
||||
* SuperIO UART can be exposed to system. |
||||
*/ |
||||
Store(1, UI3E) |
||||
Store(1, UI4E) |
||||
Store(1, C1EN) |
||||
Return (STA_VISIBLE) |
||||
|
||||
} |
||||
|
||||
Method(_DIS, 0, Serialized) |
||||
{ |
||||
Store(0, UI3E) |
||||
Store(0, UI4E) |
||||
Store(0, C1EN) |
||||
} |
||||
|
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
Name(BUF0, ResourceTemplate() |
||||
{ |
||||
IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08) |
||||
IRQNoFlags() { 3 } |
||||
}) |
||||
|
||||
Name(BUF1, ResourceTemplate() |
||||
{ |
||||
IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08) |
||||
IRQNoFlags() { 4 } |
||||
}) |
||||
|
||||
If (LLessEqual(SRID, 0x04)) { |
||||
Return (BUF0) |
||||
} Else { |
||||
Return (BUF1) |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* Real Time Clock */ |
||||
Device (RTC) |
||||
{ |
||||
Name(_HID, EISAID("PNP0B00")) |
||||
Name(_CRS, ResourceTemplate() |
||||
{ |
||||
IO(Decode16, 0x70, 0x70, 1, 8) |
||||
/* |
||||
* Disable as Windows doesn't like it, and systems |
||||
* don't seem to use it |
||||
*/ |
||||
/* IRQNoFlags() { 8 } */ |
||||
}) |
||||
} |
||||
|
||||
/* LPC device: Resource consumption */ |
||||
Device (LDRC) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C02")) |
||||
Name(_UID, 2) |
||||
|
||||
Name(RBUF, ResourceTemplate() |
||||
{ |
||||
IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */ |
||||
IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */ |
||||
IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */ |
||||
IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */ |
||||
IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */ |
||||
IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */ |
||||
IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */ |
||||
}) |
||||
|
||||
Method(_CRS, 0, NotSerialized) |
||||
{ |
||||
Return (RBUF) |
||||
} |
||||
} |
||||
} |
@ -0,0 +1,36 @@ |
||||
/* |
||||
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm/acpi/statdef.asl> |
||||
#include <asm/arch/iomap.h> |
||||
#include <asm/arch/irq.h> |
||||
|
||||
/* |
||||
* The _PTS method (Prepare To Sleep) is called before the OS is |
||||
* entering a sleep state. The sleep state number is passed in Arg0. |
||||
*/ |
||||
Method(_PTS, 1) |
||||
{ |
||||
} |
||||
|
||||
/* The _WAK method is called on system wakeup */ |
||||
Method(_WAK, 1) |
||||
{ |
||||
Return (Package() {0, 0}) |
||||
} |
||||
|
||||
/* TODO: add CPU ASL support */ |
||||
|
||||
Scope (\_SB) |
||||
{ |
||||
#include "southcluster.asl" |
||||
|
||||
/* ACPI devices */ |
||||
#include "gpio.asl" |
||||
} |
||||
|
||||
/* Chipset specific sleep states */ |
||||
#include "sleepstates.asl" |
@ -0,0 +1,13 @@ |
||||
/* |
||||
* Copyright (C) 2007-2009 coresystems GmbH |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) |
||||
Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) |
||||
Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) |
||||
Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) |
@ -0,0 +1,211 @@ |
||||
/* |
||||
* Copyright (C) 2013 Google Inc. |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
Device (PCI0) |
||||
{ |
||||
Name(_HID, EISAID("PNP0A08")) /* PCIe */ |
||||
Name(_CID, EISAID("PNP0A03")) /* PCI */ |
||||
|
||||
Name(_ADR, 0) |
||||
Name(_BBN, 0) |
||||
|
||||
Name(MCRS, ResourceTemplate() |
||||
{ |
||||
/* Bus Numbers */ |
||||
WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, |
||||
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00) |
||||
|
||||
/* IO Region 0 */ |
||||
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
||||
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00) |
||||
|
||||
/* PCI Config Space */ |
||||
IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
||||
|
||||
/* IO Region 1 */ |
||||
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
||||
0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01) |
||||
|
||||
/* VGA memory (0xa0000-0xbffff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
||||
0x00020000, , , ASEG) |
||||
|
||||
/* OPROM reserved (0xc0000-0xc3fff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
||||
0x00004000, , , OPR0) |
||||
|
||||
/* OPROM reserved (0xc4000-0xc7fff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
||||
0x00004000, , , OPR1) |
||||
|
||||
/* OPROM reserved (0xc8000-0xcbfff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
||||
0x00004000, , , OPR2) |
||||
|
||||
/* OPROM reserved (0xcc000-0xcffff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
||||
0x00004000, , , OPR3) |
||||
|
||||
/* OPROM reserved (0xd0000-0xd3fff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
||||
0x00004000, , , OPR4) |
||||
|
||||
/* OPROM reserved (0xd4000-0xd7fff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
||||
0x00004000, , , OPR5) |
||||
|
||||
/* OPROM reserved (0xd8000-0xdbfff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
||||
0x00004000, , , OPR6) |
||||
|
||||
/* OPROM reserved (0xdc000-0xdffff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
||||
0x00004000, , , OPR7) |
||||
|
||||
/* BIOS Extension (0xe0000-0xe3fff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
||||
0x00004000, , , ESG0) |
||||
|
||||
/* BIOS Extension (0xe4000-0xe7fff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
||||
0x00004000, , , ESG1) |
||||
|
||||
/* BIOS Extension (0xe8000-0xebfff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
||||
0x00004000, , , ESG2) |
||||
|
||||
/* BIOS Extension (0xec000-0xeffff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
||||
0x00004000, , , ESG3) |
||||
|
||||
/* System BIOS (0xf0000-0xfffff) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
||||
0x00010000, , , FSEG) |
||||
|
||||
/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */ |
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, |
||||
0x00000000, , , PMEM) |
||||
|
||||
/* High PCI Memory Region */ |
||||
QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, |
||||
Cacheable, ReadWrite, |
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, |
||||
0x00000000, , , UMEM) |
||||
}) |
||||
|
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
/* Update PCI resource area */ |
||||
CreateDwordField(MCRS, ^PMEM._MIN, PMIN) |
||||
CreateDwordField(MCRS, ^PMEM._MAX, PMAX) |
||||
CreateDwordField(MCRS, ^PMEM._LEN, PLEN) |
||||
|
||||
/* |
||||
* Hardcode TOLM to 2GB for now as BayTrail FSP uses this value. |
||||
* |
||||
* TODO: for generic usage, read TOLM value from register, or |
||||
* from global NVS (not implemented by U-Boot yet). |
||||
*/ |
||||
Store(0x80000000, PMIN) |
||||
Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX) |
||||
Add(Subtract(PMAX, PMIN), 1, PLEN) |
||||
|
||||
/* Update High PCI resource area */ |
||||
CreateQwordField(MCRS, ^UMEM._MIN, UMIN) |
||||
CreateQwordField(MCRS, ^UMEM._MAX, UMAX) |
||||
CreateQwordField(MCRS, ^UMEM._LEN, ULEN) |
||||
|
||||
/* Set base address to 48GB and allocate 16GB for PCI space */ |
||||
Store(0xc00000000, UMIN) |
||||
Store(0x400000000, ULEN) |
||||
Add(UMIN, Subtract(ULEN, 1), UMAX) |
||||
|
||||
Return (MCRS) |
||||
} |
||||
|
||||
/* Device Resource Consumption */ |
||||
Device (PDRC) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C02")) |
||||
Name(_UID, 1) |
||||
|
||||
Name(PDRS, ResourceTemplate() { |
||||
Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) |
||||
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) |
||||
Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) |
||||
Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) |
||||
Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) |
||||
Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) |
||||
Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) |
||||
Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) |
||||
}) |
||||
|
||||
/* Current Resource Settings */ |
||||
Method(_CRS, 0, Serialized) |
||||
{ |
||||
Return (PDRS) |
||||
} |
||||
} |
||||
|
||||
Method(_OSC, 4) |
||||
{ |
||||
/* Check for proper GUID */ |
||||
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { |
||||
/* Let OS control everything */ |
||||
Return (Arg3) |
||||
} Else { |
||||
/* Unrecognized UUID */ |
||||
CreateDWordField(Arg3, 0, CDW1) |
||||
Or(CDW1, 4, CDW1) |
||||
Return (Arg3) |
||||
} |
||||
} |
||||
|
||||
/* LPC Bridge 0:1f.0 */ |
||||
#include "lpc.asl" |
||||
|
||||
/* USB EHCI 0:1d.0 */ |
||||
#include "usb.asl" |
||||
|
||||
/* USB XHCI 0:14.0 */ |
||||
#include "xhci.asl" |
||||
|
||||
/* IRQ routing for each PCI device */ |
||||
#include "irqroute.asl" |
||||
} |
@ -0,0 +1,34 @@ |
||||
/* |
||||
* Copyright (C) 2007-2009 coresystems GmbH |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* EHCI Controller 0:1d.0 */ |
||||
|
||||
Device (EHC1) |
||||
{ |
||||
Name(_ADR, 0x001d0000) |
||||
|
||||
/* Power Resources for Wake */ |
||||
Name(_PRW, Package() { 13, 4 }) |
||||
|
||||
/* Highest D state in S3 state */ |
||||
Name(_S3D, 2) |
||||
|
||||
/* Highest D state in S4 state */ |
||||
Name(_S4D, 2) |
||||
|
||||
Device (HUB7) |
||||
{ |
||||
Name(_ADR, 0x00000000) |
||||
|
||||
Device(PRT1) { Name(_ADR, 1) } /* USB Port 0 */ |
||||
Device(PRT2) { Name(_ADR, 2) } /* USB Port 1 */ |
||||
Device(PRT3) { Name(_ADR, 3) } /* USB Port 2 */ |
||||
Device(PRT4) { Name(_ADR, 4) } /* USB Port 3 */ |
||||
} |
||||
} |
@ -0,0 +1,31 @@ |
||||
/* |
||||
* Copyright (C) 2014 Google Inc. |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* XHCI Controller 0:14.0 */ |
||||
|
||||
Device (XHCI) |
||||
{ |
||||
Name(_ADR, 0x00140000) |
||||
|
||||
/* Power Resources for Wake */ |
||||
Name(_PRW, Package() { 13, 3 }) |
||||
|
||||
/* Highest D state in S3 state */ |
||||
Name(_S3D, 3) |
||||
|
||||
Device (RHUB) |
||||
{ |
||||
Name(_ADR, 0x00000000) |
||||
|
||||
Device (PRT1) { Name(_ADR, 1) } /* USB Port 0 */ |
||||
Device (PRT2) { Name(_ADR, 2) } /* USB Port 1 */ |
||||
Device (PRT3) { Name(_ADR, 3) } /* USB Port 2 */ |
||||
Device (PRT4) { Name(_ADR, 4) } /* USB Port 3 */ |
||||
} |
||||
} |
@ -0,0 +1,74 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Google Inc. |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _DEVICE_H_ |
||||
#define _DEVICE_H_ |
||||
|
||||
/*
|
||||
* Internal PCI device numbers within the SoC. |
||||
* |
||||
* Note it must start with 0x_ prefix, as the device number macro will be |
||||
* included in the ACPI ASL files (see irq_helper.h and irq_route.h). |
||||
*/ |
||||
|
||||
/* SoC transaction router */ |
||||
#define SOC_DEV 0x00 |
||||
|
||||
/* Graphics and Display */ |
||||
#define GFX_DEV 0x02 |
||||
|
||||
/* MIPI */ |
||||
#define MIPI_DEV 0x03 |
||||
|
||||
/* EMMC Port */ |
||||
#define EMMC_DEV 0x10 |
||||
|
||||
/* SDIO Port */ |
||||
#define SDIO_DEV 0x11 |
||||
|
||||
/* SD Port */ |
||||
#define SD_DEV 0x12 |
||||
|
||||
/* SATA */ |
||||
#define SATA_DEV 0x13 |
||||
|
||||
/* xHCI */ |
||||
#define XHCI_DEV 0x14 |
||||
|
||||
/* LPE Audio */ |
||||
#define LPE_DEV 0x15 |
||||
|
||||
/* OTG */ |
||||
#define OTG_DEV 0x16 |
||||
|
||||
/* MMC45 Port */ |
||||
#define MMC45_DEV 0x17 |
||||
|
||||
/* Serial IO 1 */ |
||||
#define SIO1_DEV 0x18 |
||||
|
||||
/* Trusted Execution Engine */ |
||||
#define TXE_DEV 0x1a |
||||
|
||||
/* HD Audio */ |
||||
#define HDA_DEV 0x1b |
||||
|
||||
/* PCIe Ports */ |
||||
#define PCIE_DEV 0x1c |
||||
|
||||
/* EHCI */ |
||||
#define EHCI_DEV 0x1d |
||||
|
||||
/* Serial IO 2 */ |
||||
#define SIO2_DEV 0x1e |
||||
|
||||
/* Platform Controller Unit */ |
||||
#define PCU_DEV 0x1f |
||||
|
||||
#endif /* _DEVICE_H_ */ |
@ -0,0 +1,70 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Google Inc. |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _BAYTRAIL_IOMAP_H_ |
||||
#define _BAYTRAIL_IOMAP_H_ |
||||
|
||||
/* Memory Mapped IO bases */ |
||||
|
||||
/* PCI Configuration Space */ |
||||
#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE |
||||
#define MCFG_BASE_SIZE 0x10000000 |
||||
|
||||
/* Temporary Base Address */ |
||||
#define TEMP_BASE_ADDRESS 0xfd000000 |
||||
|
||||
/* Transactions in this range will abort */ |
||||
#define ABORT_BASE_ADDRESS 0xfeb00000 |
||||
#define ABORT_BASE_SIZE 0x00100000 |
||||
|
||||
/* High Performance Event Timer */ |
||||
#define HPET_BASE_ADDRESS 0xfed00000 |
||||
#define HPET_BASE_SIZE 0x400 |
||||
|
||||
/* SPI Bus */ |
||||
#define SPI_BASE_ADDRESS 0xfed01000 |
||||
#define SPI_BASE_SIZE 0x400 |
||||
|
||||
/* Power Management Controller */ |
||||
#define PMC_BASE_ADDRESS 0xfed03000 |
||||
#define PMC_BASE_SIZE 0x400 |
||||
|
||||
/* Power Management Unit */ |
||||
#define PUNIT_BASE_ADDRESS 0xfed05000 |
||||
#define PUNIT_BASE_SIZE 0x800 |
||||
|
||||
/* Intel Legacy Block */ |
||||
#define ILB_BASE_ADDRESS 0xfed08000 |
||||
#define ILB_BASE_SIZE 0x400 |
||||
|
||||
/* IO Memory */ |
||||
#define IO_BASE_ADDRESS 0xfed0c000 |
||||
#define IO_BASE_OFFSET_GPSCORE 0x0000 |
||||
#define IO_BASE_OFFSET_GPNCORE 0x1000 |
||||
#define IO_BASE_OFFSET_GPSSUS 0x2000 |
||||
#define IO_BASE_SIZE 0x4000 |
||||
|
||||
/* Root Complex Base Address */ |
||||
#define RCBA_BASE_ADDRESS 0xfed1c000 |
||||
#define RCBA_BASE_SIZE 0x400 |
||||
|
||||
/* MODPHY */ |
||||
#define MPHY_BASE_ADDRESS 0xfef00000 |
||||
#define MPHY_BASE_SIZE 0x100000 |
||||
|
||||
/* IO Port bases */ |
||||
#define ACPI_BASE_ADDRESS 0x0400 |
||||
#define ACPI_BASE_SIZE 0x80 |
||||
|
||||
#define GPIO_BASE_ADDRESS 0x0500 |
||||
#define GPIO_BASE_SIZE 0x100 |
||||
|
||||
#define SMBUS_BASE_ADDRESS 0xefa0 |
||||
|
||||
#endif /* _BAYTRAIL_IOMAP_H_ */ |
@ -0,0 +1,86 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Google Inc. |
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _BAYTRAIL_IRQ_H_ |
||||
#define _BAYTRAIL_IRQ_H_ |
||||
|
||||
#define PIRQA_APIC_IRQ 16 |
||||
#define PIRQB_APIC_IRQ 17 |
||||
#define PIRQC_APIC_IRQ 18 |
||||
#define PIRQD_APIC_IRQ 19 |
||||
#define PIRQE_APIC_IRQ 20 |
||||
#define PIRQF_APIC_IRQ 21 |
||||
#define PIRQG_APIC_IRQ 22 |
||||
#define PIRQH_APIC_IRQ 23 |
||||
|
||||
/* The below IRQs are for when devices are in ACPI mode */ |
||||
#define LPE_DMA0_IRQ 24 |
||||
#define LPE_DMA1_IRQ 25 |
||||
#define LPE_SSP0_IRQ 26 |
||||
#define LPE_SSP1_IRQ 27 |
||||
#define LPE_SSP2_IRQ 28 |
||||
#define LPE_IPC2HOST_IRQ 29 |
||||
#define LPSS_I2C1_IRQ 32 |
||||
#define LPSS_I2C2_IRQ 33 |
||||
#define LPSS_I2C3_IRQ 34 |
||||
#define LPSS_I2C4_IRQ 35 |
||||
#define LPSS_I2C5_IRQ 36 |
||||
#define LPSS_I2C6_IRQ 37 |
||||
#define LPSS_I2C7_IRQ 38 |
||||
#define LPSS_HSUART1_IRQ 39 |
||||
#define LPSS_HSUART2_IRQ 40 |
||||
#define LPSS_SPI_IRQ 41 |
||||
#define LPSS_DMA1_IRQ 42 |
||||
#define LPSS_DMA2_IRQ 43 |
||||
#define SCC_EMMC_IRQ 44 |
||||
#define SCC_SDIO_IRQ 46 |
||||
#define SCC_SD_IRQ 47 |
||||
#define GPIO_NC_IRQ 48 |
||||
#define GPIO_SC_IRQ 49 |
||||
#define GPIO_SUS_IRQ 50 |
||||
/* GPIO direct / dedicated IRQs */ |
||||
#define GPIO_S0_DED_IRQ_0 51 |
||||
#define GPIO_S0_DED_IRQ_1 52 |
||||
#define GPIO_S0_DED_IRQ_2 53 |
||||
#define GPIO_S0_DED_IRQ_3 54 |
||||
#define GPIO_S0_DED_IRQ_4 55 |
||||
#define GPIO_S0_DED_IRQ_5 56 |
||||
#define GPIO_S0_DED_IRQ_6 57 |
||||
#define GPIO_S0_DED_IRQ_7 58 |
||||
#define GPIO_S0_DED_IRQ_8 59 |
||||
#define GPIO_S0_DED_IRQ_9 60 |
||||
#define GPIO_S0_DED_IRQ_10 61 |
||||
#define GPIO_S0_DED_IRQ_11 62 |
||||
#define GPIO_S0_DED_IRQ_12 63 |
||||
#define GPIO_S0_DED_IRQ_13 64 |
||||
#define GPIO_S0_DED_IRQ_14 65 |
||||
#define GPIO_S0_DED_IRQ_15 66 |
||||
#define GPIO_S5_DED_IRQ_0 67 |
||||
#define GPIO_S5_DED_IRQ_1 68 |
||||
#define GPIO_S5_DED_IRQ_2 69 |
||||
#define GPIO_S5_DED_IRQ_3 70 |
||||
#define GPIO_S5_DED_IRQ_4 71 |
||||
#define GPIO_S5_DED_IRQ_5 72 |
||||
#define GPIO_S5_DED_IRQ_6 73 |
||||
#define GPIO_S5_DED_IRQ_7 74 |
||||
#define GPIO_S5_DED_IRQ_8 75 |
||||
#define GPIO_S5_DED_IRQ_9 76 |
||||
#define GPIO_S5_DED_IRQ_10 77 |
||||
#define GPIO_S5_DED_IRQ_11 78 |
||||
#define GPIO_S5_DED_IRQ_12 79 |
||||
#define GPIO_S5_DED_IRQ_13 80 |
||||
#define GPIO_S5_DED_IRQ_14 81 |
||||
#define GPIO_S5_DED_IRQ_15 82 |
||||
/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */ |
||||
#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot |
||||
#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot |
||||
#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) |
||||
#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) |
||||
|
||||
#endif /* _BAYTRAIL_IRQ_H_ */ |
@ -0,0 +1,3 @@ |
||||
dsdt.aml |
||||
dsdt.asl.tmp |
||||
dsdt.c |
@ -0,0 +1,13 @@ |
||||
/* |
||||
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* Power Button */ |
||||
Device (PWRB) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0C")) |
||||
} |
||||
|
||||
/* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */ |
@ -0,0 +1,14 @@ |
||||
/* |
||||
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) |
||||
{ |
||||
/* platform specific */ |
||||
#include <asm/arch/acpi/platform.asl> |
||||
|
||||
/* board specific */ |
||||
#include "acpi/mainboard.asl" |
||||
} |
@ -0,0 +1,3 @@ |
||||
dsdt.aml |
||||
dsdt.asl.tmp |
||||
dsdt.c |
@ -0,0 +1,11 @@ |
||||
/* |
||||
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* Power Button */ |
||||
Device (PWRB) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0C")) |
||||
} |
@ -0,0 +1,14 @@ |
||||
/* |
||||
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) |
||||
{ |
||||
/* platform specific */ |
||||
#include <asm/arch/acpi/platform.asl> |
||||
|
||||
/* board specific */ |
||||
#include "acpi/mainboard.asl" |
||||
} |
@ -0,0 +1,3 @@ |
||||
dsdt.aml |
||||
dsdt.asl.tmp |
||||
dsdt.c |
@ -0,0 +1,11 @@ |
||||
/* |
||||
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* Power Button */ |
||||
Device (PWRB) |
||||
{ |
||||
Name(_HID, EISAID("PNP0C0C")) |
||||
} |
@ -0,0 +1,14 @@ |
||||
/* |
||||
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) |
||||
{ |
||||
/* platform specific */ |
||||
#include <asm/arch/acpi/platform.asl> |
||||
|
||||
/* board specific */ |
||||
#include "acpi/mainboard.asl" |
||||
} |
@ -0,0 +1,194 @@ |
||||
/*
|
||||
* (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <errno.h> |
||||
#include <qfw.h> |
||||
|
||||
/*
|
||||
* This function prepares kernel for zboot. It loads kernel data |
||||
* to 'load_addr', initrd to 'initrd_addr' and kernel command |
||||
* line using qemu fw_cfg interface. |
||||
*/ |
||||
static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr) |
||||
{ |
||||
char *data_addr; |
||||
uint32_t setup_size, kernel_size, cmdline_size, initrd_size; |
||||
|
||||
qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size); |
||||
qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size); |
||||
|
||||
if (setup_size == 0 || kernel_size == 0) { |
||||
printf("warning: no kernel available\n"); |
||||
return -1; |
||||
} |
||||
|
||||
data_addr = load_addr; |
||||
qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA, |
||||
le32_to_cpu(setup_size), data_addr); |
||||
data_addr += le32_to_cpu(setup_size); |
||||
|
||||
qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA, |
||||
le32_to_cpu(kernel_size), data_addr); |
||||
data_addr += le32_to_cpu(kernel_size); |
||||
|
||||
data_addr = initrd_addr; |
||||
qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size); |
||||
if (initrd_size == 0) { |
||||
printf("warning: no initrd available\n"); |
||||
} else { |
||||
qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA, |
||||
le32_to_cpu(initrd_size), data_addr); |
||||
data_addr += le32_to_cpu(initrd_size); |
||||
} |
||||
|
||||
qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size); |
||||
if (cmdline_size) { |
||||
qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA, |
||||
le32_to_cpu(cmdline_size), data_addr); |
||||
/*
|
||||
* if kernel cmdline only contains '\0', (e.g. no -append |
||||
* when invoking qemu), do not update bootargs |
||||
*/ |
||||
if (*data_addr != '\0') { |
||||
if (setenv("bootargs", data_addr) < 0) |
||||
printf("warning: unable to change bootargs\n"); |
||||
} |
||||
} |
||||
|
||||
printf("loading kernel to address %p size %x", load_addr, |
||||
le32_to_cpu(kernel_size)); |
||||
if (initrd_size) |
||||
printf(" initrd %p size %x\n", |
||||
initrd_addr, |
||||
le32_to_cpu(initrd_size)); |
||||
else |
||||
printf("\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int qemu_fwcfg_list_firmware(void) |
||||
{ |
||||
int ret; |
||||
struct fw_cfg_file_iter iter; |
||||
struct fw_file *file; |
||||
|
||||
/* make sure fw_list is loaded */ |
||||
ret = qemu_fwcfg_read_firmware_list(); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
|
||||
for (file = qemu_fwcfg_file_iter_init(&iter); |
||||
!qemu_fwcfg_file_iter_end(&iter); |
||||
file = qemu_fwcfg_file_iter_next(&iter)) { |
||||
printf("%-56s\n", file->cfg.name); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag, |
||||
int argc, char * const argv[]) |
||||
{ |
||||
if (qemu_fwcfg_list_firmware() < 0) |
||||
return CMD_RET_FAILURE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag, |
||||
int argc, char * const argv[]) |
||||
{ |
||||
int ret = qemu_fwcfg_online_cpus(); |
||||
if (ret < 0) { |
||||
printf("QEMU fw_cfg interface not found\n"); |
||||
return CMD_RET_FAILURE; |
||||
} |
||||
|
||||
printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus()); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag, |
||||
int argc, char * const argv[]) |
||||
{ |
||||
char *env; |
||||
void *load_addr; |
||||
void *initrd_addr; |
||||
|
||||
env = getenv("loadaddr"); |
||||
load_addr = env ? |
||||
(void *)simple_strtoul(env, NULL, 16) : |
||||
#ifdef CONFIG_LOADADDR |
||||
(void *)CONFIG_LOADADDR; |
||||
#else |
||||
NULL; |
||||
#endif |
||||
|
||||
env = getenv("ramdiskaddr"); |
||||
initrd_addr = env ? |
||||
(void *)simple_strtoul(env, NULL, 16) : |
||||
#ifdef CONFIG_RAMDISK_ADDR |
||||
(void *)CONFIG_RAMDISK_ADDR; |
||||
#else |
||||
NULL; |
||||
#endif |
||||
|
||||
if (argc == 2) { |
||||
load_addr = (void *)simple_strtoul(argv[0], NULL, 16); |
||||
initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16); |
||||
} else if (argc == 1) { |
||||
load_addr = (void *)simple_strtoul(argv[0], NULL, 16); |
||||
} |
||||
|
||||
if (!load_addr || !initrd_addr) { |
||||
printf("missing load or initrd address\n"); |
||||
return CMD_RET_FAILURE; |
||||
} |
||||
|
||||
return qemu_fwcfg_setup_kernel(load_addr, initrd_addr); |
||||
} |
||||
|
||||
static cmd_tbl_t fwcfg_commands[] = { |
||||
U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""), |
||||
U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""), |
||||
U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""), |
||||
}; |
||||
|
||||
static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
int ret; |
||||
cmd_tbl_t *fwcfg_cmd; |
||||
|
||||
if (!qemu_fwcfg_present()) { |
||||
printf("QEMU fw_cfg interface not found\n"); |
||||
return CMD_RET_USAGE; |
||||
} |
||||
|
||||
fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands, |
||||
ARRAY_SIZE(fwcfg_commands)); |
||||
argc -= 2; |
||||
argv += 2; |
||||
if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs) |
||||
return CMD_RET_USAGE; |
||||
|
||||
ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv); |
||||
|
||||
return cmd_process_error(fwcfg_cmd, ret); |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
qfw, 4, 1, do_qemu_fw, |
||||
"QEMU firmware interface", |
||||
"<command>\n" |
||||
" - list : print firmware(s) currently loaded\n" |
||||
" - cpus : print online cpu number\n" |
||||
" - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n" |
||||
) |
Loading…
Reference in new issue