Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>master
Shengzhou Liu
13 years ago
committed by
Kumar Gala
parent
6b3a8d0086
commit
6d7b061af1
@ -0,0 +1,113 @@ |
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_portals.h> |
||||
#include <asm/fsl_liodn.h> |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_QBMAN |
||||
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { |
||||
/* dqrr liodn, frame data liodn, liodn off, sdest */ |
||||
SET_QP_INFO( 1, 2, 1, 0), |
||||
SET_QP_INFO( 3, 4, 2, 1), |
||||
SET_QP_INFO( 5, 6, 3, 2), |
||||
SET_QP_INFO( 7, 8, 4, 3), |
||||
SET_QP_INFO( 9, 10, 5, 4), |
||||
SET_QP_INFO(11, 12, 6, 5), |
||||
SET_QP_INFO(13, 14, 7, 6), |
||||
SET_QP_INFO(15, 16, 8, 7), |
||||
SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */ |
||||
SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */ |
||||
}; |
||||
#endif |
||||
|
||||
struct liodn_id_table liodn_tbl[] = { |
||||
SET_USB_LIODN(1, "fsl-usb2-mph", 127), |
||||
SET_USB_LIODN(2, "fsl-usb2-dr", 157), |
||||
|
||||
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), |
||||
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), |
||||
|
||||
SET_DMA_LIODN(1, 196), |
||||
SET_DMA_LIODN(2, 197), |
||||
|
||||
SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0), |
||||
SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0), |
||||
SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0), |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_QBMAN |
||||
SET_QMAN_LIODN(31), |
||||
SET_BMAN_LIODN(32), |
||||
#endif |
||||
SET_PME_LIODN(128), |
||||
}; |
||||
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
struct liodn_id_table fman1_liodn_tbl[] = { |
||||
SET_FMAN_RX_1G_LIODN(1, 0, 11), |
||||
SET_FMAN_RX_1G_LIODN(1, 1, 12), |
||||
SET_FMAN_RX_1G_LIODN(1, 2, 13), |
||||
SET_FMAN_RX_1G_LIODN(1, 3, 14), |
||||
}; |
||||
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); |
||||
|
||||
#if (CONFIG_SYS_NUM_FMAN == 2) |
||||
struct liodn_id_table fman2_liodn_tbl[] = { |
||||
SET_FMAN_RX_1G_LIODN(2, 0, 16), |
||||
SET_FMAN_RX_1G_LIODN(2, 1, 17), |
||||
SET_FMAN_RX_1G_LIODN(2, 2, 18), |
||||
SET_FMAN_RX_1G_LIODN(2, 3, 19), |
||||
}; |
||||
int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); |
||||
#endif |
||||
#endif |
||||
|
||||
struct liodn_id_table sec_liodn_tbl[] = { |
||||
SET_SEC_JR_LIODN_ENTRY(0, 146, 154), |
||||
SET_SEC_JR_LIODN_ENTRY(1, 147, 155), |
||||
SET_SEC_JR_LIODN_ENTRY(2, 178, 186), |
||||
SET_SEC_JR_LIODN_ENTRY(3, 179, 187), |
||||
SET_SEC_RTIC_LIODN_ENTRY(a, 144), |
||||
SET_SEC_RTIC_LIODN_ENTRY(b, 145), |
||||
SET_SEC_RTIC_LIODN_ENTRY(c, 176), |
||||
SET_SEC_RTIC_LIODN_ENTRY(d, 177), |
||||
SET_SEC_DECO_LIODN_ENTRY(0, 129, 161), |
||||
SET_SEC_DECO_LIODN_ENTRY(1, 130, 162), |
||||
SET_SEC_DECO_LIODN_ENTRY(2, 131, 163), |
||||
SET_SEC_DECO_LIODN_ENTRY(3, 132, 164), |
||||
SET_SEC_DECO_LIODN_ENTRY(4, 133, 165), |
||||
}; |
||||
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); |
||||
|
||||
struct liodn_id_table liodn_bases[] = { |
||||
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106), |
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), |
||||
#if (CONFIG_SYS_NUM_FMAN == 2) |
||||
[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64), |
||||
#endif |
||||
#endif |
||||
#ifdef CONFIG_SYS_DPAA_PME |
||||
[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133), |
||||
#endif |
||||
}; |
||||
@ -0,0 +1,138 @@ |
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/io.h> |
||||
#include "fsl_corenet_serdes.h" |
||||
|
||||
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { |
||||
[0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, |
||||
SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC1, |
||||
SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, |
||||
NONE, NONE, AURORA, AURORA}, |
||||
[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SGMII_FM2_DTSEC3, |
||||
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, |
||||
SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, |
||||
SGMII_FM1_DTSEC2, NONE, NONE, AURORA, AURORA}, |
||||
[0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, |
||||
AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, |
||||
SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3, |
||||
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4}, |
||||
[0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, |
||||
AURORA, AURORA, PCIE2, PCIE2, PCIE2, PCIE2, SGMII_FM2_DTSEC3, |
||||
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4}, |
||||
[0x1c] = {NONE, NONE, SRIO1, SRIO2, NONE, NONE, NONE, NONE, |
||||
AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, |
||||
SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3, |
||||
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4}, |
||||
}; |
||||
|
||||
enum srds_prtcl serdes_get_prtcl(int cfg, int lane) |
||||
{ |
||||
if (!serdes_lane_enabled(lane)) |
||||
return NONE; |
||||
|
||||
return serdes_cfg_tbl[cfg][lane]; |
||||
} |
||||
|
||||
int is_serdes_prtcl_valid(u32 prtcl) |
||||
{ |
||||
int i; |
||||
|
||||
if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) |
||||
return 0; |
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) { |
||||
if (serdes_cfg_tbl[prtcl][i] != NONE) |
||||
return 1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void soc_serdes_init(void) |
||||
{ |
||||
/*
|
||||
* On the P3060 the devdisr2 register does not correctly reflect |
||||
* the state of the MACs based on the RCW fields. So disable the MACs |
||||
* based on the srds_prtcl and ec1, ec2, ec3 fields |
||||
*/ |
||||
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 devdisr2 = in_be32(&gur->devdisr2); |
||||
u32 rcwsr11 = in_be32(&gur->rcwsr[11]); |
||||
u32 rcwsr13 = in_be32(&gur->rcwsr[13]); |
||||
u32 ec1_ext, ec2_ext; |
||||
|
||||
/* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */ |
||||
|
||||
if (!is_serdes_configured(SGMII_FM1_DTSEC3)) |
||||
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_3; |
||||
|
||||
if (!is_serdes_configured(SGMII_FM1_DTSEC4)) |
||||
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_4; |
||||
|
||||
if (!is_serdes_configured(SGMII_FM2_DTSEC1)) |
||||
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_1; |
||||
|
||||
if (!is_serdes_configured(SGMII_FM2_DTSEC2)) |
||||
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_2; |
||||
|
||||
if (!is_serdes_configured(SGMII_FM2_DTSEC3)) |
||||
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_3; |
||||
|
||||
if (!is_serdes_configured(SGMII_FM2_DTSEC4)) |
||||
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_4; |
||||
|
||||
if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == |
||||
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) { |
||||
devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_2; |
||||
} |
||||
|
||||
if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == |
||||
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1) { |
||||
devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1; |
||||
} |
||||
|
||||
ec1_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT; |
||||
if (ec1_ext) { |
||||
if ((ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII) || |
||||
(ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII)) |
||||
devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_4; |
||||
} |
||||
|
||||
ec2_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT; |
||||
if (ec2_ext) { |
||||
if ((ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII) || |
||||
(ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII)) |
||||
devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4; |
||||
} |
||||
|
||||
if ((rcwsr13 & FSL_CORENET_RCWSR13_EC3) == |
||||
FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII) |
||||
devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4; |
||||
|
||||
out_be32(&gur->devdisr2, devdisr2); |
||||
} |
||||
@ -0,0 +1,109 @@ |
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#include <common.h> |
||||
#include <phy.h> |
||||
#include <fm_eth.h> |
||||
#include <asm/io.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_serdes.h> |
||||
|
||||
u32 port_to_devdisr[] = { |
||||
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, |
||||
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, |
||||
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, |
||||
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, |
||||
[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, |
||||
[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, |
||||
[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, |
||||
[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, |
||||
}; |
||||
|
||||
static int is_device_disabled(enum fm_port port) |
||||
{ |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 devdisr2 = in_be32(&gur->devdisr2); |
||||
|
||||
return port_to_devdisr[port] & devdisr2; |
||||
} |
||||
|
||||
void fman_disable_port(enum fm_port port) |
||||
{ |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
setbits_be32(&gur->devdisr2, port_to_devdisr[port]); |
||||
} |
||||
|
||||
phy_interface_t fman_port_enet_if(enum fm_port port) |
||||
{ |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 rcwsr11 = in_be32(&gur->rcwsr[11]); |
||||
u32 rcwsr13 = in_be32(&gur->rcwsr[13]); |
||||
|
||||
if (is_device_disabled(port)) |
||||
return PHY_INTERFACE_MODE_NONE; |
||||
|
||||
/* handle RGMII/MII first */ |
||||
if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == |
||||
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1)) |
||||
return PHY_INTERFACE_MODE_RGMII; |
||||
|
||||
if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == |
||||
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2)) |
||||
return PHY_INTERFACE_MODE_RGMII; |
||||
|
||||
if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == |
||||
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1)) |
||||
return PHY_INTERFACE_MODE_RGMII; |
||||
|
||||
if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) == |
||||
FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII)) |
||||
return PHY_INTERFACE_MODE_RGMII; |
||||
|
||||
if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) == |
||||
FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII)) |
||||
return PHY_INTERFACE_MODE_MII; |
||||
|
||||
if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) == |
||||
FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII)) |
||||
return PHY_INTERFACE_MODE_RGMII; |
||||
|
||||
if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) == |
||||
FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII)) |
||||
return PHY_INTERFACE_MODE_MII; |
||||
|
||||
switch (port) { |
||||
case FM1_DTSEC1: |
||||
case FM1_DTSEC2: |
||||
case FM1_DTSEC3: |
||||
case FM1_DTSEC4: |
||||
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) |
||||
return PHY_INTERFACE_MODE_SGMII; |
||||
break; |
||||
case FM2_DTSEC1: |
||||
case FM2_DTSEC2: |
||||
case FM2_DTSEC3: |
||||
case FM2_DTSEC4: |
||||
if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) |
||||
return PHY_INTERFACE_MODE_SGMII; |
||||
break; |
||||
default: |
||||
return PHY_INTERFACE_MODE_NONE; |
||||
} |
||||
|
||||
return PHY_INTERFACE_MODE_NONE; |
||||
} |
||||
Loading…
Reference in new issue