LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>master
Ashish Kumar
7 years ago
committed by
York Sun
parent
22c51855bf
commit
6d9b82d085
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/*
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* Copyright 2017 NXP |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/fsl_serdes.h> |
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struct serdes_config { |
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u8 ip_protocol; |
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u8 lanes[SRDS_MAX_LANES]; |
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u8 rcw_lanes[SRDS_MAX_LANES]; |
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}; |
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static struct serdes_config serdes1_cfg_tbl[] = { |
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/* SerDes 1 */ |
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{0x12, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 3 } }, |
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{0x15, {SGMII3, SGMII7, XFI1, XFI2 }, {3, 3, 1, 1 } }, |
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{0x16, {SGMII3, SGMII7, SGMII1, XFI2 }, {3, 3, 3, 1 } }, |
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{0x17, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 2 } }, |
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{0x18, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 2, 2 } }, |
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{0x19, {SGMII3, QSGMII_B, XFI1, XFI2}, {3, 4, 1, 1 } }, |
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{0x1A, {SGMII3, QSGMII_B, SGMII1, XFI2 }, {3, 4, 3, 1 } }, |
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{0x1B, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 2 } }, |
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{0x1C, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 2, 2 } }, |
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{0x1D, {QSGMII_A, QSGMII_B, XFI1, XFI2 }, {4, 4, 1, 1 } }, |
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{0x1E, {QSGMII_A, QSGMII_B, SGMII1, XFI2 }, {4, 4, 3, 1 } }, |
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{0x1F, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 2 } }, |
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{0x20, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 2, 2 } }, |
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{0x35, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 3 } }, |
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{0x36, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 3 } }, |
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{0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } }, |
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{} |
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}; |
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static struct serdes_config serdes2_cfg_tbl[] = { |
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/* SerDes 2 */ |
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{0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } }, |
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{0x0D, {PCIE1, PCIE2, PCIE3, SATA1 }, {5, 5, 5, 9 } }, |
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{0x0E, {PCIE1, PCIE1, PCIE2, SATA1 }, {7, 7, 6, 9 } }, |
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{0x13, {PCIE1, PCIE1, PCIE3, PCIE3 }, {7, 7, 7, 7 } }, |
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{0x14, {PCIE1, PCIE2, PCIE3, PCIE3 }, {5, 5, 7, 7 } }, |
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{0x3C, {NONE, PCIE2, NONE, PCIE3 }, {0, 5, 0, 6 } }, |
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{} |
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}; |
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static struct serdes_config *serdes_cfg_tbl[] = { |
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serdes1_cfg_tbl, |
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serdes2_cfg_tbl, |
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}; |
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int serdes_get_number(int serdes, int cfg) |
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{ |
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struct serdes_config *ptr; |
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int i, j, index, lnk; |
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int is_found, max_lane = SRDS_MAX_LANES; |
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) |
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return 0; |
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ptr = serdes_cfg_tbl[serdes]; |
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while (ptr->ip_protocol) { |
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is_found = 1; |
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for (i = 0, j = max_lane - 1; i < max_lane; i++, j--) { |
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lnk = cfg & (0xf << 4 * i); |
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lnk = lnk >> (4 * i); |
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index = (serdes == FSL_SRDS_1) ? j : i; |
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if (ptr->rcw_lanes[index] == lnk && is_found) |
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is_found = 1; |
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else |
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is_found = 0; |
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} |
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if (is_found) |
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return ptr->ip_protocol; |
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ptr++; |
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} |
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return 0; |
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} |
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) |
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{ |
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struct serdes_config *ptr; |
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) |
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return 0; |
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ptr = serdes_cfg_tbl[serdes]; |
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while (ptr->ip_protocol) { |
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if (ptr->ip_protocol == cfg) |
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return ptr->lanes[lane]; |
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ptr++; |
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} |
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return 0; |
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} |
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int is_serdes_prtcl_valid(int serdes, u32 prtcl) |
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{ |
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int i; |
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struct serdes_config *ptr; |
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) |
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return 0; |
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ptr = serdes_cfg_tbl[serdes]; |
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while (ptr->ip_protocol) { |
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if (ptr->ip_protocol == prtcl) |
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break; |
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ptr++; |
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} |
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if (!ptr->ip_protocol) |
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return 0; |
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for (i = 0; i < SRDS_MAX_LANES; i++) { |
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if (ptr->lanes[i] != NONE) |
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return 1; |
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} |
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return 0; |
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} |
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@ -0,0 +1,78 @@ |
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/* |
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* NXP ls1088a SOC common device tree source |
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* |
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* Copyright 2017 NXP |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/ { |
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compatible = "fsl,ls1088a"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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memory@80000000 { |
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device_type = "memory"; |
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reg = <0x00000000 0x80000000 0 0x80000000>; |
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/* DRAM space - 1, size : 2 GB DRAM */ |
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}; |
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gic: interrupt-controller@6000000 { |
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compatible = "arm,gic-v3"; |
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ |
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<0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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interrupts = <1 9 0x4>; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ |
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<1 14 0x8>, /* Physical Non-Secure PPI, active-low */ |
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<1 11 0x8>, /* Virtual PPI, active-low */ |
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<1 10 0x8>; /* Hypervisor PPI, active-low */ |
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}; |
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serial0: serial@21c0500 { |
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device_type = "serial"; |
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compatible = "fsl,ns16550", "ns16550a"; |
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reg = <0x0 0x21c0500 0x0 0x100>; |
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clock-frequency = <0>; /* Updated by bootloader */ |
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interrupts = <0 32 0x1>; /* edge triggered */ |
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}; |
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serial1: serial@21c0600 { |
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device_type = "serial"; |
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compatible = "fsl,ns16550", "ns16550a"; |
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reg = <0x0 0x21c0600 0x0 0x100>; |
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clock-frequency = <0>; /* Updated by bootloader */ |
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interrupts = <0 32 0x1>; /* edge triggered */ |
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}; |
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fsl_mc: fsl-mc@80c000000 { |
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compatible = "fsl,qoriq-mc"; |
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ |
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<0x00000000 0x08340000 0 0x40000>; /* MC control reg */ |
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}; |
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dspi: dspi@2100000 { |
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compatible = "fsl,vf610-dspi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2100000 0x0 0x10000>; |
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interrupts = <0 26 0x4>; /* Level high type */ |
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num-cs = <6>; |
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}; |
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qspi: quadspi@1550000 { |
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compatible = "fsl,vf610-qspi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x20c0000 0x0 0x10000>, |
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<0x0 0x20000000 0x0 0x10000000>; |
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reg-names = "QuadSPI", "QuadSPI-memory"; |
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num-cs = <4>; |
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}; |
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}; |
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@ -0,0 +1,87 @@ |
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/*
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* Copyright 2017 NXP |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <phy.h> |
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#include <fsl-mc/ldpaa_wriop.h> |
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#include <asm/io.h> |
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#include <asm/arch/fsl_serdes.h> |
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u32 dpmac_to_devdisr[] = { |
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[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, |
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[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2, |
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[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3, |
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[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4, |
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[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5, |
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[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6, |
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[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7, |
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[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8, |
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[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9, |
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[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10, |
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}; |
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static int is_device_disabled(int dpmac_id) |
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{ |
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
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u32 devdisr2 = in_le32(&gur->devdisr2); |
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return dpmac_to_devdisr[dpmac_id] & devdisr2; |
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} |
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void wriop_dpmac_disable(int dpmac_id) |
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{ |
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
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setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); |
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} |
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void wriop_dpmac_enable(int dpmac_id) |
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{ |
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
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clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); |
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} |
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phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) |
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{ |
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enum srds_prtcl; |
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if (is_device_disabled(dpmac_id + 1)) |
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return PHY_INTERFACE_MODE_NONE; |
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switch (lane_prtcl) { |
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case SGMII1: |
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case SGMII2: |
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case SGMII3: |
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case SGMII7: |
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return PHY_INTERFACE_MODE_SGMII; |
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} |
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if (lane_prtcl >= XFI1 && lane_prtcl <= XFI2) |
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return PHY_INTERFACE_MODE_XGMII; |
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if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B) |
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return PHY_INTERFACE_MODE_QSGMII; |
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return PHY_INTERFACE_MODE_NONE; |
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} |
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void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) |
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{ |
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switch (lane_prtcl) { |
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case QSGMII_A: |
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wriop_init_dpmac(sd, 3, (int)lane_prtcl); |
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wriop_init_dpmac(sd, 4, (int)lane_prtcl); |
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wriop_init_dpmac(sd, 5, (int)lane_prtcl); |
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wriop_init_dpmac(sd, 6, (int)lane_prtcl); |
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break; |
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case QSGMII_B: |
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wriop_init_dpmac(sd, 7, (int)lane_prtcl); |
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wriop_init_dpmac(sd, 8, (int)lane_prtcl); |
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wriop_init_dpmac(sd, 9, (int)lane_prtcl); |
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wriop_init_dpmac(sd, 10, (int)lane_prtcl); |
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break; |
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} |
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} |
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