Commit 1b0757e deleted the EP88x entry from boards.cfg file.
But it missed to remove include/configs/EP88x.h and board/ep88x/.
This commit removes them and adds EP88x to README.scrapyard.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
master
Masahiro Yamada
11 years ago
committed by
Tom Rini
parent
4168ba7661
commit
6dca9450a2
@ -1,31 +0,0 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2004 Arabella Software Ltd.
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# Yuli Barcohen <yuli@arabellasw.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -1,117 +0,0 @@ |
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/*
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* Copyright (C) 2005 Arabella Software Ltd. |
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* Yuli Barcohen <yuli@arabellasw.com> |
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* |
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* Support for Embedded Planet EP88x boards. |
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* Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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/*
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* SDRAM uses two Micron chips. |
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* Minimal CPU frequency is 40MHz. |
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*/ |
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static uint sdram_table[] = { |
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/* Single read (offset 0x00 in UPM RAM) */ |
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0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404, |
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0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
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/* Burst read (offset 0x08 in UPM RAM) */ |
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0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404, |
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0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00, |
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
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/* Single write (offset 0x18 in UPM RAM) */ |
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0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404, |
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0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
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/* Burst write (offset 0x20 in UPM RAM) */ |
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0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400, |
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0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05, |
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
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/* Refresh (offset 0x30 in UPM RAM) */ |
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0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04, |
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0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34, |
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0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4, |
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/* Exception (offset 0x3C in UPM RAM) */ |
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0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05 |
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}; |
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int board_early_init_f (void) |
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{ |
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vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; |
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bcsr[0] |= 0x0C; /* Turn the LEDs off */ |
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bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
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flash detection by CFI driver |
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*/ |
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#if defined(CONFIG_8xx_CONS_SMC1) |
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bcsr[6] |= 0x10; /* Enables RS-232 transceiver */ |
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#endif |
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#if defined(CONFIG_8xx_CONS_SCC2) |
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bcsr[7] |= 0x10; /* Enables RS-232 transceiver */ |
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#endif |
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#ifdef CONFIG_ETHER_ON_FEC1 |
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bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */ |
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#endif |
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#ifdef CONFIG_ETHER_ON_FEC2 |
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bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */ |
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#endif |
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return 0; |
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} |
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phys_size_t initdram (int board_type) |
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{ |
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long int msize; |
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volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); |
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/* Configure SDRAM refresh */ |
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memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */ |
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memctl->memc_mamr = (65 << 24) | CONFIG_SYS_MAMR; /* No refresh */ |
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udelay(100); |
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/* Run MRS pattern from location 0x36 */ |
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memctl->memc_mar = 0x88; |
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memctl->memc_mcr = 0x80002236; |
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udelay(100); |
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memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ |
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memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; |
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memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; |
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msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE); |
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memctl->memc_or1 |= ~(msize - 1); |
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return msize; |
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} |
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int checkboard( void ) |
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{ |
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vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; |
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puts("Board: "); |
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switch (bcsr[15]) { |
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case 0xE7: |
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puts("EP88xC 1.0"); |
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break; |
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default: |
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printf("unknown ID=%02X", bcsr[15]); |
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} |
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printf(" CPLD revision %d\n", bcsr[14]); |
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return 0; |
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} |
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@ -1,79 +0,0 @@ |
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/* |
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* (C) Copyright 2001-2010 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Modified by Yuli Barcohen <yuli@arabellasw.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.text : |
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{ |
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arch/powerpc/cpu/mpc8xx/start.o (.text*) |
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arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
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*(.text*) |
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. = ALIGN(16); |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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} |
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x0FFF) & 0xFFFFF000; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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_GOT2_TABLE_ = .; |
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KEEP(*(.got2)) |
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KEEP(*(.got)) |
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PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
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_FIXUP_TABLE_ = .; |
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KEEP(*(.fixup)) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
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__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
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.data : |
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{ |
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*(.data*) |
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*(.sdata*) |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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. = .; |
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. = ALIGN(4); |
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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. = ALIGN(4096); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(4096); |
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__init_end = .; |
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__bss_start = .; |
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.bss (NOLOAD) : |
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{ |
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*(.bss*) |
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*(.sbss*) |
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*(COMMON) |
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. = ALIGN(4); |
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} |
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__bss_end = . ; |
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PROVIDE (end = .); |
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} |
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ENTRY(_start) |
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@ -1,187 +0,0 @@ |
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/*
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* Copyright (C) 2005 Arabella Software Ltd. |
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* Yuli Barcohen <yuli@arabellasw.com> |
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* |
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* Support for Embedded Planet EP88x boards. |
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* Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#define CONFIG_MPC885 |
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#define CONFIG_EP88X /* Embedded Planet EP88x board */ |
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#define CONFIG_SYS_TEXT_BASE 0xFC000000 |
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#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ |
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/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ |
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#define CONFIG_ENV_OVERWRITE |
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
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#define CONFIG_BAUDRATE 38400 |
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#define CONFIG_ETHER_ON_FEC1 /* Enable Ethernet on FEC1 */ |
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#define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */ |
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#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) |
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#define CONFIG_SYS_DISCOVER_PHY |
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#define CONFIG_MII_INIT 1 |
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#define FEC_ENET |
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#endif /* CONFIG_FEC_ENET */ |
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#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ |
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#define CONFIG_8xx_CPUCLK_DEFAULT 100000000 |
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#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 |
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#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_IMMAP |
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#define CONFIG_CMD_MII |
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#define CONFIG_CMD_PING |
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#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ |
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#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */ |
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#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)" |
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#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ |
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#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ |
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_SYS_HUSH_PARSER |
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#define CONFIG_SYS_LONGHELP /* #undef to save memory */ |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ |
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#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */ |
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/*-----------------------------------------------------------------------
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* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) |
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*/ |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
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#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* Up to 128 Mbyte */ |
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#define CONFIG_SYS_MAMR 0x00805000 |
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/*
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* 4096 Up to 4096 SDRAM rows |
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* 1000 factor s -> ms |
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* 32 PTP (pre-divider from MPTPR) |
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* 4 Number of refresh cycles per period |
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* 64 Refresh cycle in ms per number of rows |
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*/ |
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#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ |
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#define CONFIG_SYS_RESET_ADDRESS 0x09900000 |
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/*-----------------------------------------------------------------------
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ |
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#ifdef CONFIG_BZIP2 |
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#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ |
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#else |
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ |
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#endif /* CONFIG_BZIP2 */ |
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/*-----------------------------------------------------------------------
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* Flash organisation |
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*/ |
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#define CONFIG_SYS_FLASH_BASE 0xFC000000 |
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* Max num of sects on one chip */ |
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/* Environment is in flash */ |
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#define CONFIG_ENV_IS_IN_FLASH |
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
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#define CONFIG_SYS_OR0_PRELIM 0xFC000160 |
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V) |
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#define CONFIG_SYS_DIRECT_FLASH_TFTP |
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/*-----------------------------------------------------------------------
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* BCSR |
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*/ |
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#define CONFIG_SYS_OR3_PRELIM 0xFF0005B0 |
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#define CONFIG_SYS_BR3_PRELIM (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V) |
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#define CONFIG_SYS_BCSR 0xFA400000 |
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/*-----------------------------------------------------------------------
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* Internal Memory Map Register |
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*/ |
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#define CONFIG_SYS_IMMR 0xF0000000 |
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM) |
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*/ |
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
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/*-----------------------------------------------------------------------
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* Configuration registers |
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*/ |
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#ifdef CONFIG_WATCHDOG |
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ |
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SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
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SYPCR_SWP) |
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#else |
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ |
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SYPCR_SWF | SYPCR_SWP) |
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#endif /* CONFIG_WATCHDOG */ |
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#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) |
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/* TBSCR - Time Base Status and Control Register */ |
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#define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE) |
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/* PISCR - Periodic Interrupt Status and Control */ |
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#define CONFIG_SYS_PISCR PISCR_PS |
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/* SCCR - System Clock and reset Control Register */ |
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#define SCCR_MASK SCCR_EBDF11 |
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#define CONFIG_SYS_SCCR SCCR_RTSEL |
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#define CONFIG_SYS_DER 0 |
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*/ |
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */ |
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|
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#endif /* __CONFIG_H */ |
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