@ -1,5 +1,5 @@
/*
* ( C ) Copyright 2007
* ( C ) Copyright 2007 - 2008
* Matthias Fuchs , esd gmbh , matthias . fuchs @ esd - electronics . com .
* Based on board / amcc / sequoia / sequoia . c
*
@ -32,6 +32,7 @@
# include <ppc440.h>
# include <asm/processor.h>
# include <asm/io.h>
# include <asm/bitops.h>
# include <command.h>
# include <i2c.h>
# ifdef CONFIG_RESET_PHY_R
@ -43,12 +44,12 @@
DECLARE_GLOBAL_DATA_PTR ;
extern flash_info_t flash_info [ CFG_MAX_FLASH_BANKS ] ; /* info for FLASH chips */
extern flash_info_t flash_info [ CFG_MAX_FLASH_BANKS ] ; /* info for FLASH chips */
ulong flash_get_size ( ulong base , int banknum ) ;
int pci_is_66mhz ( void ) ;
int bootstrap_eeprom_read ( unsigned dev_addr , unsigned offset , uchar * buffer , unsigned cnt ) ;
int bootstrap_eeprom_read ( unsigned dev_addr , unsigned offset ,
uchar * buffer , unsigned cnt ) ;
struct serial_device * default_serial_console ( void )
{
@ -70,7 +71,8 @@ struct serial_device *default_serial_console(void)
/* mark scratchreg valid */
scratchreg = ( scratchreg & 0xffffff00 ) | 0x80 ;
i = bootstrap_eeprom_read ( CFG_I2C_BOOT_EEPROM_ADDR , 0x10 , buf , 4 ) ;
i = bootstrap_eeprom_read ( CFG_I2C_BOOT_EEPROM_ADDR ,
0x10 , buf , 4 ) ;
if ( ( i ! = - 1 ) & & ( buf [ 0 ] = = 0x19 ) & & ( buf [ 1 ] = = 0x75 ) ) {
scratchreg | = buf [ 2 ] ;
@ -99,10 +101,10 @@ int board_early_init_f(void)
mtdcr ( ebccfga , xbcfg ) ;
mtdcr ( ebccfgd , 0xf8400000 ) ;
/*--------------------------------------------------------------------
/*
* Setup the GPIO pins
* TODO : setup GPIOs via CFG_4xx_GPIO_TABLE in board ' s config file
* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
*/
out32 ( GPIO0_OR , 0x40000002 ) ;
out32 ( GPIO0_TCR , 0x4c90011f ) ;
out32 ( GPIO0_OSRL , 0x28011400 ) ;
@ -141,9 +143,9 @@ int board_early_init_f(void)
mtspr ( dbcr0 , 0x20000000 ) ; /* do chip reset */
}
/*--------------------------------------------------------------------
/*
* Setup the interrupt controller polarities , triggers , etc .
* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
*/
mtdcr ( uic0sr , 0xffffffff ) ; /* clear all */
mtdcr ( uic0er , 0x00000000 ) ; /* disable all */
mtdcr ( uic0cr , 0x00000005 ) ; /* ATI & UIC1 crit are critical */
@ -170,9 +172,11 @@ int board_early_init_f(void)
/* select Ethernet pins */
mfsdr ( SDR0_PFC1 , sdr0_pfc1 ) ;
sdr0_pfc1 = ( sdr0_pfc1 & ~ SDR0_PFC1_SELECT_MASK ) | SDR0_PFC1_SELECT_CONFIG_4 ;
sdr0_pfc1 = ( sdr0_pfc1 & ~ SDR0_PFC1_SELECT_MASK ) |
SDR0_PFC1_SELECT_CONFIG_4 ;
mfsdr ( SDR0_PFC2 , sdr0_pfc2 ) ;
sdr0_pfc2 = ( sdr0_pfc2 & ~ SDR0_PFC2_SELECT_MASK ) | SDR0_PFC2_SELECT_CONFIG_4 ;
sdr0_pfc2 = ( sdr0_pfc2 & ~ SDR0_PFC2_SELECT_MASK ) |
SDR0_PFC2_SELECT_CONFIG_4 ;
/* enable 2nd IIC */
sdr0_pfc1 = ( sdr0_pfc1 & ~ SDR0_PFC1_SIS_MASK ) | SDR0_PFC1_SIS_IIC1_SEL ;
@ -192,9 +196,9 @@ int board_early_init_f(void)
return 0 ;
}
/*---------------------------------------------------------------------------+
| misc_init_r .
+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
/*
* misc_init_r .
*/
int misc_init_r ( void )
{
uint pbcr ;
@ -221,32 +225,7 @@ int misc_init_r(void)
mtdcr ( ebccfga , pb0cr ) ;
# endif
pbcr = mfdcr ( ebccfgd ) ;
switch ( gd - > bd - > bi_flashsize ) {
case 1 < < 20 :
size_val = 0 ;
break ;
case 2 < < 20 :
size_val = 1 ;
break ;
case 4 < < 20 :
size_val = 2 ;
break ;
case 8 < < 20 :
size_val = 3 ;
break ;
case 16 < < 20 :
size_val = 4 ;
break ;
case 32 < < 20 :
size_val = 5 ;
break ;
case 64 < < 20 :
size_val = 6 ;
break ;
case 128 < < 20 :
size_val = 7 ;
break ;
}
size_val = ffs ( gd - > bd - > bi_flashsize ) - 21 ;
pbcr = ( pbcr & 0x0001ffff ) | gd - > bd - > bi_flashstart | ( size_val < < 17 ) ;
# if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr ( ebccfga , pb2cr ) ;
@ -286,20 +265,22 @@ int misc_init_r(void)
mfsdr ( SDR0_USB2H0CR , usb2h0cr ) ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_XOCLK_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL ; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_WDINT_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ ; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_DVBUS_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS ; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_DWNSTR_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST ; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_UTMICN_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST ; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST ;
/* An 8-bit/60MHz interface is the only possible alternative
when connecting the Device to the PHY */
/*
* An 8 - bit / 60 MHz interface is the only possible alternative
* when connecting the Device to the PHY
*/
usb2h0cr = usb2h0cr & ~ SDR0_USB2H0CR_WDINT_MASK ;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ ; /*1*/
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ ;
usb2d0cr = usb2d0cr & ~ SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK ;
sdr0_pfc1 = sdr0_pfc1 & ~ SDR0_PFC1_UES_MASK ;
@ -309,7 +290,7 @@ int misc_init_r(void)
mtsdr ( SDR0_USB2PHY0CR , usb2phy0cr ) ;
mtsdr ( SDR0_USB2H0CR , usb2h0cr ) ;
/*clear resets*/
/* clear resets */
udelay ( 1000 ) ;
mtsdr ( SDR0_SRST1 , 0x00000000 ) ;
udelay ( 1000 ) ;
@ -317,18 +298,18 @@ int misc_init_r(void)
printf ( " USB: Host \n " ) ;
} else if ( ( strcmp ( act , " dev " ) = = 0 ) | | ( in_be32 ( ( void * ) GPIO0_IR ) & GPIO0_USB_PRSNT ) ) {
/*-------------------PATCH-------------------------------*/
} else if ( ( strcmp ( act , " dev " ) = = 0 ) | |
( in_be32 ( ( void * ) GPIO0_IR ) & GPIO0_USB_PRSNT ) ) {
mfsdr ( SDR0_USB2PHY0CR , usb2phy0cr ) ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_XOCLK_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL ; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_DVBUS_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS ; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_DWNSTR_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST ; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_UTMICN_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST ; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST ;
mtsdr ( SDR0_USB2PHY0CR , usb2phy0cr ) ;
udelay ( 1000 ) ;
@ -344,7 +325,6 @@ int misc_init_r(void)
udelay ( 1000 ) ;
mtsdr ( SDR0_SRST1 , 0x60306000 ) ;
/*-------------------PATCH-------------------------------*/
/* SDR Setting */
mfsdr ( SDR0_USB2PHY0CR , usb2phy0cr ) ;
@ -353,23 +333,23 @@ int misc_init_r(void)
mfsdr ( SDR0_PFC1 , sdr0_pfc1 ) ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_XOCLK_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL ; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_WDINT_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ ; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_DVBUS_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN ; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_DWNSTR_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV ; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV ;
usb2phy0cr = usb2phy0cr & ~ SDR0_USB2PHY0CR_UTMICN_MASK ;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV ; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV ;
usb2h0cr = usb2h0cr & ~ SDR0_USB2H0CR_WDINT_MASK ;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ ; /*0*/
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ ;
usb2d0cr = usb2d0cr & ~ SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK ;
sdr0_pfc1 = sdr0_pfc1 & ~ SDR0_PFC1_UES_MASK ;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL ; /*1*/
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL ;
mtsdr ( SDR0_USB2H0CR , usb2h0cr ) ;
mtsdr ( SDR0_USB2PHY0CR , usb2phy0cr ) ;
@ -453,43 +433,42 @@ void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
}
# endif
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things . Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted .
/*
* pci_pre_init
*
* Different boards may wish to customize the pci controller structure
* ( add regions , override default access routines , etc ) or perform
* certain pre - initialization actions .
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things . Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted .
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
* Different boards may wish to customize the pci controller structure
* ( add regions , override default access routines , etc ) or perform
* certain pre - initialization actions .
*/
# if defined(CONFIG_PCI)
int pci_pre_init ( struct pci_controller * hose )
{
unsigned long addr ;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode .
+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode .
*/
mfsdr ( sdr_amp1 , addr ) ;
mtsdr ( sdr_amp1 , ( addr & 0x000000FF ) | 0x0000FF00 ) ;
addr = mfdcr ( plb3_acr ) ;
mtdcr ( plb3_acr , addr | 0x80000000 ) ;
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr ( sdr_amp0 , addr ) ;
mtsdr ( sdr_amp0 , ( addr & 0x000000FF ) | 0x0000FF00 ) ;
addr = mfdcr ( plb4_acr ) | 0xa0000000 ; /* Was 0x8---- */
mtdcr ( plb4_acr , addr ) ;
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode .
+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
/*
* Set Nebula PLB4 arbiter to fair mode .
*/
/* Segment0 */
addr = ( mfdcr ( plb0_acr ) & ~ plb0_acr_ppm_mask ) | plb0_acr_ppm_fair ;
addr = ( addr & ~ plb0_acr_hbu_mask ) | plb0_acr_hbu_enabled ;
@ -512,64 +491,84 @@ int pci_pre_init(struct pci_controller *hose)
}
# endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map ( PIM ) . But the bootstrap config choices are limited and
* may not be sufficient for a given board .
/*
* pci_target_init
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
* The bootstrap configuration provides default settings for the pci
* inbound map ( PIM ) . But the bootstrap config choices are limited and
* may not be sufficient for a given board .
*/
# if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init ( struct pci_controller * hose )
{
/*--------------------------------------------------------------------------+
char * ptmla_str , * ptmms_str ;
/*
* Set up Direct MMIO registers
* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
/*--------------------------------------------------------------------------+
| PowerPC440EPX PCI Master configuration .
| Map one 1 Gig range of PLB / processor addresses to PCI memory space .
| PLB address 0x80000000 - 0xBFFFFFFF = = > PCI address 0x80000000 - 0xBFFFFFFF
| Use byte reversed out routines to handle endianess .
| Make this region non - prefetchable .
+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
out32r ( PCIX0_PMM0MA , 0x00000000 ) ; /* PMM0 Mask/Attribute - disabled b4 setting */
*/
/*
* PowerPC440EPX PCI Master configuration .
* Map one 1 Gig range of PLB / processor addresses to PCI memory space .
* PLB address 0x80000000 - 0xBFFFFFFF
* = = > PCI address 0x80000000 - 0xBFFFFFFF
* Use byte reversed out routines to handle endianess .
* Make this region non - prefetchable .
*/
out32r ( PCIX0_PMM0MA , 0x00000000 ) ; /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r ( PCIX0_PMM0LA , CFG_PCI_MEMBASE ) ; /* PMM0 Local Address */
out32r ( PCIX0_PMM0PCILA , CFG_PCI_MEMBASE ) ; /* PMM0 PCI Low Address */
out32r ( PCIX0_PMM0PCILA , CFG_PCI_MEMBASE ) ; /* PMM0 PCI Low Address */
out32r ( PCIX0_PMM0PCIHA , 0x00000000 ) ; /* PMM0 PCI High Address */
out32r ( PCIX0_PMM0MA , 0xc0000001 ) ; /* 1G + No prefetching, and enable region */
out32r ( PCIX0_PMM0MA , 0xc0000001 ) ; /* 1G + No prefetching, */
/* and enable region */
if ( ! is_monarch ( ) ) {
/* BAR1: top 64MB of RAM */
out32r ( PCIX0_PTM1MS , 0xfc000001 ) ; /* Memory Size/Attribute */
out32r ( PCIX0_PTM1LA , 0x0c000000 ) ; /* Local Addr. Reg */
ptmla_str = getenv ( " ptm1la " ) ;
ptmms_str = getenv ( " ptm1ms " ) ;
if ( NULL ! = ptmla_str & & NULL ! = ptmms_str ) {
out32r ( PCIX0_PTM1MS ,
simple_strtoul ( ptmms_str , NULL , 16 ) ) ;
out32r ( PCIX0_PTM1LA ,
simple_strtoul ( ptmla_str , NULL , 16 ) ) ;
} else {
/* BAR1: default top 64MB of RAM */
out32r ( PCIX0_PTM1MS , 0xfc000001 ) ;
out32r ( PCIX0_PTM1LA , 0x0c000000 ) ;
}
} else {
/* BAR1: complete 256MB RAM (TODO: make dynamic) */
out32r ( PCIX0_PTM1MS , 0xf0000001 ) ; /* Memory Size/Attribute */
out32r ( PCIX0_PTM1LA , 0x00000000 ) ; /* Local Addr. Reg */
/* BAR1: default: complete 256MB RAM */
out32r ( PCIX0_PTM1MS , 0xf0000001 ) ;
out32r ( PCIX0_PTM1LA , 0x00000000 ) ;
}
/* BAR2: 16 MB FPGA registers */
out32r ( PCIX0_PTM2MS , 0xff000001 ) ; /* Memory Size/Attribute */
out32r ( PCIX0_PTM2LA , 0xef000000 ) ; /* Local Addr. Reg */
ptmla_str = getenv ( " ptm2la " ) ; /* Local Addr. Reg */
ptmms_str = getenv ( " ptm2ms " ) ; /* Memory Size/Attribute */
if ( NULL ! = ptmla_str & & NULL ! = ptmms_str ) {
out32r ( PCIX0_PTM2MS , simple_strtoul ( ptmms_str , NULL , 16 ) ) ;
out32r ( PCIX0_PTM2LA , simple_strtoul ( ptmla_str , NULL , 16 ) ) ;
} else {
/* BAR2: default: 16 MB FPGA + registers */
out32r ( PCIX0_PTM2MS , 0xff000001 ) ; /* Memory Size/Attribute */
out32r ( PCIX0_PTM2LA , 0xef000000 ) ; /* Local Addr. Reg */
}
if ( is_monarch ( ) ) {
/* BAR2: map FPGA registers behind system memory at 1GB */
pci_write_config_dword ( 0 , PCI_BASE_ADDRESS_2 , 0x40000008 ) ;
}
/*--------------------------------------------------------------------------+
/*
* Set up Configuration registers
* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
*/
/* Program the board's vendor id */
pci_write_config_word ( 0 , PCI_SUBSYSTEM_VENDOR_ID ,
CFG_PCI_SUBSYS_VENDORID ) ;
#if 0 /* disabled for PMC405 backward compatibility */
/* disabled for PMC405 backward compatibility */
/* Configure command register as bus master */
pci_write_config_word ( 0 , PCI_COMMAND , PCI_COMMAND_MASTER ) ;
# endif
/* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
/* 240nS PCI clock */
pci_write_config_word ( 0 , PCI_LATENCY_TIMER , 1 ) ;
@ -587,8 +586,10 @@ void pci_target_init(struct pci_controller *hose)
CFG_PCI_CLASSCODE_NONMONARCH ) ;
/* PCI configuration done: release ERREADY */
out_be32 ( ( void * ) GPIO1_OR , in_be32 ( ( void * ) GPIO1_OR ) | GPIO1_PPC_EREADY ) ;
out_be32 ( ( void * ) GPIO1_TCR , in_be32 ( ( void * ) GPIO1_TCR ) | GPIO1_PPC_EREADY ) ;
out_be32 ( ( void * ) GPIO1_OR ,
in_be32 ( ( void * ) GPIO1_OR ) | GPIO1_PPC_EREADY ) ;
out_be32 ( ( void * ) GPIO1_TCR ,
in_be32 ( ( void * ) GPIO1_TCR ) | GPIO1_PPC_EREADY ) ;
} else {
/* Program the board's subsystem id/classcode */
pci_write_config_word ( 0 , PCI_SUBSYSTEM_ID ,
@ -599,20 +600,19 @@ void pci_target_init(struct pci_controller *hose)
}
# endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/*
* pci_master_init
*/
# if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init ( struct pci_controller * hose )
{
unsigned short temp_short ;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs .
| Enable PowerPC440 EP to be a master on the PCI bus ( PMM ) .
| Enable PowerPC440 EP to act as a PCI memory target ( PTM ) .
+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
/*
* Write the PowerPC440 EP PCI Configuration regs .
* Enable PowerPC440 EP to be a master on the PCI bus ( PMM ) .
* Enable PowerPC440 EP to act as a PCI memory target ( PTM ) .
*/
if ( is_monarch ( ) ) {
pci_read_config_word ( 0 , PCI_COMMAND , & temp_short ) ;
pci_write_config_word ( 0 , PCI_COMMAND ,
@ -622,7 +622,6 @@ void pci_master_init(struct pci_controller *hose)
}
# endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
static void wait_for_pci_ready ( void )
{
int i ;
@ -649,22 +648,19 @@ static void wait_for_pci_ready(void)
}
}
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed . With various hardware environments ( especially cPCI and
* PPMC ) it ' s insufficient to depend on the state of the arbiter enable
* bit in the strap register , or generic host / adapter assumptions .
*
* Rather than hard - code a bad assumption in the general 440 code , the
* 440 pci code requires the board to decide at runtime .
/*
* is_pci_host
*
* Return 0 for adapter mode , non - zero for host ( monarch ) mode .
* This routine is called to determine if a pci scan should be
* performed . With various hardware environments ( especially cPCI and
* PPMC ) it ' s insufficient to depend on the state of the arbiter enable
* bit in the strap register , or generic host / adapter assumptions .
*
* Rather than hard - code a bad assumption in the general 440 code , the
* 440 pci code requires the board to decide at runtime .
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
* Return 0 for adapter mode , non - zero for host ( monarch ) mode .
*/
# if defined(CONFIG_PCI)
int is_pci_host ( struct pci_controller * hose )
{
@ -681,6 +677,7 @@ int is_pci_host(struct pci_controller *hose)
return 0 ;
}
# endif /* defined(CONFIG_PCI) */
# if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power - on long - running tests
@ -692,7 +689,6 @@ int post_hotkeys_pressed(void)
}
# endif /* CONFIG_POST */
# ifdef CONFIG_RESET_PHY_R
void reset_phy ( void )
{
@ -713,17 +709,19 @@ void reset_phy(void)
# endif
# if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* < state > - 1 : deliver current state
/*
* Input : < dev_addr > I2C address of EEPROM device to enable .
* < state > - 1 : deliver current state
* 0 : disable write
* 1 : enable write
* Returns : - 1 : wrong device address
* 0 : dis - / en - able done
* Returns : - 1 : wrong device address
* 0 : dis - / en - able done
* 0 / 1 : current state if < state > was - 1.
*/
int eeprom_write_enable ( unsigned dev_addr , int state )
{
if ( ( CFG_I2C_EEPROM_ADDR ! = dev_addr ) & & ( CFG_I2C_BOOT_EEPROM_ADDR ! = dev_addr ) ) {
if ( ( CFG_I2C_EEPROM_ADDR ! = dev_addr ) & &
( CFG_I2C_BOOT_EEPROM_ADDR ! = dev_addr ) ) {
return - 1 ;
} else {
switch ( state ) {
@ -747,9 +745,9 @@ int eeprom_write_enable(unsigned dev_addr, int state)
}
# endif /* #if defined(CFG_EEPROM_WREN) */
# define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
int bootstrap_eeprom_write ( unsigned dev_addr , unsigned offset , uchar * buffer , unsigned cnt )
int bootstrap_eeprom_write ( unsigned dev_addr , unsigned offset ,
uchar * buffer , unsigned cnt )
{
unsigned end = offset + cnt ;
unsigned blk_off ;
@ -758,7 +756,8 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, un
# if defined(CFG_EEPROM_WREN)
eeprom_write_enable ( dev_addr , 1 ) ;
# endif
/* Write data until done or would cross a write page boundary.
/*
* Write data until done or would cross a write page boundary .
* We must write the address again when changing pages
* because the address counter only increments within a page .
*/
@ -780,7 +779,8 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, un
# define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
# define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
maxlen = BOOT_EEPROM_PAGE_SIZE - BOOT_EEPROM_PAGE_OFFSET ( blk_off ) ;
maxlen = BOOT_EEPROM_PAGE_SIZE -
BOOT_EEPROM_PAGE_OFFSET ( blk_off ) ;
if ( maxlen > I2C_RXTX_LEN )
maxlen = I2C_RXTX_LEN ;
@ -803,14 +803,15 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, un
return rcode ;
}
int bootstrap_eeprom_read ( unsigned dev_addr , unsigned offset , uchar * buffer , unsigned cnt )
int bootstrap_eeprom_read ( unsigned dev_addr , unsigned offset ,
uchar * buffer , unsigned cnt )
{
unsigned end = offset + cnt ;
unsigned blk_off ;
int rcode = 0 ;
/* Read data until done or would cross a page boundary.
/*
* Read data until done or would cross a page boundary .
* We must write the address again when changing pages
* because the next page may be in a different device .
*/
@ -844,7 +845,6 @@ int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, un
return rcode ;
}
# if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
int usb_board_init ( void )
{
@ -854,7 +854,8 @@ int usb_board_init(void)
if ( ( act = = NULL | | strcmp ( act , " hostdev " ) = = 0 ) & &
! ( in_be32 ( ( void * ) GPIO0_IR ) & GPIO0_USB_PRSNT ) )
/* enable power on USB socket */
out_be32 ( ( void * ) GPIO1_OR , in_be32 ( ( void * ) GPIO1_OR ) & ~ GPIO1_USB_PWR_N ) ;
out_be32 ( ( void * ) GPIO1_OR ,
in_be32 ( ( void * ) GPIO1_OR ) & ~ GPIO1_USB_PWR_N ) ;
for ( i = 0 ; i < 1000 ; i + + )
udelay ( 1000 ) ;
Wolfgang Denk
17 years ago