fix TI Innovator/OMAP1510 pin configs * Patches by Kshitij, 18 Aug 2003 - add support for arm926ejs cpu core - add support for TI OMAP 1610 Innovator Boardmaster
wdenk
22 years ago
parent
c29fdfc1d8
commit
6f21347d49
@ -0,0 +1,47 @@ |
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := omap1610innovator.o flash.o
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SOBJS := platform.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $^
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,26 @@ |
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# (C) Copyright 2003
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# Texas Instruments, <www.ti.com>
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# Kshitij Gupta <Kshitij@ti.com>
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#
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# TI Innovator board with OMAP1610 (ARM925EJS) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# Innovator has 1 bank of 256 MB SDRAM
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# Physical Address:
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# 1000'0000 to 2000'0000
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#
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#
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# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
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# (mem base + reserved)
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#
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# we load ourself to 1100'0000
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#
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#
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TEXT_BASE = 0x11000000
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@ -0,0 +1,482 @@ |
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/*
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* (C) Copyright 2001 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2003 |
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* Texas Instruments, <www.ti.com> |
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* Kshitij Gupta <Kshitij@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <linux/byteorder/swab.h> |
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#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/* Board support for 1 or 2 flash devices */ |
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#undef FLASH_PORT_WIDTH32 |
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#define FLASH_PORT_WIDTH16 |
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#ifdef FLASH_PORT_WIDTH16 |
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#define FLASH_PORT_WIDTH ushort |
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#define FLASH_PORT_WIDTHV vu_short |
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#define SWAP(x) __swab16(x) |
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#else |
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#define FLASH_PORT_WIDTH ulong |
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#define FLASH_PORT_WIDTHV vu_long |
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#define SWAP(x) __swab32(x) |
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#endif |
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#define FPW FLASH_PORT_WIDTH |
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#define FPWV FLASH_PORT_WIDTHV |
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#define mb() __asm__ __volatile__ ("" : : : "memory") |
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/* Flash Organization Structure */ |
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typedef struct OrgDef { |
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unsigned int sector_number; |
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unsigned int sector_size; |
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} OrgDef; |
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/* Flash Organizations */ |
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OrgDef OrgIntel_28F256L18T[] = { |
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{4, 32 * 1024}, /* 4 * 32kBytes sectors */ |
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{255, 128 * 1024}, /* 255 * 128kBytes sectors */ |
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}; |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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unsigned long flash_init (void); |
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static ulong flash_get_size (FPW * addr, flash_info_t * info); |
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static int write_data (flash_info_t * info, ulong dest, FPW data); |
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static void flash_get_offsets (ulong base, flash_info_t * info); |
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void inline spin_wheel (void); |
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void flash_print_info (flash_info_t * info); |
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void flash_unprotect_sectors (FPWV * addr); |
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int flash_erase (flash_info_t * info, int s_first, int s_last); |
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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int i; |
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ulong size = 0; |
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { |
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switch (i) { |
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case 0: |
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flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); |
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flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); |
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break; |
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default: |
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panic ("configured to many flash banks!\n"); |
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break; |
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} |
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size += flash_info[i].size; |
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} |
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/* Protect monitor and environment sectors
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*/ |
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flash_protect (FLAG_PROTECT_SET, |
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CFG_FLASH_BASE, |
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CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); |
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flash_protect (FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); |
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return size; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_get_offsets (ulong base, flash_info_t * info) |
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{ |
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int i; |
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OrgDef *pOrgDef; |
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pOrgDef = OrgIntel_28F256L18T; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return; |
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} |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { |
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for (i = 0; i < info->sector_count; i++) { |
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if (i > 255) { |
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info->start[i] = base + (i * 0x8000); |
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info->protect[i] = 0; |
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} else { |
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info->start[i] = base + |
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(i * PHYS_FLASH_SECT_SIZE); |
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info->protect[i] = 0; |
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} |
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} |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t * info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: |
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printf ("INTEL "); |
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break; |
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default: |
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printf ("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F256L18T: |
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printf ("FLASH 28F256L18T\n"); |
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break; |
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default: |
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printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (FPW * addr, flash_info_t * info) |
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{ |
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volatile FPW value; |
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/* Write auto select command: read Manufacturer ID */ |
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addr[0x5555] = (FPW) 0x00AA00AA; |
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addr[0x2AAA] = (FPW) 0x00550055; |
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addr[0x5555] = (FPW) 0x00900090; |
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mb (); |
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value = addr[0]; |
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switch (value) { |
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case (FPW) INTEL_MANUFACT: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (0); /* no or unknown flash */ |
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} |
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mb (); |
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value = addr[1]; /* device ID */ |
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switch (value) { |
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case (FPW) (INTEL_ID_28F256L18T): |
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info->flash_id += FLASH_28F256L18T; |
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info->sector_count = 259; |
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info->size = 0x02000000; |
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break; /* => 32 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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break; |
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} |
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if (info->sector_count > CFG_MAX_FLASH_SECT) { |
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printf ("** ERROR: sector count %d > max (%d) **\n", |
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info->sector_count, CFG_MAX_FLASH_SECT); |
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info->sector_count = CFG_MAX_FLASH_SECT; |
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} |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (info->size); |
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} |
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/* unprotects a sector for write and erase
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* on some intel parts, this unprotects the entire chip, but it |
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* wont hurt to call this additional times per sector... |
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*/ |
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void flash_unprotect_sectors (FPWV * addr) |
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{ |
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#define PD_FINTEL_WSMS_READY_MASK 0x0080 |
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*addr = (FPW) 0x00500050; /* clear status register */ |
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/* this sends the clear lock bit command */ |
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*addr = (FPW) 0x00600060; |
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*addr = (FPW) 0x00D000D0; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t * info, int s_first, int s_last) |
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{ |
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int flag, prot, sect; |
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ulong type, start, last; |
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int rcode = 0; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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type = (info->flash_id & FLASH_VENDMASK); |
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if ((type != FLASH_MAN_INTEL)) { |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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start = get_timer (0); |
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last = start; |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect <= s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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FPWV *addr = (FPWV *) (info->start[sect]); |
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FPW status; |
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printf ("Erasing sector %2d ... ", sect); |
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flash_unprotect_sectors (addr); |
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked (); |
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*addr = (FPW) 0x00500050;/* clear status register */ |
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*addr = (FPW) 0x00200020;/* erase setup */ |
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*addr = (FPW) 0x00D000D0;/* erase confirm */ |
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while (((status = |
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*addr) & (FPW) 0x00800080) != |
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(FPW) 0x00800080) { |
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if (get_timer_masked () >
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CFG_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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/* suspend erase */ |
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*addr = (FPW) 0x00B000B0; |
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/* reset to read mode */ |
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*addr = (FPW) 0x00FF00FF; |
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rcode = 1; |
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break; |
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} |
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} |
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/* clear status register cmd. */ |
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*addr = (FPW) 0x00500050; |
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*addr = (FPW) 0x00FF00FF;/* resest to read mode */ |
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printf (" done\n"); |
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} |
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} |
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return rcode; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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* 4 - Flash not identified |
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*/ |
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
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{ |
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ulong cp, wp; |
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FPW data; |
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int count, i, l, rc, port_width; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return 4; |
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} |
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/* get lower word aligned address */ |
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#ifdef FLASH_PORT_WIDTH16 |
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wp = (addr & ~1); |
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port_width = 2; |
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#else |
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wp = (addr & ~3); |
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port_width = 4; |
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#endif |
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/*
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* handle unaligned start bytes |
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*/ |
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if ((l = addr - wp) != 0) { |
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data = 0; |
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for (i = 0, cp = wp; i < l; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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for (; i < port_width && cnt > 0; ++i) { |
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data = (data << 8) | *src++; |
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--cnt; |
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++cp; |
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} |
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for (; cnt == 0 && i < port_width; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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} |
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/*
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* handle word aligned part |
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*/ |
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count = 0; |
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while (cnt >= port_width) { |
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data = 0; |
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for (i = 0; i < port_width; ++i) { |
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data = (data << 8) | *src++; |
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} |
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if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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cnt -= port_width; |
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if (count++ > 0x800) { |
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spin_wheel (); |
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count = 0; |
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} |
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} |
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if (cnt == 0) { |
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return (0); |
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} |
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/*
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* handle unaligned tail bytes |
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*/ |
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data = 0; |
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for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { |
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data = (data << 8) | *src++; |
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--cnt; |
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} |
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for (; i < port_width; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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return (write_data (info, wp, SWAP (data))); |
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} |
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/*-----------------------------------------------------------------------
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* Write a word or halfword to Flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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static int write_data (flash_info_t * info, ulong dest, FPW data) |
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{ |
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FPWV *addr = (FPWV *) dest; |
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ulong status; |
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int flag; |
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/* Check if Flash is (sufficiently) erased */ |
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if ((*addr & data) != data) { |
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printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); |
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return (2); |
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} |
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flash_unprotect_sectors (addr); |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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*addr = (FPW) 0x00400040; /* write setup */ |
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*addr = data; |
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked (); |
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/* wait while polling the status register */ |
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while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
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if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { |
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*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (1); |
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} |
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} |
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*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (0); |
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} |
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void inline spin_wheel (void) |
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{ |
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static int p = 0; |
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static char w[] = "\\/-"; |
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printf ("\010%c", w[p]); |
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(++p == 3) ? (p = 0) : 0; |
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} |
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@ -0,0 +1,270 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Kshitij Gupta <Kshitij@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#if defined(CONFIG_OMAP1610) |
||||
#include <./configs/omap1510.h> |
||||
#endif |
||||
|
||||
void flash__init (void); |
||||
void ether__init (void); |
||||
void set_muxconf_regs (void); |
||||
void peripheral_power_enable (void); |
||||
|
||||
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) |
||||
|
||||
static inline void delay (unsigned long loops) |
||||
{ |
||||
__asm__ volatile ("1:\n" |
||||
"subs %0, %1, #1\n" |
||||
"bne 1b":"=r" (loops):"0" (loops)); |
||||
} |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_init (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* arch number of OMAP 1510-Board */ |
||||
/* to be changed for OMAP 1610 Board */ |
||||
gd->bd->bi_arch_number = 234; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0x10000100; |
||||
|
||||
/* Configure MUX settings */ |
||||
set_muxconf_regs (); |
||||
peripheral_power_enable (); |
||||
|
||||
/* this speeds up your boot a quite a bit. However to make it
|
||||
* work, you need make sure your kernel startup flush bug is fixed. |
||||
* ... rkw ... |
||||
*/ |
||||
icache_enable (); |
||||
|
||||
flash__init (); |
||||
ether__init (); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
/* currently empty */ |
||||
return (0); |
||||
} |
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
void flash__init (void) |
||||
{ |
||||
#define EMIFS_GlB_Config_REG 0xfffecc0c |
||||
unsigned int regval; |
||||
regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); |
||||
/* Turn off write protection for flash devices. */ |
||||
regval = regval | 0x0001; |
||||
*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; |
||||
} |
||||
/*************************************************************
|
||||
Routine:ether__init |
||||
Description: take the Ethernet controller out of reset and wait |
||||
for the EEPROM load to complete. |
||||
*************************************************************/ |
||||
void ether__init (void) |
||||
{ |
||||
#define ETH_CONTROL_REG 0x0400000b |
||||
|
||||
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; |
||||
udelay (3); |
||||
} |
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
int dram_init (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/******************************************************
|
||||
Routine: set_muxconf_regs |
||||
Description: Setting up the configuration Mux registers |
||||
specific to the hardware |
||||
*******************************************************/ |
||||
void set_muxconf_regs (void) |
||||
{ |
||||
volatile unsigned int *MuxConfReg; |
||||
/* set each registers to its reset value; */ |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); |
||||
/* setup for UART1 */ |
||||
*MuxConfReg &= ~(0x02000000); /* bit 25 */ |
||||
/* setup for UART2 */ |
||||
*MuxConfReg &= ~(0x01000000); /* bit 24 */ |
||||
/* Disable Uwire CS Hi-Z */ |
||||
*MuxConfReg |= 0x08000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); |
||||
/*setup mux for UART3 */ |
||||
*MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ |
||||
*MuxConfReg &= ~0x0000003e; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); |
||||
/* Disable Uwire CS Hi-Z */ |
||||
*MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); |
||||
/* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ |
||||
/* hardware will actually use TX and RTS based on bit 25 in */ |
||||
/* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ |
||||
*MuxConfReg |= 0x00201000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); |
||||
/* setup for UART2 */ |
||||
/* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ |
||||
/* hardware will actually use TX and RTS based on bit 24 in */ |
||||
/* FUNC_MUX_CTRL_0. */ |
||||
*MuxConfReg |= 0x09000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); |
||||
*MuxConfReg = 0x00000000; |
||||
/* mux setup for SD/MMC driver */ |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); |
||||
*MuxConfReg &= 0xFFFE0FFF; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); |
||||
/* bit 13 for MMC2 XOR_CLK */ |
||||
*MuxConfReg &= ~(0x00002000); |
||||
/* bit 29 for UART 1 */ |
||||
*MuxConfReg &= ~(0x00002000); |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); |
||||
/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ |
||||
*MuxConfReg |= 0x000C0000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); |
||||
*MuxConfReg &= ~(0x00000070); |
||||
*MuxConfReg &= ~(0x00000008); |
||||
*MuxConfReg |= 0x00000003; |
||||
*MuxConfReg |= 0x00000180; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); |
||||
/* bit 17, software controls VBUS */ |
||||
*MuxConfReg &= ~(0x00020000); |
||||
/* Enable USB 48 and 12M clocks */ |
||||
*MuxConfReg |= 0x00000200; |
||||
*MuxConfReg &= ~(0x00000180); |
||||
/*2.75V for MMCSDIO1 */ |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); |
||||
*MuxConfReg = 0x00001FE7; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); |
||||
*MuxConfReg = 0x00000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); |
||||
*MuxConfReg = 0x00000000; |
||||
/* Turn on UART2 48 MHZ clock */ |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); |
||||
*MuxConfReg |= 0x40000000; |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); |
||||
/* setup for USB VBus detection OMAP161x */ |
||||
*MuxConfReg |= 0x00040000; /* bit 18 */ |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); |
||||
/* PullUps for SD/MMC driver */ |
||||
*MuxConfReg |= ~(0xFFFE0FFF); |
||||
MuxConfReg = |
||||
(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); |
||||
*MuxConfReg = COMP_MODE_ENABLE; |
||||
} |
||||
|
||||
/******************************************************
|
||||
Routine: peripheral_power_enable |
||||
Description: Enable the power for UART1 |
||||
*******************************************************/ |
||||
void peripheral_power_enable (void) |
||||
{ |
||||
#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) |
||||
#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) |
||||
|
||||
*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; |
||||
} |
||||
@ -0,0 +1,385 @@ |
||||
/* |
||||
* Board specific setup info |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Kshitij Gupta <Kshitij@ti.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
#if defined(CONFIG_OMAP1610) |
||||
#include <./configs/omap1510.h> |
||||
#endif |
||||
|
||||
|
||||
_TEXT_BASE: |
||||
.word TEXT_BASE /* sdram load addr from config.mk */ |
||||
|
||||
.globl platformsetup
|
||||
platformsetup: |
||||
|
||||
|
||||
/*------------------------------------------------------* |
||||
* Set up ARM CLM registers (IDLECT1) * |
||||
*------------------------------------------------------*/ |
||||
ldr r0, REG_ARM_IDLECT1 |
||||
ldr r1, VAL_ARM_IDLECT1 |
||||
str r1, [r0] |
||||
|
||||
/*------------------------------------------------------* |
||||
* Set up ARM CLM registers (IDLECT2) * |
||||
*------------------------------------------------------*/ |
||||
ldr r0, REG_ARM_IDLECT2 |
||||
ldr r1, VAL_ARM_IDLECT2 |
||||
str r1, [r0] |
||||
|
||||
/*------------------------------------------------------* |
||||
* Set up ARM CLM registers (IDLECT3) * |
||||
*------------------------------------------------------*/ |
||||
ldr r0, REG_ARM_IDLECT3 |
||||
ldr r1, VAL_ARM_IDLECT3 |
||||
str r1, [r0] |
||||
|
||||
|
||||
mov r1, #0x01 /* PER_EN bit */ |
||||
ldr r0, REG_ARM_RSTCT2 |
||||
strh r1, [r0] /* CLKM; Peripheral reset. */
|
||||
|
||||
/* Set CLKM to Sync-Scalable */ |
||||
/* I supposedly need to enable the dsp clock before switching */ |
||||
mov r1, #0x0000 |
||||
ldr r0, REG_ARM_SYSST |
||||
strh r1, [r0] |
||||
mov r0, #0x400 |
||||
1: |
||||
subs r0, r0, #0x1 /* wait for any bubbles to finish */ |
||||
bne 1b |
||||
ldr r1, VAL_ARM_CKCTL |
||||
ldr r0, REG_ARM_CKCTL |
||||
strh r1, [r0] |
||||
|
||||
/* a few nops to let settle */ |
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
|
||||
/* setup DPLL 1 */ |
||||
/* Ramp up the clock to 96Mhz */ |
||||
ldr r1, VAL_DPLL1_CTL |
||||
ldr r0, REG_DPLL1_CTL |
||||
strh r1, [r0] |
||||
ands r1, r1, #0x10 /* Check if PLL is enabled. */ |
||||
beq lock_end /* Do not look for lock if BYPASS selected */ |
||||
2: |
||||
ldrh r1, [r0] |
||||
ands r1, r1, #0x01 /* Check the LOCK bit.*/ |
||||
beq 2b /* loop until bit goes hi. */ |
||||
lock_end: |
||||
|
||||
|
||||
/*------------------------------------------------------* |
||||
* Turn off the watchdog during init... * |
||||
*------------------------------------------------------*/ |
||||
ldr r0, REG_WATCHDOG |
||||
ldr r1, WATCHDOG_VAL1 |
||||
str r1, [r0] |
||||
ldr r1, WATCHDOG_VAL2 |
||||
str r1, [r0] |
||||
ldr r0, REG_WSPRDOG |
||||
ldr r1, WSPRDOG_VAL1 |
||||
str r1, [r0] |
||||
ldr r0, REG_WWPSDOG |
||||
|
||||
watch1Wait: |
||||
ldr r1, [r0] |
||||
tst r1, #0x10 |
||||
bne watch1Wait |
||||
|
||||
ldr r0, REG_WSPRDOG |
||||
ldr r1, WSPRDOG_VAL2 |
||||
str r1, [r0] |
||||
ldr r0, REG_WWPSDOG |
||||
watch2Wait: |
||||
ldr r1, [r0] |
||||
tst r1, #0x10 |
||||
bne watch2Wait |
||||
|
||||
|
||||
|
||||
|
||||
/* Set memory timings corresponding to the new clock speed */ |
||||
|
||||
/* Check execution location to determine current execution location |
||||
* and branch to appropriate initialization code. |
||||
*/ |
||||
/* Load physical SDRAM base. */ |
||||
mov r0, #0x10000000 |
||||
/* Get current execution location. */ |
||||
mov r1, pc |
||||
/* Compare. */ |
||||
cmp r1, r0 |
||||
/* Skip over EMIF-fast initialization if running from SDRAM. */ |
||||
bge skip_sdram |
||||
|
||||
/* |
||||
* Delay for SDRAM initialization. |
||||
*/ |
||||
mov r3, #0x1800 /* value should be checked */ |
||||
3: |
||||
subs r3, r3, #0x1 /* Decrement count */ |
||||
bne 3b |
||||
|
||||
|
||||
/* |
||||
* Set SDRAM control values. Disable refresh before MRS command. |
||||
*/ |
||||
|
||||
/* mobile ddr operation */ |
||||
ldr r0, REG_SDRAM_OPERATION |
||||
mov r2, #07 |
||||
str r2, [r0] |
||||
|
||||
/* config register */ |
||||
ldr r0, REG_SDRAM_CONFIG |
||||
ldr r1, SDRAM_CONFIG_VAL |
||||
str r1, [r0] |
||||
|
||||
/* manual command register */ |
||||
ldr r0, REG_SDRAM_MANUAL_CMD |
||||
/* issue set cke high */ |
||||
mov r1, #CMD_SDRAM_CKE_SET_HIGH |
||||
str r1, [r0] |
||||
/* issue nop */ |
||||
mov r1, #CMD_SDRAM_NOP |
||||
str r1, [r0] |
||||
|
||||
mov r2, #0x0100 |
||||
waitMDDR1: |
||||
subs r2, r2, #1 |
||||
bne waitMDDR1 /* delay loop */ |
||||
|
||||
/* issue precharge */ |
||||
mov r1, #CMD_SDRAM_PRECHARGE |
||||
str r1, [r0] |
||||
|
||||
/* issue autorefresh x 2 */ |
||||
mov r1, #CMD_SDRAM_AUTOREFRESH |
||||
str r1, [r0] |
||||
str r1, [r0] |
||||
|
||||
/* mrs register ddr mobile */ |
||||
ldr r0, REG_SDRAM_MRS |
||||
mov r1, #0x33 |
||||
str r1, [r0] |
||||
|
||||
/* emrs1 low-power register */ |
||||
ldr r0, REG_SDRAM_EMRS1 |
||||
/* self refresh on all banks */ |
||||
mov r1, #0 |
||||
str r1, [r0] |
||||
|
||||
ldr r0, REG_DLL_URD_CONTROL |
||||
ldr r1, DLL_URD_CONTROL_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, REG_DLL_LRD_CONTROL |
||||
ldr r1, DLL_LRD_CONTROL_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, REG_DLL_WRT_CONTROL |
||||
ldr r1, DLL_WRT_CONTROL_VAL |
||||
str r1, [r0] |
||||
|
||||
/* delay loop */ |
||||
mov r2, #0x0100 |
||||
waitMDDR2: |
||||
subs r2, r2, #1 |
||||
bne waitMDDR2 |
||||
|
||||
/* |
||||
* Delay for SDRAM initialization. |
||||
*/ |
||||
mov r3, #0x1800 |
||||
4: |
||||
subs r3, r3, #1 /* Decrement count. */ |
||||
bne 4b |
||||
b common_tc |
||||
|
||||
skip_sdram: |
||||
|
||||
ldr r0, REG_SDRAM_CONFIG |
||||
ldr r1, SDRAM_CONFIG_VAL |
||||
str r1, [r0] |
||||
|
||||
common_tc: |
||||
/* slow interface */ |
||||
ldr r1, VAL_TC_EMIFS_CS0_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS0_CONFIG |
||||
str r1, [r0] /* Chip Select 0 */ |
||||
|
||||
ldr r1, VAL_TC_EMIFS_CS1_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS1_CONFIG |
||||
str r1, [r0] /* Chip Select 1 */ |
||||
ldr r1, VAL_TC_EMIFS_CS3_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS3_CONFIG |
||||
str r1, [r0] /* Chip Select 3 */ |
||||
/* back to arch calling code */ |
||||
mov pc, lr |
||||
|
||||
/* the literal pools origin */ |
||||
.ltorg |
||||
|
||||
|
||||
REG_TC_EMIFS_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc0c
|
||||
REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc10
|
||||
REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc14
|
||||
REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc18
|
||||
REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc1c
|
||||
|
||||
/* MPU clock/reset/power mode control registers */ |
||||
REG_ARM_CKCTL: /* 16 bits */ |
||||
.word 0xfffece00
|
||||
|
||||
REG_ARM_IDLECT3: /* 16 bits */ |
||||
.word 0xfffece24
|
||||
REG_ARM_IDLECT2: /* 16 bits */ |
||||
.word 0xfffece08
|
||||
REG_ARM_IDLECT1: /* 16 bits */ |
||||
.word 0xfffece04
|
||||
|
||||
REG_ARM_RSTCT2: /* 16 bits */ |
||||
.word 0xfffece14
|
||||
REG_ARM_SYSST: /* 16 bits */ |
||||
.word 0xfffece18
|
||||
/* DPLL control registers */ |
||||
REG_DPLL1_CTL: /* 16 bits */ |
||||
.word 0xfffecf00
|
||||
|
||||
/* Watch Dog register */ |
||||
/* secure watchdog stop */ |
||||
REG_WSPRDOG: |
||||
.word 0xfffeb048
|
||||
/* watchdog write pending */ |
||||
REG_WWPSDOG: |
||||
.word 0xfffeb034 |
||||
|
||||
WSPRDOG_VAL1: |
||||
.word 0x0000aaaa
|
||||
WSPRDOG_VAL2: |
||||
.word 0x00005555
|
||||
|
||||
/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, |
||||
counter @8192 rows, 10 ns, 8 burst */
|
||||
REG_SDRAM_CONFIG: |
||||
.word 0xfffecc20
|
||||
|
||||
/* Operation register */ |
||||
REG_SDRAM_OPERATION: |
||||
.word 0xfffecc80
|
||||
|
||||
/* Manual command register */ |
||||
REG_SDRAM_MANUAL_CMD: |
||||
.word 0xfffecc84
|
||||
|
||||
/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ |
||||
REG_SDRAM_MRS: |
||||
.word 0xfffecc70
|
||||
|
||||
/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ |
||||
REG_SDRAM_EMRS1: |
||||
.word 0xfffecc78
|
||||
|
||||
/* WRT DLL register */ |
||||
REG_DLL_WRT_CONTROL: |
||||
.word 0xfffecc68
|
||||
DLL_WRT_CONTROL_VAL: |
||||
.word 0x03f00002
|
||||
|
||||
/* URD DLL register */ |
||||
REG_DLL_URD_CONTROL: |
||||
.word 0xfffeccc0
|
||||
DLL_URD_CONTROL_VAL: |
||||
.word 0x00800002
|
||||
|
||||
/* LRD DLL register */ |
||||
REG_DLL_LRD_CONTROL: |
||||
.word 0xfffecccc
|
||||
|
||||
REG_WATCHDOG: |
||||
.word 0xfffec808
|
||||
|
||||
/* 96 MHz Samsung Mobile DDR */ |
||||
SDRAM_CONFIG_VAL: |
||||
.word 0x001200f4 |
||||
|
||||
DLL_LRD_CONTROL_VAL: |
||||
.word 0x00800002
|
||||
|
||||
VAL_ARM_CKCTL: |
||||
.word 0x3000
|
||||
VAL_DPLL1_CTL: |
||||
.word 0x2830
|
||||
|
||||
VAL_TC_EMIFS_CS0_CONFIG: |
||||
.word 0x002130b0
|
||||
VAL_TC_EMIFS_CS1_CONFIG: |
||||
.word 0x00001131
|
||||
VAL_TC_EMIFS_CS2_CONFIG: |
||||
.word 0x000055f0
|
||||
VAL_TC_EMIFS_CS3_CONFIG: |
||||
.word 0x88011131
|
||||
VAL_TC_EMIFF_SDRAM_CONFIG: |
||||
.word 0x010290fc
|
||||
VAL_TC_EMIFF_MRS: |
||||
.word 0x00000027
|
||||
|
||||
VAL_ARM_IDLECT1: |
||||
.word 0x00000400
|
||||
|
||||
VAL_ARM_IDLECT2: |
||||
.word 0x00000886
|
||||
VAL_ARM_IDLECT3: |
||||
.word 0x00000015
|
||||
|
||||
WATCHDOG_VAL1: |
||||
.word 0x000000f5
|
||||
WATCHDOG_VAL2: |
||||
.word 0x000000a0
|
||||
|
||||
/* command values */ |
||||
.equ CMD_SDRAM_NOP, 0x00000000 |
||||
.equ CMD_SDRAM_PRECHARGE, 0x00000001 |
||||
.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 |
||||
.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 |
||||
@ -0,0 +1,51 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm926ejs/start.o (.text) |
||||
*(.text) |
||||
} |
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
armboot_end_data = .; |
||||
. = ALIGN(4); |
||||
.bss : { *(.bss) } |
||||
armboot_end = .; |
||||
} |
||||
@ -0,0 +1,43 @@ |
||||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(CPU).a
|
||||
|
||||
START = start.o
|
||||
OBJS = interrupts.o cpu.o
|
||||
|
||||
all: .depend $(START) $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,27 @@ |
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
|
||||
-mshort-load-bytes -msoft-float
|
||||
|
||||
PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
|
||||
@ -0,0 +1,159 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* CPU specific code |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <arm926ejs.h> |
||||
|
||||
/* read co-processor 15, register #1 (control register) */ |
||||
static unsigned long read_p15_c1 (void) |
||||
{ |
||||
unsigned long value; |
||||
|
||||
__asm__ __volatile__( |
||||
"mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" |
||||
: "=r" (value) |
||||
: |
||||
: "memory"); |
||||
|
||||
#ifdef MMU_DEBUG |
||||
printf ("p15/c1 is = %08lx\n", value); |
||||
#endif |
||||
return value; |
||||
} |
||||
|
||||
/* write to co-processor 15, register #1 (control register) */ |
||||
static void write_p15_c1 (unsigned long value) |
||||
{ |
||||
#ifdef MMU_DEBUG |
||||
printf ("write %08lx to p15/c1\n", value); |
||||
#endif |
||||
__asm__ __volatile__( |
||||
"mcr p15, 0, %0, c1, c0, 0 @ write it back\n" |
||||
: |
||||
: "r" (value) |
||||
: "memory"); |
||||
|
||||
read_p15_c1 (); |
||||
} |
||||
|
||||
static void cp_delay (void) |
||||
{ |
||||
volatile int i; |
||||
|
||||
/* Many OMAP regs need at least 2 nops */ |
||||
for (i = 0; i < 100; i++); |
||||
} |
||||
|
||||
/* See also ARM Ref. Man. */ |
||||
#define C1_MMU (1<<0) /* mmu off/on */ |
||||
#define C1_ALIGN (1<<1) /* alignment faults off/on */ |
||||
#define C1_DC (1<<2) /* dcache off/on */ |
||||
#define C1_WB (1<<3) /* merging write buffer on/off */ |
||||
#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ |
||||
#define C1_SYS_PROT (1<<8) /* system protection */ |
||||
#define C1_ROM_PROT (1<<9) /* ROM protection */ |
||||
#define C1_IC (1<<12) /* icache off/on */ |
||||
#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ |
||||
#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ |
||||
|
||||
int cpu_init (void) |
||||
{ |
||||
/*
|
||||
* setup up stack if necessary |
||||
*/ |
||||
#ifdef CONFIG_USE_IRQ |
||||
IRQ_STACK_START = _armboot_end + |
||||
CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4; |
||||
FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ; |
||||
_armboot_real_end = FIQ_STACK_START + 4; |
||||
#else |
||||
_armboot_real_end = _armboot_end + CONFIG_STACKSIZE; |
||||
#endif /* CONFIG_USE_IRQ */ |
||||
return (0); |
||||
} |
||||
|
||||
int cleanup_before_linux (void) |
||||
{ |
||||
/*
|
||||
* this function is called just before we call linux |
||||
* it prepares the processor for linux |
||||
* |
||||
* we turn off caches etc ... |
||||
*/ |
||||
|
||||
unsigned long i; |
||||
|
||||
disable_interrupts (); |
||||
|
||||
/* turn off I/D-cache */ |
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); |
||||
i &= ~(C1_DC | C1_IC); |
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); |
||||
|
||||
/* flush I/D-cache */ |
||||
i = 0; |
||||
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); |
||||
return (0); |
||||
} |
||||
|
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
extern void reset_cpu (ulong addr); |
||||
|
||||
disable_interrupts (); |
||||
reset_cpu (0); |
||||
/*NOTREACHED*/ |
||||
return (0); |
||||
} |
||||
|
||||
void icache_enable (void) |
||||
{ |
||||
ulong reg; |
||||
|
||||
reg = read_p15_c1 (); /* get control reg. */ |
||||
cp_delay (); |
||||
write_p15_c1 (reg | C1_IC); |
||||
} |
||||
|
||||
void icache_disable (void) |
||||
{ |
||||
ulong reg; |
||||
|
||||
reg = read_p15_c1 (); |
||||
cp_delay (); |
||||
write_p15_c1 (reg & ~C1_IC); |
||||
} |
||||
|
||||
int icache_status (void) |
||||
{ |
||||
return (read_p15_c1 () & C1_IC) != 0; |
||||
} |
||||
@ -0,0 +1,293 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <arm925t.h> |
||||
#include <configs/omap1510.h> |
||||
|
||||
#include <asm/proc-armv/ptrace.h> |
||||
|
||||
extern void reset_cpu(ulong addr); |
||||
#define TIMER_LOAD_VAL 0xffffffff |
||||
|
||||
/* macro to read the 32 bit timer */ |
||||
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8)) |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
/* enable IRQ interrupts */ |
||||
void enable_interrupts (void) |
||||
{ |
||||
unsigned long temp; |
||||
__asm__ __volatile__("mrs %0, cpsr\n" |
||||
"bic %0, %0, #0x80\n" |
||||
"msr cpsr_c, %0" |
||||
: "=r" (temp) |
||||
: "memory"); |
||||
} |
||||
|
||||
/*
|
||||
* disable IRQ/FIQ interrupts |
||||
* returns true if interrupts had been enabled before we disabled them |
||||
*/ |
||||
int disable_interrupts (void) |
||||
{ |
||||
unsigned long old,temp; |
||||
__asm__ __volatile__("mrs %0, cpsr\n" |
||||
"orr %1, %0, #0xc0\n" |
||||
"msr cpsr_c, %1" |
||||
: "=r" (old), "=r" (temp) |
||||
: "memory"); |
||||
return (old & 0x80) == 0; |
||||
} |
||||
#else |
||||
void enable_interrupts (void) |
||||
{ |
||||
return; |
||||
} |
||||
int disable_interrupts (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
|
||||
|
||||
void bad_mode (void) |
||||
{ |
||||
panic ("Resetting CPU ...\n"); |
||||
reset_cpu (0); |
||||
} |
||||
|
||||
void show_regs (struct pt_regs *regs) |
||||
{ |
||||
unsigned long flags; |
||||
const char *processor_modes[] = { |
||||
"USER_26", "FIQ_26", "IRQ_26", "SVC_26", |
||||
"UK4_26", "UK5_26", "UK6_26", "UK7_26", |
||||
"UK8_26", "UK9_26", "UK10_26", "UK11_26", |
||||
"UK12_26", "UK13_26", "UK14_26", "UK15_26", |
||||
"USER_32", "FIQ_32", "IRQ_32", "SVC_32", |
||||
"UK4_32", "UK5_32", "UK6_32", "ABT_32", |
||||
"UK8_32", "UK9_32", "UK10_32", "UND_32", |
||||
"UK12_32", "UK13_32", "UK14_32", "SYS_32", |
||||
}; |
||||
|
||||
flags = condition_codes (regs); |
||||
|
||||
printf ("pc : [<%08lx>] lr : [<%08lx>]\n" |
||||
"sp : %08lx ip : %08lx fp : %08lx\n", |
||||
instruction_pointer (regs), |
||||
regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); |
||||
printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", |
||||
regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); |
||||
printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", |
||||
regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); |
||||
printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", |
||||
regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); |
||||
printf ("Flags: %c%c%c%c", |
||||
flags & CC_N_BIT ? 'N' : 'n', |
||||
flags & CC_Z_BIT ? 'Z' : 'z', |
||||
flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); |
||||
printf (" IRQs %s FIQs %s Mode %s%s\n", |
||||
interrupts_enabled (regs) ? "on" : "off", |
||||
fast_interrupts_enabled (regs) ? "on" : "off", |
||||
processor_modes[processor_mode (regs)], |
||||
thumb_mode (regs) ? " (T)" : ""); |
||||
} |
||||
|
||||
void do_undefined_instruction (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("undefined instruction\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_software_interrupt (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("software interrupt\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_prefetch_abort (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("prefetch abort\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_data_abort (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("data abort\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_not_used (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("not used\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_fiq (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("fast interrupt request\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_irq (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("interrupt request\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
static ulong timestamp; |
||||
static ulong lastdec; |
||||
|
||||
/* nothing really to do with interrupts, just starts up a counter. */ |
||||
int interrupt_init (void) |
||||
{ |
||||
int32_t val; |
||||
|
||||
*((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; |
||||
val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | |
||||
(CFG_PVT << MPUTIM_PTV_BIT); |
||||
*((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val; |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* timer without interrupts |
||||
*/ |
||||
|
||||
void reset_timer (void) |
||||
{ |
||||
reset_timer_masked (); |
||||
} |
||||
|
||||
ulong get_timer (ulong base) |
||||
{ |
||||
return get_timer_masked () - base; |
||||
} |
||||
|
||||
void set_timer (ulong t) |
||||
{ |
||||
timestamp = t; |
||||
} |
||||
|
||||
/* very rough timer... */ |
||||
void udelay (unsigned long usec) |
||||
{ |
||||
#ifdef CONFIG_INNOVATOROMAP1610 |
||||
#define LOOPS_PER_MSEC 100 /* tuned on omap1610 */ |
||||
volatile int i, time_remaining = LOOPS_PER_MSEC * usec; |
||||
|
||||
for (i = time_remaining; i > 0; i--) { |
||||
} |
||||
#else |
||||
|
||||
ulong tmo; |
||||
tmo = usec / 1000; |
||||
tmo *= CFG_HZ; |
||||
tmo /= 1000; |
||||
tmo += get_timer (0); |
||||
while (get_timer_masked () < tmo) |
||||
/*NOP*/; |
||||
#endif |
||||
} |
||||
|
||||
void reset_timer_masked (void) |
||||
{ |
||||
/* reset time */ |
||||
lastdec = READ_TIMER; |
||||
timestamp = 0; |
||||
} |
||||
|
||||
ulong get_timer_masked (void) |
||||
{ |
||||
ulong now = READ_TIMER; /* current tick value */ |
||||
|
||||
if (lastdec >= now) { /* did I roll (rem decrementer) */ |
||||
/* normal mode */ |
||||
/* record amount of time since last check */ |
||||
timestamp += lastdec - now; |
||||
} else { |
||||
/* we have an overflow ... */ |
||||
timestamp += lastdec + TIMER_LOAD_VAL - now; |
||||
} |
||||
lastdec = now; |
||||
|
||||
return timestamp; |
||||
} |
||||
|
||||
void udelay_masked (unsigned long usec) |
||||
{ |
||||
#ifdef CONFIG_INNOVATOROMAP1610 |
||||
#define LOOPS_PER_MSEC 100 /* tuned on omap1610 */ |
||||
volatile int i, time_remaining = LOOPS_PER_MSEC*usec; |
||||
for (i=time_remaining; i>0; i--) { } |
||||
#else |
||||
|
||||
ulong tmo; |
||||
|
||||
tmo = usec / 1000; |
||||
tmo *= CFG_HZ; |
||||
tmo /= 1000; |
||||
|
||||
reset_timer_masked (); |
||||
|
||||
while (get_timer_masked () < tmo) |
||||
/*NOP*/; |
||||
#endif |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long). |
||||
* On ARM it just returns the timer value. |
||||
*/ |
||||
unsigned long long get_ticks(void) |
||||
{ |
||||
return get_timer(0); |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency). |
||||
* On ARM it returns the number of timer ticks per second. |
||||
*/ |
||||
ulong get_tbclk (void) |
||||
{ |
||||
ulong tbclk; |
||||
tbclk = CFG_HZ; |
||||
return tbclk; |
||||
} |
||||
@ -0,0 +1,426 @@ |
||||
/* |
||||
* armboot - Startup Code for ARM926EJS CPU-core |
||||
* |
||||
* Copyright (c) 2003 Texas Instruments |
||||
* |
||||
* ----- Adapted for OMAP1610 from ARM925t code ------ |
||||
* |
||||
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
|
||||
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
|
||||
* Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
|
||||
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
#if defined(CONFIG_OMAP1610) |
||||
#include <./configs/omap1510.h> |
||||
#endif |
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* Jump vector table as in table 3.1 in [1] |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
|
||||
.globl _start
|
||||
_start: |
||||
b reset |
||||
ldr pc, _undefined_instruction |
||||
ldr pc, _software_interrupt |
||||
ldr pc, _prefetch_abort |
||||
ldr pc, _data_abort |
||||
ldr pc, _not_used |
||||
ldr pc, _irq |
||||
ldr pc, _fiq |
||||
|
||||
_undefined_instruction: |
||||
.word undefined_instruction
|
||||
_software_interrupt: |
||||
.word software_interrupt
|
||||
_prefetch_abort: |
||||
.word prefetch_abort
|
||||
_data_abort: |
||||
.word data_abort
|
||||
_not_used: |
||||
.word not_used
|
||||
_irq: |
||||
.word irq
|
||||
_fiq: |
||||
.word fiq
|
||||
|
||||
.balignl 16,0xdeadbeef |
||||
|
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* Startup Code (reset vector) |
||||
* |
||||
* do important init only if we don't start from memory! |
||||
* setup Memory and board specific bits prior to relocation. |
||||
* relocate armboot to ram |
||||
* setup stack |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
/* |
||||
* CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h) |
||||
*/ |
||||
_TEXT_BASE: |
||||
.word TEXT_BASE
|
||||
|
||||
.globl _armboot_start
|
||||
_armboot_start: |
||||
.word _start
|
||||
|
||||
/* |
||||
* Note: _armboot_end_data and _armboot_end are defined |
||||
* by the (board-dependent) linker script. |
||||
* _armboot_end_data is the first usable FLASH address after armboot |
||||
*/ |
||||
.globl _armboot_end_data
|
||||
_armboot_end_data: |
||||
.word armboot_end_data
|
||||
.globl _armboot_end
|
||||
_armboot_end: |
||||
.word armboot_end
|
||||
|
||||
/* |
||||
* _armboot_real_end is the first usable RAM address behind armboot |
||||
* and the various stacks |
||||
*/ |
||||
.globl _armboot_real_end
|
||||
_armboot_real_end: |
||||
.word 0x0badc0de
|
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
/* IRQ stack memory (calculated at run-time) */ |
||||
.globl IRQ_STACK_START
|
||||
IRQ_STACK_START: |
||||
.word 0x0badc0de
|
||||
|
||||
/* IRQ stack memory (calculated at run-time) */ |
||||
.globl FIQ_STACK_START
|
||||
FIQ_STACK_START: |
||||
.word 0x0badc0de
|
||||
#endif |
||||
|
||||
|
||||
/* |
||||
* the actual reset code |
||||
*/ |
||||
|
||||
reset: |
||||
/* |
||||
* set the cpu to SVC32 mode |
||||
*/ |
||||
mrs r0,cpsr |
||||
bic r0,r0,#0x1f |
||||
orr r0,r0,#0xd3 |
||||
msr cpsr,r0 |
||||
|
||||
|
||||
/*
|
||||
* turn off the watchdog, unlock/diable sequence |
||||
*/ |
||||
mov r1, #0xF5 |
||||
ldr r0, =WDTIM_MODE |
||||
strh r1, [r0] |
||||
mov r1, #0xA0 |
||||
strh r1, [r0] |
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* |
||||
* mask all IRQs by setting all bits in the INTMR - default |
||||
*/ |
||||
|
||||
mov r1, #0xffffffff |
||||
ldr r0, =REG_IHL1_MIR |
||||
str r1, [r0] |
||||
ldr r0, =REG_IHL2_MIR |
||||
str r1, [r0] |
||||
bl cpu_init_crit |
||||
|
||||
relocate: |
||||
/* |
||||
* relocate armboot to RAM |
||||
*/ |
||||
adr r0, _start /* r0 <- current position of code */ |
||||
ldr r2, _armboot_start |
||||
ldr r3, _armboot_end |
||||
sub r2, r3, r2 /* r2 <- size of armboot */ |
||||
ldr r1, _TEXT_BASE /* r1 <- destination address */ |
||||
add r2, r0, r2 /* r2 <- source end address */ |
||||
|
||||
/* |
||||
* r0 = source address |
||||
* r1 = target address |
||||
* r2 = source end address |
||||
*/ |
||||
copy_loop: |
||||
ldmia r0!, {r3-r10} |
||||
stmia r1!, {r3-r10} |
||||
cmp r0, r2 |
||||
ble copy_loop |
||||
|
||||
/* set up the stack */ |
||||
ldr r0, _armboot_end |
||||
add r0, r0, #CONFIG_STACKSIZE |
||||
sub sp, r0, #12 /* leave 3 words for abort-stack */ |
||||
|
||||
ldr pc, _start_armboot |
||||
|
||||
_start_armboot: |
||||
.word start_armboot
|
||||
|
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* CPU_init_critical registers |
||||
* |
||||
* setup important registers |
||||
* setup memory timing |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
|
||||
cpu_init_crit: |
||||
/* |
||||
* flush v4 I/D caches |
||||
*/ |
||||
mov r0, #0 |
||||
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
||||
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
||||
|
||||
/* |
||||
* disable MMU stuff and caches |
||||
*/ |
||||
mrc p15, 0, r0, c1, c0, 0 |
||||
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ |
||||
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ |
||||
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ |
||||
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ |
||||
mcr p15, 0, r0, c1, c0, 0 |
||||
|
||||
/* |
||||
* Go setup Memory and board specific bits prior to relocation. |
||||
*/ |
||||
mov ip, lr /* perserve link reg across call */ |
||||
bl platformsetup /* go setup pll,mux,memory */ |
||||
mov lr, ip /* restore link */ |
||||
mov pc, lr /* back to my caller */ |
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* Interrupt handling |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
@
|
||||
@ IRQ stack frame.
|
||||
@
|
||||
#define S_FRAME_SIZE 72 |
||||
|
||||
#define S_OLD_R0 68 |
||||
#define S_PSR 64 |
||||
#define S_PC 60 |
||||
#define S_LR 56 |
||||
#define S_SP 52 |
||||
|
||||
#define S_IP 48 |
||||
#define S_FP 44 |
||||
#define S_R10 40 |
||||
#define S_R9 36 |
||||
#define S_R8 32 |
||||
#define S_R7 28 |
||||
#define S_R6 24 |
||||
#define S_R5 20 |
||||
#define S_R4 16 |
||||
#define S_R3 12 |
||||
#define S_R2 8 |
||||
#define S_R1 4 |
||||
#define S_R0 0 |
||||
|
||||
#define MODE_SVC 0x13 |
||||
#define I_BIT 0x80 |
||||
|
||||
/* |
||||
* use bad_save_user_regs for abort/prefetch/undef/swi ... |
||||
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling |
||||
*/ |
||||
|
||||
.macro bad_save_user_regs
|
||||
@ carve out a frame on current user stack
|
||||
sub sp, sp, #S_FRAME_SIZE |
||||
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
||||
ldr r2, _armboot_end @ find top of stack
|
||||
add r2, r2, #CONFIG_STACKSIZE @ find base of normal stack |
||||
sub r2, r2, #8 @ set base 2 words into abort stack
|
||||
@ get values for "aborted" pc and cpsr (into parm regs)
|
||||
ldmia r2, {r2 - r3} |
||||
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack |
||||
add r5, sp, #S_SP |
||||
mov r1, lr |
||||
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
|
||||
mov r0, sp @ save current stack into r0 (param register)
|
||||
.endm |
||||
|
||||
.macro irq_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE |
||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||
@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
|
||||
add r8, sp, #S_PC |
||||
stmdb r8, {sp, lr}^ @ Calling SP, LR
|
||||
str lr, [r8, #0] @ Save calling PC
|
||||
mrs r6, spsr |
||||
str r6, [r8, #4] @ Save CPSR
|
||||
str r0, [r8, #8] @ Save OLD_R0
|
||||
mov r0, sp |
||||
.endm |
||||
|
||||
.macro irq_restore_user_regs
|
||||
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
|
||||
mov r0, r0 |
||||
ldr lr, [sp, #S_PC] @ Get PC |
||||
add sp, sp, #S_FRAME_SIZE |
||||
subs pc, lr, #4 @ return & move spsr_svc into cpsr
|
||||
.endm |
||||
|
||||
.macro get_bad_stack
|
||||
@ get bottom of stack (into sp by by user stack pointer).
|
||||
ldr r13, _armboot_end |
||||
@ head to reserved words at the top of the stack
|
||||
add r13, r13, #CONFIG_STACKSIZE |
||||
sub r13, r13, #8 @ reserved a couple spots in abort stack
|
||||
|
||||
str lr, [r13] @ save caller lr in position 0 of saved stack
|
||||
mrs lr, spsr @ get the spsr
|
||||
str lr, [r13, #4] @ save spsr in position 1 of saved stack
|
||||
mov r13, #MODE_SVC @ prepare SVC-Mode |
||||
@ msr spsr_c, r13
|
||||
msr spsr, r13 @ switch modes, make sure moves will execute
|
||||
mov lr, pc @ capture return pc
|
||||
movs pc, lr @ jump to next instruction & switch modes.
|
||||
.endm |
||||
|
||||
.macro get_irq_stack @ setup IRQ stack
|
||||
ldr sp, IRQ_STACK_START |
||||
.endm |
||||
|
||||
.macro get_fiq_stack @ setup FIQ stack
|
||||
ldr sp, FIQ_STACK_START |
||||
.endm |
||||
|
||||
/* |
||||
* exception handlers |
||||
*/ |
||||
.align 5
|
||||
undefined_instruction: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_undefined_instruction |
||||
|
||||
.align 5
|
||||
software_interrupt: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_software_interrupt |
||||
|
||||
.align 5
|
||||
prefetch_abort: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_prefetch_abort |
||||
|
||||
.align 5
|
||||
data_abort: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_data_abort |
||||
|
||||
.align 5
|
||||
not_used: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_not_used |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
|
||||
.align 5
|
||||
irq: |
||||
get_irq_stack |
||||
irq_save_user_regs |
||||
bl do_irq |
||||
irq_restore_user_regs |
||||
|
||||
.align 5
|
||||
fiq: |
||||
get_fiq_stack |
||||
/* someone ought to write a more effiction fiq_save_user_regs */ |
||||
irq_save_user_regs |
||||
bl do_fiq |
||||
irq_restore_user_regs |
||||
|
||||
#else |
||||
|
||||
.align 5
|
||||
irq: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_irq |
||||
|
||||
.align 5
|
||||
fiq: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_fiq |
||||
|
||||
#endif |
||||
|
||||
.align 5
|
||||
.globl reset_cpu
|
||||
reset_cpu: |
||||
ldr r1, rstctl1 /* get clkm1 reset ctl */ |
||||
mov r3, #0x0
|
||||
strh r3, [r1] /* clear it */ |
||||
mov r3, #0x8 |
||||
strh r3, [r1] /* force dsp+arm reset */ |
||||
_loop_forever: |
||||
b _loop_forever |
||||
|
||||
|
||||
rstctl1: |
||||
.word 0xfffece10
|
||||
@ -0,0 +1,8 @@ |
||||
/************************************************
|
||||
* NAME arm926ejs.h * |
||||
* Version : 23 June 2003 * |
||||
************************************************/ |
||||
/* Currently empty */ |
||||
#ifndef __ARM926EJS_H__ |
||||
#define __ARM926EJS_H__ |
||||
#endif /*__ARM926EJS_H__*/ |
||||
@ -0,0 +1,51 @@ |
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307 |
||||
* USA |
||||
*/ |
||||
/* DO NOT EDIT!! - this file automatically generated
|
||||
* from .s file by awk -f s2h.awk |
||||
*/ |
||||
/* Size defintions
|
||||
* Copyright (C) ARM Limited 1998. All rights reserved. |
||||
*/ |
||||
|
||||
#ifndef __sizes_h |
||||
#define __sizes_h 1 |
||||
|
||||
/* handy sizes */ |
||||
#define SZ_1K 0x00000400 |
||||
#define SZ_4K 0x00001000 |
||||
#define SZ_8K 0x00002000 |
||||
#define SZ_16K 0x00004000 |
||||
#define SZ_64K 0x00010000 |
||||
#define SZ_128K 0x00020000 |
||||
#define SZ_256K 0x00040000 |
||||
#define SZ_512K 0x00080000 |
||||
|
||||
#define SZ_1M 0x00100000 |
||||
#define SZ_2M 0x00200000 |
||||
#define SZ_4M 0x00400000 |
||||
#define SZ_8M 0x00800000 |
||||
#define SZ_16M 0x01000000 |
||||
#define SZ_32M 0x02000000 |
||||
#define SZ_64M 0x04000000 |
||||
#define SZ_128M 0x08000000 |
||||
#define SZ_256M 0x10000000 |
||||
#define SZ_512M 0x20000000 |
||||
|
||||
#define SZ_1G 0x40000000 |
||||
#define SZ_2G 0x80000000 |
||||
|
||||
#endif /* __sizes_h */ |
||||
@ -0,0 +1,169 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Texas Instruments. |
||||
* Kshitij Gupta <kshitij@ti.com> |
||||
* Configuation settings for the TI OMAP Innovator board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ |
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
||||
#define CONFIG_OMAP1610 1 /* which is in a 1610 */ |
||||
#define CONFIG_INNOVATOROMAP1610 1 /* a Innovator Board */ |
||||
|
||||
/* input clock of PLL */ |
||||
/* the OMAP1610 Innovator has 12MHz input clock */ |
||||
#define CONFIG_SYS_CLK_FREQ 12000000 |
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
/*
|
||||
*/ |
||||
#define CONFIG_DRIVER_LAN91C96 |
||||
#define CONFIG_LAN91C96_BASE 0x04000300 |
||||
#define CONFIG_LAN91C96_EXT_PHY |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE (-4) |
||||
#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ |
||||
#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart |
||||
on helen */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 Innovator */ |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) |
||||
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
#include <configs/omap1510.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ |
||||
root=/dev/nfs rw nfsroot=157.87.82.48:\
|
||||
/home/a0875451/mwd/myfs/target ip=dhcp" |
||||
#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ |
||||
#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ |
||||
#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ |
||||
#define CONFIG_BOOTFILE "uImage" /* file to load */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "OMAP1610 Innovator # " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
/* Print Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ |
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x10000000 /* default load address */ |
||||
|
||||
/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
|
||||
* DPLL1. This time is further subdivided by a local divisor. |
||||
*/ |
||||
#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ |
||||
#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ |
||||
#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ |
||||
#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ |
||||
/* addr of environment */ |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) |
||||
|
||||
/* timeout values are in ticks */ |
||||
#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
||||
#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue