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Add Vibren (was Accelent) PXA255 IDP Support

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Patch by Cliff Brake, 04 Feb 2005
master
Wolfgang Denk 20 years ago
parent 2df741bf7c
commit 70a2047ff6
10 changed files with 1567 additions and 0 deletions
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  1. 48
      board/pxa255_idp/Makefile
  2. 11
      board/pxa255_idp/README
  3. 3
      board/pxa255_idp/config.mk
  4. 46
      board/pxa255_idp/idp_notes.txt
  5. 496
      board/pxa255_idp/memsetup.S
  6. 140
      board/pxa255_idp/pxa_idp.c
  7. 119
      board/pxa255_idp/pxa_reg_calcs.out
  8. 311
      board/pxa255_idp/pxa_reg_calcs.py
  9. 55
      board/pxa255_idp/u-boot.lds
  10. 338
      include/configs/pxa255_idp.h

48
board/pxa255_idp/Makefile
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#
# (C) Copyright 2000-2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := pxa_idp.o
SOBJS := memsetup.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

11
board/pxa255_idp/README
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Tested:
- MMC
- Ethernet
- BL console (on serial port connector J5)
- flash support
Todo:
- display support
- PCMCIA support

3
board/pxa255_idp/config.mk
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#TEXT_BASE = 0xa1700000
TEXT_BASE = 0xa3000000
#TEXT_BASE = 0

46
board/pxa255_idp/idp_notes.txt
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Notes on the Vibren PXA255 IDP.
Chip select usage:
CS0 - flash
CS1 - alt flash (Mdoc or main flash)
CS2 - high speed expansion bus
CS3 - Media Q, low speed exp bus
CS4 - low speed exp bus
CS5 - low speed exp bus
- IDE: offset 0x03000000 (abs: 0x17000000)
- Eth: offset 0x03400000 (abs: 0x17400000)
- core voltage latch: offset 0x03800000 (abs: 0x17800000)
- CPLD: offset 0x03C00000 (abs: 0x17C00000)
PCMCIA Power control
MAX1602EE w/ code pulled high (Cirrus code)
vx = 5v
vy = 3v
Bit pattern
PWR 3,2,1,0
vcc vpp A1VCC A0VCC A1VPP A0VPP
=====================================================
0 0 0 0 0 0 0x0
3 (vy) 0 1 0 1 1 0xB
3 (vy) 3 (vy) 1 0 0 1 0x9
3 (vy) 12(12in) 1 0 1 0 0xA
5 (vx) 0 0 1 1 1 0x7
5 (vx) 5 (vx) 0 1 0 1 0x5
5 (vx 12(12in) 0 1 1 0 0x6
Display power sequencing:
- VDD applied
- within 1sec, activate scanning signals
- wait at least 50mS - scanning signals must be active before activating DISP
Signal mapping:
Schematic LV8V31 signal name
=========================================
LCD_ENAVLCD DISP
LCD_PWR Applies VDD to board
Both of the above signals are controlled by the CPLD

496
board/pxa255_idp/memsetup.S
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/*
* Most of this taken from Redboot hal_platform_setup.h with cleanup
*
* NOTE: I haven't clean this up considerably, just enough to get it
* running. See hal_platform_setup.h for the source. See
* board/cradle/memsetup.S for another PXA250 setup that is
* much cleaner.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
DRAM_SIZE: .long CFG_DRAM_SIZE
/* wait for coprocessor write complete */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
/*
* Memory setup
*/
.globl memsetup
memsetup:
mov r10, lr
#ifdef DEBUG_BLINK_ENABLE
/* 3rd blink */
bl blink
#endif
/* Set up GPIO pins first ----------------------------------------- */
ldr r0, =GPSR0
ldr r1, =CFG_GPSR0_VAL
str r1, [r0]
ldr r0, =GPSR1
ldr r1, =CFG_GPSR1_VAL
str r1, [r0]
ldr r0, =GPSR2
ldr r1, =CFG_GPSR2_VAL
str r1, [r0]
ldr r0, =GPCR0
ldr r1, =CFG_GPCR0_VAL
str r1, [r0]
ldr r0, =GPCR1
ldr r1, =CFG_GPCR1_VAL
str r1, [r0]
ldr r0, =GPCR2
ldr r1, =CFG_GPCR2_VAL
str r1, [r0]
ldr r0, =GPDR0
ldr r1, =CFG_GPDR0_VAL
str r1, [r0]
ldr r0, =GPDR1
ldr r1, =CFG_GPDR1_VAL
str r1, [r0]
ldr r0, =GPDR2
ldr r1, =CFG_GPDR2_VAL
str r1, [r0]
ldr r0, =GAFR0_L
ldr r1, =CFG_GAFR0_L_VAL
str r1, [r0]
ldr r0, =GAFR0_U
ldr r1, =CFG_GAFR0_U_VAL
str r1, [r0]
ldr r0, =GAFR1_L
ldr r1, =CFG_GAFR1_L_VAL
str r1, [r0]
ldr r0, =GAFR1_U
ldr r1, =CFG_GAFR1_U_VAL
str r1, [r0]
ldr r0, =GAFR2_L
ldr r1, =CFG_GAFR2_L_VAL
str r1, [r0]
ldr r0, =GAFR2_U
ldr r1, =CFG_GAFR2_U_VAL
str r1, [r0]
ldr r0, =PSSR /* enable GPIO pins */
ldr r1, =CFG_PSSR_VAL
str r1, [r0]
#ifdef DEBUG_BLINK_ENABLE
/* 4th debug blink */
bl blink
#endif
/* ---------------------------------------------------------------- */
/* Enable memory interface */
/* */
/* The sequence below is based on the recommended init steps */
/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
/* Chapter 10. */
/* ---------------------------------------------------------------- */
/* ---------------------------------------------------------------- */
/* Step 1: Wait for at least 200 microsedonds to allow internal */
/* clocks to settle. Only necessary after hard reset... */
/* FIXME: can be optimized later */
/* ---------------------------------------------------------------- */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
/* so 0x300 should be plenty */
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
mem_init:
ldr r1, =MEMC_BASE /* get memory controller base addr. */
/* ---------------------------------------------------------------- */
/* Step 2a: Initialize Asynchronous static memory controller */
/* ---------------------------------------------------------------- */
/* MSC registers: timing, bus width, mem type */
/* MSC0: nCS(0,1) */
ldr r2, =CFG_MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
/* that data latches */
/* MSC1: nCS(2,3) */
ldr r2, =CFG_MSC1_VAL
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
ldr r2, =CFG_MSC2_VAL
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2b: Initialize Card Interface */
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
ldr r2, =CFG_MECR_VAL
str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
ldr r2, =CFG_MCMEM0_VAL
str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
/* MCMEM1: Card Interface slot 1 timing */
ldr r2, =CFG_MCMEM1_VAL
str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
ldr r2, =CFG_MCATT0_VAL
str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
ldr r2, =CFG_MCATT1_VAL
str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
ldr r2, =CFG_MCIO0_VAL
str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
ldr r2, =CFG_MCIO1_VAL
str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
#ifdef DEBUG_BLINK_ENABLE
/* 5th blink */
bl blink
#endif
/* ---------------------------------------------------------------- */
/* Step 2c: Write FLYCNFG FIXME: what's that??? */
/* ---------------------------------------------------------------- */
/* ---------------------------------------------------------------- */
/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
/* ---------------------------------------------------------------- */
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field. */
ldr r3, =CFG_MDREFR_VAL
ldr r2, =0xFFF
and r3, r3, r2
ldr r4, =0x03ca4000
orr r4, r4, r3
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
/* Note: preserve the mdrefr value in r4 */
/* ---------------------------------------------------------------- */
/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
/* ---------------------------------------------------------------- */
/* Initialize SXCNFG register. Assert the enable bits */
/* Write SXMRS to cause an MRS command to all enabled banks of */
/* synchronous static memory. Note that SXLCR need not be written */
/* at this time. */
/* FIXME: we use async mode for now */
/* ---------------------------------------------------------------- */
/* Step 4: Initialize SDRAM */
/* ---------------------------------------------------------------- */
/* set MDREFR according to user define with exception of a few bits */
ldr r4, =CFG_MDREFR_VAL
orr r4, r4, #(MDREFR_SLFRSH)
bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4b: de-assert MDREFR:SLFRSH. */
bic r4, r4, #(MDREFR_SLFRSH)
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
ldr r4, =CFG_MDREFR_VAL
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
/* configure but not enable each SDRAM partition pair. */
ldr r4, =CFG_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
ldr r4, [r1, #MDCNFG_OFFSET]
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
/* 100..200 µsec. */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
/* so 0x300 should be plenty */
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
/* Step 4f: Trigger a number (usually 8) refresh cycles by */
/* attempting non-burst read or write accesses to disabled */
/* SDRAM, as commonly specified in the power up sequence */
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
ldr r3, =CFG_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
/* Step 4g: Write MDCNFG with enable bits asserted */
/* (MDCNFG:DEx set to 1). */
ldr r3, [r1, #MDCNFG_OFFSET]
orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
str r3, [r1, #MDCNFG_OFFSET]
/* Step 4h: Write MDMRS. */
ldr r2, =CFG_MDMRS_VAL
str r2, [r1, #MDMRS_OFFSET]
/* We are finished with Intel's memory controller initialisation */
#if 0
/* FIXME turn on serial ports */
/* look into moving this to board_init() */
ldr r2, =(PXA_CS5_PHYS + 0x03C0002c)
mov r3, #0x13
str r3, [r2]
#endif
#ifdef DEBUG_BLINK_ENABLE
/* 6th blink */
bl blink
#endif
/* ---------------------------------------------------------------- */
/* Disable (mask) all interrupts at interrupt controller */
/* ---------------------------------------------------------------- */
initirqs:
mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
ldr r2, =ICLR
str r1, [r2]
ldr r2, =ICMR /* mask all interrupts at the controller */
str r1, [r2]
/* ---------------------------------------------------------------- */
/* Clock initialisation */
/* ---------------------------------------------------------------- */
initclks:
/* Disable the peripheral clocks, and set the core clock frequency */
/* (hard-coding at 398.12MHz for now). */
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
/* Note: See label 'ENABLECLKS' for the re-enabling */
#if 0
ldr r1, =CKEN
mov r2, #0
str r2, [r1]
/* default value in case no valid rotary switch setting is found */
ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
/* ... and write the core clock config register */
ldr r1, =CCCR
str r2, [r1]
#endif
#ifdef RTC
/* enable the 32Khz oscillator for RTC and PowerManager */
ldr r1, =OSCC
mov r2, #OSCC_OON
str r2, [r1]
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
/* has settled. */
60:
ldr r2, [r1]
ands r2, r2, #1
beq 60b
#endif
/* ---------------------------------------------------------------- */
/* */
/* ---------------------------------------------------------------- */
/* Save SDRAM size */
ldr r1, =DRAM_SIZE
str r8, [r1]
/* Interrupt init: Mask all interrupts */
ldr r0, =ICMR /* enable no sources */
mov r1, #0
str r1, [r0]
/* FIXME */
#define NODEBUG
#ifdef NODEBUG
/*Disable software and data breakpoints */
mov r0,#0
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
mcr p15,0,r0,c14,c4,0 /* dbcon */
/*Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 /* dcsr */
#endif
/* ---------------------------------------------------------------- */
/* End memsetup */
/* ---------------------------------------------------------------- */
#ifdef DEBUG_BLINK_ENABLE
/* 7th blink */
bl blink
#endif
endmemsetup:
mov pc, r10
#ifdef DEBUG_BLINK_ENABLE
/* debug LED code */
/* delay about 200ms */
delay:
/* reset OSCR to 0 */
ldr r8, =OSCR
mov r9, #0
str r9, [r8]
/* make sure new value has stuck */
1:
ldr r8, =OSCR
ldr r9, [r8]
mov r8, #0x10000
cmp r9, r8
bgt 1b
/* now, wait for delay to expire */
1:
ldr r8, =OSCR
ldr r9, [r8]
mov r8, #0xd4000
cmp r8, r9
bgt 1b
mov pc, lr
/* blink code -- trashes r7, r8, r9 */
.globl blink
blink:
mov r7, lr
/* set GPIO10 as outout */
ldr r8, =GPDR0
ldr r9, [r8]
orr r9, r9, #(1<<10)
str r9, [r8]
/* turn LED off */
mov r9, #(1<<10)
ldr r8, =GPCR0
str r9, [r8]
bl delay
/* turn LED on */
mov r9, #(1<<10)
ldr r8, =GPSR0
str r9, [r8]
bl delay
/* turn LED off */
mov r9, #(1<<10)
ldr r8, =GPCR0
str r9, [r8]
mov pc, r7
#endif

140
board/pxa255_idp/pxa_idp.c
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/*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2004
* BEC Systems <http://bec-systems.com>
* Cliff Brake <cliff.brake@gmail.com>
* Support for Accelent/Vibren PXA255 IDP
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* arch number of Lubbock-Board */
gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
/* turn on serial ports */
*(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13;
/* set PWM for LCD */
/* a value that works is 60Hz, 77% duty cycle */
CKEN |= CKEN0_PWM0;
PWM_CTRL0 = 0x3f;
PWM_PERVAL0 = 0x3ff;
PWM_PWDUTY0 = 792;
/* clear reset to AC97 codec */
CKEN |= CKEN2_AC97;
GCR = GCR_COLD_RST;
/* enable LCD backlight */
/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
/* test display */
/* lcd_puts("This is a test\nTest #2\n"); */
return 0;
}
int board_late_init(void)
{
setenv("stdout", "serial");
setenv("stderr", "serial");
return 0;
}
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
return 0;
}
#ifdef DEBUG_BLINKC_ENABLE
void delay_c(void)
{
/* reset OSCR to 0 */
OSCR = 0;
while(OSCR > 0x10000)
;
while(OSCR < 0xd4000)
;
}
void blink_c(void)
{
int led_bit = (1<<10);
GPDR0 = led_bit;
GPCR0 = led_bit;
delay_c();
GPSR0 = led_bit;
delay_c();
GPCR0 = led_bit;
}
int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
printf("IDPCMD started\n");
return 0;
}
U_BOOT_CMD(idpcmd, CFG_MAXARGS, 0, do_idpcmd,
"idpcmd - custom IDP command\n",
"no args at this time\n"
);
#endif

119
board/pxa255_idp/pxa_reg_calcs.out
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gafr0_l: 0x80001005
gafr0_u: 0xa5128012
gafr1_l: 0x699a9558
gafr1_u: 0xaaa5aa6a
gafr2_l: 0xaaaaaaaa
gafr2_u: 0x2
gpcr0: 0x1800400
gpcr1: 0x0
gpcr2: 0x0
gpdr0: 0xc1818440
gpdr1: 0xfcffab82
gpdr2: 0x1ffff
gpsr0: 0x8000
gpsr1: 0x3f0002
gpsr2: 0x1c000
#define CFG_GAFR0_L_VAL 0x80001005
#define CFG_GAFR0_U_VAL 0xa5128012
#define CFG_GAFR1_L_VAL 0x699a9558
#define CFG_GAFR1_U_VAL 0xaaa5aa6a
#define CFG_GAFR2_L_VAL 0xaaaaaaaa
#define CFG_GAFR2_U_VAL 0x2
#define CFG_GPCR0_VAL 0x1800400
#define CFG_GPCR1_VAL 0x0
#define CFG_GPCR2_VAL 0x0
#define CFG_GPDR0_VAL 0xc1818440
#define CFG_GPDR1_VAL 0xfcffab82
#define CFG_GPDR2_VAL 0x1ffff
#define CFG_GPSR0_VAL 0x8000
#define CFG_GPSR1_VAL 0x3f0002
#define CFG_GPSR2_VAL 0x1c000
GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET#
GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET#
GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA
GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ#
GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH
GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH#
GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK
GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD#
GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD#
GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD#
GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED
GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK
GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK
GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT
GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ
GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1#
GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0
GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB
GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY
GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O#
GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0
GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI
GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O#
GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK
GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM
GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD
GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD
GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK
GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK
GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0
GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT
GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC
GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1
GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5#
GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD
GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS
GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD
GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR
GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI
GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD
GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR
GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS
GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD
GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD
GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS
GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS
GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD
GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD
GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE#
GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE#
GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR#
GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW#
GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1#
GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2#
GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL
GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG#
GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT#
GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16#
GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0
GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1
GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2
GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3
GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4
GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5
GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6
GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7
GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8
GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9
GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10
GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11
GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12
GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13
GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14
GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15
GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK
GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK
GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK
GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS
GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2#
GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3#
GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4#
GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc=
GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc=
GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc=
GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc=

311
board/pxa255_idp/pxa_reg_calcs.py
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#!/usr/bin/python
# (C) Copyright 2004
# BEC Systems <http://bec-systems.com>
# Cliff Brake <cliff.brake@gmail.com>
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
# calculations for PXA255 registers
class gpio:
dir = '0'
set = '0'
clr = '0'
alt = '0'
desc = ''
def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
self.dir = dir
self.set = set
self.clr = clr
self.alt = alt
self.desc = desc
# the following is a dictionary of all GPIOs in the system
# the key is the GPIO number
pxa255_alt_func = {
0: ['gpio', 'none', 'none', 'none'],
1: ['gpio', 'gpio reset', 'none', 'none'],
2: ['gpio', 'none', 'none', 'none'],
3: ['gpio', 'none', 'none', 'none'],
4: ['gpio', 'none', 'none', 'none'],
5: ['gpio', 'none', 'none', 'none'],
6: ['gpio', 'MMC clk', 'none', 'none'],
7: ['gpio', '48MHz clock', 'none', 'none'],
8: ['gpio', 'MMC CS0', 'none', 'none'],
9: ['gpio', 'MMC CS1', 'none', 'none'],
10: ['gpio', 'RTC Clock', 'none', 'none'],
11: ['gpio', '3.6MHz', 'none', 'none'],
12: ['gpio', '32KHz', 'none', 'none'],
13: ['gpio', 'none', 'MBGNT', 'none'],
14: ['gpio', 'MBREQ', 'none', 'none'],
15: ['gpio', 'none', 'nCS_1', 'none'],
16: ['gpio', 'none', 'PWM0', 'none'],
17: ['gpio', 'none', 'PWM1', 'none'],
18: ['gpio', 'RDY', 'none', 'none'],
19: ['gpio', 'DREQ[1]', 'none', 'none'],
20: ['gpio', 'DREQ[0]', 'none', 'none'],
21: ['gpio', 'none', 'none', 'none'],
22: ['gpio', 'none', 'none', 'none'],
23: ['gpio', 'none', 'SSP SCLK', 'none'],
24: ['gpio', 'none', 'SSP SFRM', 'none'],
25: ['gpio', 'none', 'SSP TXD', 'none'],
26: ['gpio', 'SSP RXD', 'none', 'none'],
27: ['gpio', 'SSP EXTCLK', 'none', 'none'],
28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'],
29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'],
30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'],
31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'],
32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'],
33: ['gpio', 'none', 'nCS_5', 'none'],
34: ['gpio', 'FF RXD', 'MMC CS0', 'none'],
35: ['gpio', 'FF CTS', 'none', 'none'],
36: ['gpio', 'FF DCD', 'none', 'none'],
37: ['gpio', 'FF DSR', 'none', 'none'],
38: ['gpio', 'FF RI', 'none', 'none'],
39: ['gpio', 'MMC CS1', 'FF TXD', 'none'],
40: ['gpio', 'none', 'FF DTR', 'none'],
41: ['gpio', 'none', 'FF RTS', 'none'],
42: ['gpio', 'BT RXD', 'none', 'HW RXD'],
43: ['gpio', 'none', 'BT TXD', 'HW TXD'],
44: ['gpio', 'BT CTS', 'none', 'HW CTS'],
45: ['gpio', 'none', 'BT RTS', 'HW RTS'],
46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'],
47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'],
48: ['gpio', 'HW TXD', 'nPOE', 'none'],
49: ['gpio', 'HW RXD', 'nPWE', 'none'],
50: ['gpio', 'HW CTS', 'nPIOR', 'none'],
51: ['gpio', 'nPIOW', 'HW RTS', 'none'],
52: ['gpio', 'none', 'nPCE[1]', 'none'],
53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'],
54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'],
55: ['gpio', 'none', 'nPREG', 'none'],
56: ['gpio', 'nPWAIT', 'none', 'none'],
57: ['gpio', 'nIOIS16', 'none', 'none'],
58: ['gpio', 'none', 'LDD[0]', 'none'],
59: ['gpio', 'none', 'LDD[1]', 'none'],
60: ['gpio', 'none', 'LDD[2]', 'none'],
61: ['gpio', 'none', 'LDD[3]', 'none'],
62: ['gpio', 'none', 'LDD[4]', 'none'],
63: ['gpio', 'none', 'LDD[5]', 'none'],
64: ['gpio', 'none', 'LDD[6]', 'none'],
65: ['gpio', 'none', 'LDD[7]', 'none'],
66: ['gpio', 'MBREQ', 'LDD[8]', 'none'],
67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'],
68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'],
69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'],
70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'],
71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'],
72: ['gpio', '32 KHz', 'LDD[14]', 'none'],
73: ['gpio', 'MBGNT', 'LDD[15]', 'none'],
74: ['gpio', 'none', 'LCD_FCLK', 'none'],
75: ['gpio', 'none', 'LCD_LCLK', 'none'],
76: ['gpio', 'none', 'LCD_PCLK', 'none'],
77: ['gpio', 'none', 'LCD_ACBIAS', 'none'],
78: ['gpio', 'none', 'nCS_2', 'none'],
79: ['gpio', 'none', 'nCS_3', 'none'],
80: ['gpio', 'none', 'nCS_4', 'none'],
81: ['gpio', 'NSSPSCLK', 'none', 'none'],
82: ['gpio', 'NSSPSFRM', 'none', 'none'],
83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
}
#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
gpio_list = []
for i in range(0,85):
gpio_list.append(gpio())
#chip select GPIOs
gpio_list[18] = gpio(0, 0, 0, 1, 'RDY')
gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#')
gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#')
gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#')
gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#')
gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#')
gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#')
gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI')
gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#')
gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB')
gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0')
# PCMCIA stuff
gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#')
gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#')
gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#')
gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL')
gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#')
gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#')
gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#')
gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#')
gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#')
gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#')
# SSP port
gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD')
gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD')
gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM')
gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK')
gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK')
# audio codec
gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1')
gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC')
gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT')
gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0')
gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK')
# serial ports
gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD')
gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD')
gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS')
gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS')
gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR')
gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR')
gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI')
gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD')
gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD')
gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD')
gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS')
gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS')
gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD')
gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD')
# misc GPIO signals
gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ')
gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT')
gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK')
gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK')
gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED')
gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#')
gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#')
gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#')
gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK')
gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#')
gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH')
gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#')
gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA')
gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#')
gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#')
# LCD GPIOs
gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0')
gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1')
gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2')
gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3')
gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4')
gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5')
gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6')
gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7')
gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8')
gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9')
gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10')
gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11')
gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12')
gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13')
gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14')
gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15')
gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK')
gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK')
gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK')
gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS')
# calculate registers
pxa_regs = {
'gpdr0':0, 'gpdr1':0, 'gpdr2':0,
'gpsr0':0, 'gpsr1':0, 'gpsr2':0,
'gpcr0':0, 'gpcr1':0, 'gpcr2':0,
'gafr0_l':0, 'gafr0_u':0,
'gafr1_l':0, 'gafr1_u':0,
'gafr2_l':0, 'gafr2_u':0,
}
# U-boot define names
uboot_reg_names = {
'gpdr0':'CFG_GPDR0_VAL', 'gpdr1':'CFG_GPDR1_VAL', 'gpdr2':'CFG_GPDR2_VAL',
'gpsr0':'CFG_GPSR0_VAL', 'gpsr1':'CFG_GPSR1_VAL', 'gpsr2':'CFG_GPSR2_VAL',
'gpcr0':'CFG_GPCR0_VAL', 'gpcr1':'CFG_GPCR1_VAL', 'gpcr2':'CFG_GPCR2_VAL',
'gafr0_l':'CFG_GAFR0_L_VAL', 'gafr0_u':'CFG_GAFR0_U_VAL',
'gafr1_l':'CFG_GAFR1_L_VAL', 'gafr1_u':'CFG_GAFR1_U_VAL',
'gafr2_l':'CFG_GAFR2_L_VAL', 'gafr2_u':'CFG_GAFR2_U_VAL',
}
# bit mappings
bit_mappings = [
{ 'gpio':(0,32), 'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} },
{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} },
{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} },
{ 'gpio':(0,16), 'shift':2, 'regs':{'alt':'gafr0_l'} },
{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} },
{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} },
{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} },
{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} },
{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} },
]
def stuff_bits(bit_mapping, gpio_list):
gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1])
for gpio in gpios:
for reg in bit_mapping['regs'].keys():
value = eval( 'gpio_list[gpio].%s' % (reg) )
if ( value ):
# we have a high bit
bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift']
bit = value << (bit_shift)
pxa_regs[bit_mapping['regs'][reg]] |= bit
for i in bit_mappings:
stuff_bits(i, gpio_list)
# now print out all regs
registers = pxa_regs.keys()
registers.sort()
for reg in registers:
print '%s: 0x%x' % (reg, pxa_regs[reg])
# print define to past right into U-Boot source code
print
print
for reg in registers:
print '#define %s 0x%x' % (uboot_reg_names[reg], pxa_regs[reg])
# print all GPIOS
print
print
for i in range(len(gpio_list)):
gpio_i = gpio_list[i]
alt_func_desc = pxa255_alt_func[i][gpio_i.alt]
print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc)

55
board/pxa255_idp/u-boot.lds
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/*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/pxa/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

338
include/configs/pxa255_idp.h
Unescape View File

@ -0,0 +1,338 @@
/*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* Copied from lubbock.h
*
* (C) Copyright 2004
* BEC Systems <http://bec-systems.com>
* Cliff Brake <cliff.brake@gmail.com>
* Configuation settings for the Accelent/Vibren PXA255 IDP
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/pxa-regs.h>
/*
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
#define CONFIG_INIT_CRITICAL /* undef for developing */
/*
* define the following to enable debug blinks. A debug blink function
* must be defined in memsetup.S
*/
#undef DEBUG_BLINK_ENABLE
#undef DEBUG_BLINKC_ENABLE
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
#undef CONFIG_LCD
#ifdef CONFIG_LCD
#define CONFIG_SHARP_LM8V31
#endif
#define CONFIG_MMC 1
#define BOARD_LATE_INIT 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* PXA250 IDP memory map information
*/
#define IDP_CS5_ETH_OFFSET 0x03400000
/*
* Hardware drivers
*/
#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
#define CONFIG_SMC_USE_32_BIT 1
/* #define CONFIG_SMC_USE_IOFUNCS */
/* the following has to be set high -- suspect something is wrong with
* with the tftp timeout routines. FIXME!!!
*/
#define CONFIG_NET_RETRY_COUNT 100
/*
* select serial console configuration
*/
#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_DHCP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND "bootm 40000"
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
#define CONFIG_CMDLINE_TAG
/*
* Current memory map for Vibren supplied Linux images:
*
* Flash:
* 0 - 0x3ffff (size = 0x40000): bootloader
* 0x40000 - 0x13ffff (size = 0x100000): kernel
* 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
*
* RAM:
* 0xa0008000 - kernel is loaded
* 0xa3000000 - Uboot runs (48MB into RAM)
*
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"prog_boot_mmc=" \
"mw.b 0xa0000000 0xff 0x40000; " \
"if mmcinit && " \
"fatload mmc 0 0xa0000000 u-boot.bin; " \
"then " \
"protect off 0x0 0x3ffff; " \
"erase 0x0 0x3ffff; " \
"cp.b 0xa0000000 0x0 0x40000; " \
"reset;" \
"fi\0" \
"prog_uzImage_mmc=" \
"mw.b 0xa0000000 0xff 0x100000; " \
"if mmcinit && " \
"fatload mmc 0 0xa0000000 uzImage; " \
"then " \
"protect off 0x40000 0xfffff; " \
"erase 0x40000 0xfffff; " \
"cp.b 0xa0000000 0x40000 0x100000; " \
"fi\0" \
"prog_jffs_mmc=" \
"mw.b 0xa0000000 0xff 0x1e00000; " \
"if mmcinit && " \
"fatload mmc 0 0xa0000000 root.jffs; " \
"then " \
"protect off 0x140000 0x1f3ffff; " \
"erase 0x140000 0x1f3ffff; " \
"cp.b 0xa0000000 0x140000 0x1e00000; " \
"fi\0" \
"boot_mmc=" \
"if mmcinit && " \
"fatload mmc 0 0xa1000000 uzImage && " \
"then " \
"bootm 0xa1000000; " \
"fi\0" \
"prog_boot_net=" \
"mw.b 0xa0000000 0xff 0x100000; " \
"if bootp 0xa0000000 u-boot.bin; " \
"then " \
"protect off 0x0 0x3ffff; " \
"erase 0x0 0x3ffff; " \
"cp.b 0xa0000000 0x0 0x40000; " \
"reset; " \
"fi\0" \
"prog_uzImage_net=" \
"mw.b 0xa0000000 0xff 0x100000; " \
"if bootp 0xa0000000 uzImage; " \
"then " \
"protect off 0x40000 0xfffff; " \
"erase 0x40000 0xfffff; " \
"cp.b 0xa0000000 0x40000 0x100000; " \
"fi\0" \
"prog_jffs_net=" \
"mw.b 0xa0000000 0xff 0x1e00000; " \
"if bootp 0xa0000000 root.jffs; " \
"then " \
"protect off 0x140000 0x1f3ffff; " \
"erase 0x140000 0x1f3ffff; " \
"cp.b 0xa0000000 0x140000 0x1e00000; " \
"fi\0"
/* "erase_env=" */
/* "protect off" */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT "$ " /* Monitor Command Prompt */
#else
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#endif
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_DEVICE_NULLDEV 1
#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0xa0800000 /* default load address */
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
#define RTC 1 /* enable 32KHz osc */
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_MMC_BASE 0xF0000000
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
#define CFG_DRAM_BASE 0xa0000000
#define CFG_DRAM_SIZE 0x04000000
#define CFG_FLASH_BASE PHYS_FLASH_1
/*
* GPIO settings
*/
#define CFG_GAFR0_L_VAL 0x80001005
#define CFG_GAFR0_U_VAL 0xa5128012
#define CFG_GAFR1_L_VAL 0x699a9558
#define CFG_GAFR1_U_VAL 0xaaa5aa6a
#define CFG_GAFR2_L_VAL 0xaaaaaaaa
#define CFG_GAFR2_U_VAL 0x2
#define CFG_GPCR0_VAL 0x1800400
#define CFG_GPCR1_VAL 0x0
#define CFG_GPCR2_VAL 0x0
#define CFG_GPDR0_VAL 0xc1818440
#define CFG_GPDR1_VAL 0xfcffab82
#define CFG_GPDR2_VAL 0x1ffff
#define CFG_GPSR0_VAL 0x8000
#define CFG_GPSR1_VAL 0x3f0002
#define CFG_GPSR2_VAL 0x1c000
#define CFG_PSSR_VAL 0x20
/*
* Memory settings
*/
#define CFG_MSC0_VAL 0x29DCA4D2
#define CFG_MSC1_VAL 0x43AC494C
#define CFG_MSC2_VAL 0x39D449D4
#define CFG_MDCNFG_VAL 0x090009C9
#define CFG_MDREFR_VAL 0x0085C017
#define CFG_MDMRS_VAL 0x00220022
/*
* PCMCIA and CF Interfaces
*/
#define CFG_MECR_VAL 0x00000003
#define CFG_MCMEM0_VAL 0x00014405
#define CFG_MCMEM1_VAL 0x00014405
#define CFG_MCATT0_VAL 0x00014405
#define CFG_MCATT1_VAL 0x00014405
#define CFG_MCIO0_VAL 0x00014405
#define CFG_MCIO1_VAL 0x00014405
/*
* FLASH and environment organization
*/
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER 1
#define CFG_MONITOR_BASE 0
#define CFG_MONITOR_LEN 0x40000
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_FLASH_USE_BUFFER_WRITE 1
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
/* put cfg at end of flash for now */
#define CFG_ENV_IS_IN_FLASH 1
/* Addr of Environment Sector */
#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x40000
#endif /* __CONFIG_H */
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