@ -157,9 +157,11 @@ static const struct sys_mmu_table early_mmu_table[] = {
{ CONFIG_SYS_FSL_IFC_BASE , CONFIG_SYS_FSL_IFC_BASE ,
CONFIG_SYS_FSL_IFC_SIZE , MT_DEVICE_NGNRNE , PTE_BLOCK_NON_SHARE } ,
{ CONFIG_SYS_FSL_DRAM_BASE1 , CONFIG_SYS_FSL_DRAM_BASE1 ,
CONFIG_SYS_FSL_DRAM_SIZE1 , MT_NORMAL , PTE_BLOCK_OUTER_SHARE } ,
CONFIG_SYS_FSL_DRAM_SIZE1 , MT_NORMAL ,
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS } ,
{ CONFIG_SYS_FSL_DRAM_BASE2 , CONFIG_SYS_FSL_DRAM_BASE2 ,
CONFIG_SYS_FSL_DRAM_SIZE2 , MT_NORMAL , PTE_BLOCK_OUTER_SHARE } ,
CONFIG_SYS_FSL_DRAM_SIZE2 , MT_NORMAL ,
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS } ,
# endif
} ;
@ -245,7 +247,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
CONFIG_SYS_FSL_QBMAN_SIZE , MT_DEVICE_NGNRNE ,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN } ,
{ CONFIG_SYS_FSL_DRAM_BASE2 , CONFIG_SYS_FSL_DRAM_BASE2 ,
CONFIG_SYS_FSL_DRAM_SIZE2 , MT_NORMAL , PTE_BLOCK_OUTER_SHARE } ,
CONFIG_SYS_FSL_DRAM_SIZE2 , MT_NORMAL ,
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS } ,
{ CONFIG_SYS_PCIE1_PHYS_ADDR , CONFIG_SYS_PCIE1_PHYS_ADDR ,
CONFIG_SYS_PCIE1_PHYS_SIZE , MT_DEVICE_NGNRNE ,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN } ,
@ -256,7 +259,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
CONFIG_SYS_PCIE3_PHYS_SIZE , MT_DEVICE_NGNRNE ,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN } ,
{ CONFIG_SYS_FSL_DRAM_BASE3 , CONFIG_SYS_FSL_DRAM_BASE3 ,
CONFIG_SYS_FSL_DRAM_SIZE3 , MT_NORMAL , PTE_BLOCK_OUTER_SHARE } ,
CONFIG_SYS_FSL_DRAM_SIZE3 , MT_NORMAL ,
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS } ,
# endif
} ;
# endif