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nios2: remove obsolete PCI5441 and PK1C20 boards

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Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
master
Thomas Chou 10 years ago
parent 00a2517fcb
commit 70fbc46192
17 changed files with 0 additions and 749 deletions
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  1. 8
      arch/nios2/Kconfig
  2. 170
      board/psyent/common/AMDLV065D.c
  3. 15
      board/psyent/pci5441/Kconfig
  4. 6
      board/psyent/pci5441/MAINTAINERS
  5. 8
      board/psyent/pci5441/Makefile
  6. 14
      board/psyent/pci5441/config.mk
  7. 24
      board/psyent/pci5441/pci5441.c
  8. 15
      board/psyent/pk1c20/Kconfig
  9. 6
      board/psyent/pk1c20/MAINTAINERS
  10. 8
      board/psyent/pk1c20/Makefile
  11. 14
      board/psyent/pk1c20/config.mk
  12. 46
      board/psyent/pk1c20/led.c
  13. 36
      board/psyent/pk1c20/pk1c20.c
  14. 2
      configs/PCI5441_defconfig
  15. 2
      configs/PK1C20_defconfig
  16. 150
      include/configs/PCI5441.h
  17. 225
      include/configs/PK1C20.h

8
arch/nios2/Kconfig
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@ -11,16 +11,8 @@ choice
config TARGET_NIOS2_GENERIC
bool "Support nios2-generic"
config TARGET_PCI5441
bool "Support PCI5441"
config TARGET_PK1C20
bool "Support PK1C20"
endchoice
source "board/altera/nios2-generic/Kconfig"
source "board/psyent/pci5441/Kconfig"
source "board/psyent/pk1c20/Kconfig"
endmenu

170
board/psyent/common/AMDLV065D.c
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@ -1,170 +0,0 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#define SECTSZ (64 * 1024)
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/*----------------------------------------------------------------------*/
unsigned long flash_init (void)
{
int i;
unsigned long addr;
flash_info_t *fli = &flash_info[0];
fli->size = CONFIG_SYS_FLASH_SIZE;
fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
addr = CONFIG_SYS_FLASH_BASE;
for (i = 0; i < fli->sector_count; ++i) {
fli->start[i] = addr;
addr += SECTSZ;
fli->protect[i] = 1;
}
return (CONFIG_SYS_FLASH_SIZE);
}
/*--------------------------------------------------------------------*/
void flash_print_info (flash_info_t * info)
{
int i, k;
int erased;
unsigned long *addr;
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
/* Check if whole sector is erased */
erased = 1;
addr = (unsigned long *) info->start[i];
for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
if ( readl(addr++) != (unsigned long)-1) {
erased = 0;
break;
}
}
/* Print the info */
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " ");
}
printf ("\n");
}
/*-------------------------------------------------------------------*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
unsigned char *addr = (unsigned char *) info->start[0];
unsigned char *addr2;
int prot, sect;
ulong start;
/* Some sanity checking */
if ((s_first < 0) || (s_first > s_last)) {
printf ("- no sectors to erase\n");
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
/* It's ok to erase multiple sectors provided we don't delay more
* than 50 usec between cmds ... at which point the erase time-out
* occurs. So don't go and put printf() calls in the loop ... it
* won't be very helpful ;-)
*/
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (unsigned char *) info->start[sect];
writeb (0xaa, addr);
writeb (0x55, addr);
writeb (0x80, addr);
writeb (0xaa, addr);
writeb (0x55, addr);
writeb (0x30, addr2);
/* Now just wait for 0xff & provide some user
* feedback while we wait.
*/
start = get_timer (0);
while ( readb (addr2) != 0xff) {
udelay (1000 * 1000);
putc ('.');
if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("timeout\n");
return 1;
}
}
}
}
printf ("\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
vu_char *cmd = (vu_char *) info->start[0];
vu_char *dst = (vu_char *) addr;
unsigned char b;
ulong start;
while (cnt) {
/* Check for sufficient erase */
b = *src;
if ((readb (dst) & b) != b) {
printf ("%02x : %02x\n", readb (dst), b);
return (2);
}
writeb (0xaa, cmd);
writeb (0x55, cmd);
writeb (0xa0, cmd);
writeb (dst, b);
/* Verify write */
start = get_timer (0);
while (readb (dst) != b) {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return 1;
}
}
dst++;
src++;
cnt--;
}
return (0);
}

15
board/psyent/pci5441/Kconfig
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@ -1,15 +0,0 @@
if TARGET_PCI5441
config SYS_BOARD
string
default "pci5441"
config SYS_VENDOR
string
default "psyent"
config SYS_CONFIG_NAME
string
default "PCI5441"
endif

6
board/psyent/pci5441/MAINTAINERS
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@ -1,6 +0,0 @@
PCI5441 BOARD
M: Scott McNutt <smcnutt@psyent.com>
S: Maintained
F: board/psyent/pci5441/
F: include/configs/PCI5441.h
F: configs/PCI5441_defconfig

8
board/psyent/pci5441/Makefile
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@ -1,8 +0,0 @@
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := pci5441.o ../common/AMDLV065D.o

14
board/psyent/pci5441/config.mk
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@ -1,14 +0,0 @@
#
# (C) Copyright 2004, Psyent Corporation <www.psyent.com>
# Scott McNutt <smcnutt@psyent.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
CONFIG_SYS_TEXT_BASE = 0x018e0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

24
board/psyent/pci5441/pci5441.c
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@ -1,24 +0,0 @@
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
int board_early_init_f (void)
{
return 0;
}
int checkboard (void)
{
puts ("BOARD : Psyent PCI-5441\n");
return 0;
}
phys_size_t initdram (int board_type)
{
return (0);
}

15
board/psyent/pk1c20/Kconfig
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@ -1,15 +0,0 @@
if TARGET_PK1C20
config SYS_BOARD
string
default "pk1c20"
config SYS_VENDOR
string
default "psyent"
config SYS_CONFIG_NAME
string
default "PK1C20"
endif

6
board/psyent/pk1c20/MAINTAINERS
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@ -1,6 +0,0 @@
PK1C20 BOARD
M: Scott McNutt <smcnutt@psyent.com>
S: Maintained
F: board/psyent/pk1c20/
F: include/configs/PK1C20.h
F: configs/PK1C20_defconfig

8
board/psyent/pk1c20/Makefile
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@ -1,8 +0,0 @@
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := pk1c20.o led.o ../common/AMDLV065D.o

14
board/psyent/pk1c20/config.mk
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@ -1,14 +0,0 @@
#
# (C) Copyright 2004, Psyent Corporation <www.psyent.com>
# Scott McNutt <smcnutt@psyent.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
CONFIG_SYS_TEXT_BASE = 0x01fc0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

46
board/psyent/pk1c20/led.c
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@ -1,46 +0,0 @@
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <nios2-io.h>
#include <status_led.h>
/* The LED port is configured as output only, so we
* must track the state manually.
*/
static led_id_t val = 0;
void __led_init (led_id_t mask, int state)
{
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
if (state == STATUS_LED_ON)
val &= ~mask;
else
val |= mask;
writel (val, &pio->data);
}
void __led_set (led_id_t mask, int state)
{
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
if (state == STATUS_LED_ON)
val &= ~mask;
else
val |= mask;
writel (val, &pio->data);
}
void __led_toggle (led_id_t mask)
{
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
val ^= mask;
writel (val, &pio->data);
}

36
board/psyent/pk1c20/pk1c20.c
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@ -1,36 +0,0 @@
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
int board_early_init_f (void)
{
return 0;
}
int checkboard (void)
{
puts ("BOARD : Psyent PK-1C20\n");
return 0;
}
phys_size_t initdram (int board_type)
{
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

2
configs/PCI5441_defconfig
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@ -1,2 +0,0 @@
CONFIG_NIOS2=y
CONFIG_TARGET_PCI5441=y

2
configs/PK1C20_defconfig
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@ -1,2 +0,0 @@
CONFIG_NIOS2=y
CONFIG_TARGET_PK1C20=y

150
include/configs/PCI5441.h
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@ -1,150 +0,0 @@
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*------------------------------------------------------------------------
* BOARD/CPU
*----------------------------------------------------------------------*/
#define CONFIG_PCI5441 1 /* PCI-5441 board */
#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
#define CONFIG_SYS_NIOS_SYSID_BASE 0x00920828 /* System id address */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
* CACHE -- the following will support II/s and II/f. The II/s does not
* have dcache, so the cache instructions will behave as NOPs.
*----------------------------------------------------------------------*/
#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
/*------------------------------------------------------------------------
* MEMORY BASE ADDRESSES
*----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
/*------------------------------------------------------------------------
* MEMORY ORGANIZATION
* -Monitor at top.
* -The heap is placed below the monitor.
* -Global data is placed below the heap.
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128k */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
/*------------------------------------------------------------------------
* FLASH (AM29LV065D)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */
/*------------------------------------------------------------------------
* ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
* CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
* reset address, no? This will keep the environment in user region
* of flash. NOTE: the monitor length must be multiple of sector size
* (which is common practice).
*----------------------------------------------------------------------*/
#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
#define CONFIG_ALTERA_UART 1 /* Use altera uart */
#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */
#endif
#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
/*------------------------------------------------------------------------
* DEBUG
*----------------------------------------------------------------------*/
#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
/*------------------------------------------------------------------------
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
* registers, the interrupt frequency can be reduced using TMRCNT.
* If the default period is acceptable, TMRCNT can be left undefined.
* TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
#define CONFIG_SYS_LOW_RES_TIMER
#define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */
#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
#define CONFIG_SYS_NIOS_TMRCNT \
(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#define CONFIG_CMD_BDI
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVES
/*------------------------------------------------------------------------
* MISC
*----------------------------------------------------------------------*/
#define CONFIG_SYS_LONGHELP /* Provide extended help*/
#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
#define CONFIG_SYS_MAXARGS 16 /* Max command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
#endif /* __CONFIG_H */

225
include/configs/PK1C20.h
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@ -1,225 +0,0 @@
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*------------------------------------------------------------------------
* BOARD/CPU
*----------------------------------------------------------------------*/
#define CONFIG_PK1C20 1 /* PK1C20 board */
#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
* CACHE -- the following will support II/s and II/f. The II/s does not
* have dcache, so the cache instructions will behave as NOPs.
*----------------------------------------------------------------------*/
#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
/*------------------------------------------------------------------------
* MEMORY BASE ADDRESSES
*----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */
#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
/*------------------------------------------------------------------------
* MEMORY ORGANIZATION
* -Monitor at top.
* -The heap is placed below the monitor.
* -Global data is placed below the heap.
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
/*------------------------------------------------------------------------
* FLASH (AM29LV065D)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */
/*------------------------------------------------------------------------
* ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
* CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
* reset address, no? This will keep the environment in user region
* of flash. NOTE: the monitor length must be multiple of sector size
* (which is common practice).
*----------------------------------------------------------------------*/
#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
#define CONFIG_ALTERA_UART 1 /* Use altera uart */
#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
#endif
#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
/*------------------------------------------------------------------------
* EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
* epcs device access is enabled. The base address is the epcs
* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
* The register base is currently at offset 0x600 from the memory base.
*----------------------------------------------------------------------*/
#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
/*------------------------------------------------------------------------
* DEBUG
*----------------------------------------------------------------------*/
#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
/*------------------------------------------------------------------------
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
* registers, the interrupt frequency can be reduced using TMRCNT.
* If the default period is acceptable, TMRCNT can be left undefined.
* TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
#define CONFIG_SYS_LOW_RES_TIMER
#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */
#define CONFIG_SYS_NIOS_TMRCNT \
(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
* must implement its own led routines -- leds are, after all,
* board-specific, no?
*----------------------------------------------------------------------*/
#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
#define CONFIG_STATUS_LED /* Enable status driver */
#define CONFIG_BOARD_SPECIFIC_LED
#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
#define STATUS_LED_STATE 1 /* Blinking */
#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */
/*------------------------------------------------------------------------
* ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
* and really doesn't need any additional clutter. So I choose the lazy
* way out to avoid changes there -- define the base address to ensure
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
#define CONFIG_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVES
/*------------------------------------------------------------------------
* COMPACT FLASH
*----------------------------------------------------------------------*/
#if defined(CONFIG_CMD_IDE)
#define CONFIG_IDE_PREINIT /* Implement id_preinit */
#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
#define CONFIG_SYS_ATA_BASE_ADDR 0x00900800 /* ATA base addr */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset */
#define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */
#define CONFIG_SYS_ATA_STRIDE 4 /* Width betwix addrs */
#define CONFIG_DOS_PARTITION
/* Board-specific cf regs */
#define CONFIG_SYS_CF_PRESENT 0x00900880 /* CF Present PIO base */
#define CONFIG_SYS_CF_POWER 0x00900890 /* CF Power FET PIO base*/
#define CONFIG_SYS_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */
#endif
/*------------------------------------------------------------------------
* JFFS2
*----------------------------------------------------------------------*/
#if defined(CONFIG_CMD_JFFS2)
#define CONFIG_SYS_JFFS_CUSTOM_PART /* board defined part */
#endif
/*------------------------------------------------------------------------
* MISC
*----------------------------------------------------------------------*/
#define CONFIG_SYS_LONGHELP /* Provide extended help*/
#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
#define CONFIG_SYS_MAXARGS 16 /* Max command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
#define CONFIG_SYS_HUSH_PARSER
#endif /* __CONFIG_H */
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