This covers only non-L2 switch ethernet interfaces i.e. RGMII and SGMII interface for both T1040RDB and T1042RDB_PI T1040RDB is configured as serdes protocol 0x66 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 1 SGMII on DTSEC3 T1042RDB_PI is configured as serdes protocol 0x06 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: Minor change in commit message] Signed-off-by: York Sun <yorksun@freescale.com>master
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/immap_85xx.h> |
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#include <fm_eth.h> |
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#include <fsl_mdio.h> |
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#include <malloc.h> |
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#include <asm/fsl_dtsec.h> |
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#include "../common/fman.h" |
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int board_eth_init(bd_t *bis) |
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{ |
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#ifdef CONFIG_FMAN_ENET |
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struct memac_mdio_info memac_mdio_info; |
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unsigned int i; |
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int phy_addr = 0; |
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printf("Initializing Fman\n"); |
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memac_mdio_info.regs = |
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; |
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memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; |
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/* Register the real 1G MDIO bus */ |
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fm_memac_mdio_init(bis, &memac_mdio_info); |
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/*
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* Program on board RGMII, SGMII PHY addresses. |
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*/ |
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { |
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int idx = i - FM1_DTSEC1; |
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switch (fm_info_get_enet_if(i)) { |
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#ifdef CONFIG_T1040RDB |
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case PHY_INTERFACE_MODE_SGMII: |
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/* T1040RDB only supports SGMII on DTSEC3 */ |
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fm_info_set_phy_address(FM1_DTSEC3, |
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CONFIG_SYS_SGMII1_PHY_ADDR); |
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#endif |
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case PHY_INTERFACE_MODE_RGMII: |
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if (FM1_DTSEC4 == i) |
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phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; |
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if (FM1_DTSEC5 == i) |
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phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; |
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fm_info_set_phy_address(i, phy_addr); |
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break; |
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case PHY_INTERFACE_MODE_QSGMII: |
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fm_info_set_phy_address(i, 0); |
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break; |
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case PHY_INTERFACE_MODE_NONE: |
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fm_info_set_phy_address(i, 0); |
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break; |
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default: |
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printf("Fman1: DTSEC%u set to unknown interface %i\n", |
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idx + 1, fm_info_get_enet_if(i)); |
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fm_info_set_phy_address(i, 0); |
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break; |
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} |
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fm_info_set_mdio(i, |
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); |
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} |
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cpu_eth_init(bis); |
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#endif |
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return pci_eth_init(bis); |
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} |
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