Support spi driver and can detect MX25U1635E flash on AE3XX board. Verification: sf probe 0:0 50000000 0 spi_flash_std_probe(sf_Probr.c) spi_flash_probe_slave(sf_Probr.c) SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB NDS32 # sf test 0x100000 0x1000 SPI flash test: 0 erase: 34 ticks, 117 KiB/s 0.936 Mbps 1 check: 15 ticks, 266 KiB/s 2.128 Mbps 2 write: 21 ticks, 190 KiB/s 1.520 Mbps 3 read: 11 ticks, 363 KiB/s 2.904 Mbps Test passed 0 erase: 34 ticks, 117 KiB/s 0.936 Mbps 1 check: 15 ticks, 266 KiB/s 2.128 Mbps 2 write: 21 ticks, 190 KiB/s 1.520 Mbps 3 read: 11 ticks, 363 KiB/s 2.904 Mbps Signed-off-by: rick <rick@andestech.com>master
rick
7 years ago
committed by
Andes
parent
7b1a50b7b6
commit
7155cd2e6e
@ -0,0 +1,499 @@ |
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/*
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* NDS SPI controller driver. |
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* |
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* Copyright 2017 Andes Technology, Inc. |
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* Author: Rick Chen (rick@andestech.com) |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <clk.h> |
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#include <common.h> |
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#include <malloc.h> |
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#include <spi.h> |
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#include <asm/io.h> |
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#include <dm.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define MAX_TRANSFER_LEN 512 |
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#define CHUNK_SIZE 1 |
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#define SPI_TIMEOUT 0x100000 |
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#define SPI0_BUS 0 |
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#define SPI1_BUS 1 |
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#define SPI0_BASE 0xf0b00000 |
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#define SPI1_BASE 0xf0f00000 |
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#define NSPI_MAX_CS_NUM 1 |
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struct ae3xx_spi_regs { |
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u32 rev; |
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u32 reserve1[3]; |
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u32 format; /* 0x10 */ |
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#define DATA_LENGTH(x) ((x-1)<<8) |
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u32 pio; |
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u32 reserve2[2]; |
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u32 tctrl; /* 0x20 */ |
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#define TRAMODE_OFFSET 24 |
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#define TRAMODE_MASK (0x0F<<TRAMODE_OFFSET) |
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#define TRAMODE_WR_SYNC (0<<TRAMODE_OFFSET) |
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#define TRAMODE_WO (1<<TRAMODE_OFFSET) |
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#define TRAMODE_RO (2<<TRAMODE_OFFSET) |
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#define TRAMODE_WR (3<<TRAMODE_OFFSET) |
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#define TRAMODE_RW (4<<TRAMODE_OFFSET) |
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#define TRAMODE_WDR (5<<TRAMODE_OFFSET) |
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#define TRAMODE_RDW (6<<TRAMODE_OFFSET) |
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#define TRAMODE_NONE (7<<TRAMODE_OFFSET) |
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#define TRAMODE_DW (8<<TRAMODE_OFFSET) |
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#define TRAMODE_DR (9<<TRAMODE_OFFSET) |
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#define WCNT_OFFSET 12 |
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#define WCNT_MASK (0x1FF<<WCNT_OFFSET) |
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#define RCNT_OFFSET 0 |
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#define RCNT_MASK (0x1FF<<RCNT_OFFSET) |
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u32 cmd; |
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u32 addr; |
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u32 data; |
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u32 ctrl; /* 0x30 */ |
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#define TXFTH_OFFSET 16 |
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#define RXFTH_OFFSET 8 |
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#define TXDMAEN (1<<4) |
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#define RXDMAEN (1<<3) |
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#define TXFRST (1<<2) |
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#define RXFRST (1<<1) |
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#define SPIRST (1<<0) |
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u32 status; |
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#define TXFFL (1<<23) |
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#define TXEPTY (1<<22) |
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#define TXFVE_MASK (0x1F<<16) |
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#define RXFEM (1<<14) |
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#define RXFVE_OFFSET (8) |
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#define RXFVE_MASK (0x1F<<RXFVE_OFFSET) |
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#define SPIBSY (1<<0) |
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u32 inten; |
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u32 intsta; |
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u32 timing; /* 0x40 */ |
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#define SCLK_DIV_MASK 0xFF |
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}; |
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struct nds_spi_slave { |
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#ifndef CONFIG_DM_SPI |
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struct spi_slave slave; |
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#endif |
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volatile struct ae3xx_spi_regs *regs; |
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int to; |
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unsigned int freq; |
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ulong clock; |
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unsigned int mode; |
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u8 num_cs; |
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unsigned int mtiming; |
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size_t cmd_len; |
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u8 cmd_buf[16]; |
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size_t data_len; |
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size_t tran_len; |
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u8 *din; |
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u8 *dout; |
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unsigned int max_transfer_length; |
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}; |
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static int __ae3xx_spi_set_speed(struct nds_spi_slave *ns) |
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{ |
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u32 tm; |
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u8 div; |
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tm = ns->regs->timing; |
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tm &= ~SCLK_DIV_MASK; |
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if(ns->freq >= ns->clock) |
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div =0xff; |
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else{ |
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for (div = 0; div < 0xff; div++) { |
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if (ns->freq >= ns->clock / (2 * (div + 1))) |
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break; |
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} |
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} |
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tm |= div; |
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ns->regs->timing = tm; |
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return 0; |
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} |
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static int __ae3xx_spi_claim_bus(struct nds_spi_slave *ns) |
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{ |
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unsigned int format=0; |
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ns->regs->ctrl |= (TXFRST|RXFRST|SPIRST); |
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while((ns->regs->ctrl &(TXFRST|RXFRST|SPIRST))&&(ns->to--)) |
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if(!ns->to) |
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return -EINVAL; |
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ns->cmd_len = 0; |
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format = ns->mode|DATA_LENGTH(8); |
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ns->regs->format = format; |
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__ae3xx_spi_set_speed(ns); |
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return 0; |
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} |
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static int __ae3xx_spi_release_bus(struct nds_spi_slave *ns) |
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{ |
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/* do nothing */ |
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return 0; |
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} |
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static int __ae3xx_spi_start(struct nds_spi_slave *ns) |
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{ |
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int i,olen=0; |
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int tc = ns->regs->tctrl; |
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tc &= ~(WCNT_MASK|RCNT_MASK|TRAMODE_MASK); |
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if ((ns->din)&&(ns->cmd_len)) |
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tc |= TRAMODE_WR; |
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else if (ns->din) |
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tc |= TRAMODE_RO; |
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else |
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tc |= TRAMODE_WO; |
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if(ns->dout) |
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olen = ns->tran_len; |
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tc |= (ns->cmd_len+olen-1) << WCNT_OFFSET; |
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if(ns->din) |
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tc |= (ns->tran_len-1) << RCNT_OFFSET; |
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ns->regs->tctrl = tc; |
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ns->regs->cmd = 1; |
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for (i=0;i<ns->cmd_len;i++) |
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ns->regs->data = ns->cmd_buf[i]; |
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return 0; |
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} |
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static int __ae3xx_spi_stop(struct nds_spi_slave *ns) |
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{ |
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ns->regs->timing = ns->mtiming; |
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while ((ns->regs->status & SPIBSY)&&(ns->to--)) |
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if (!ns->to) |
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return -EINVAL; |
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return 0; |
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} |
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static void __nspi_espi_tx(struct nds_spi_slave *ns, const void *dout) |
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{ |
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ns->regs->data = *(u8 *)dout; |
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} |
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static int __nspi_espi_rx(struct nds_spi_slave *ns, void *din, unsigned int bytes) |
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{ |
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*(u8 *)din = ns->regs->data; |
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return bytes; |
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} |
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static int __ae3xx_spi_xfer(struct nds_spi_slave *ns, |
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unsigned int bitlen, const void *data_out, void *data_in, |
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unsigned long flags) |
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{ |
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unsigned int event, rx_bytes; |
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const void *dout = NULL; |
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void *din = NULL; |
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int num_blks, num_chunks, max_tran_len, tran_len; |
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int num_bytes; |
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u8 *cmd_buf = ns->cmd_buf; |
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size_t cmd_len = ns->cmd_len; |
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size_t data_len = bitlen / 8; |
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int rf_cnt; |
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int ret = 0; |
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max_tran_len = ns->max_transfer_length; |
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switch (flags) { |
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case SPI_XFER_BEGIN: |
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cmd_len = ns->cmd_len = data_len; |
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memcpy(cmd_buf, data_out, cmd_len); |
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return 0; |
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case 0: |
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case SPI_XFER_END: |
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if (bitlen == 0) { |
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return 0; |
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} |
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ns->data_len = data_len; |
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ns->din = (u8 *)data_in; |
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ns->dout = (u8 *)data_out; |
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break; |
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case SPI_XFER_BEGIN | SPI_XFER_END: |
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ns->data_len = 0; |
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ns->din = 0; |
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ns->dout = 0; |
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cmd_len = ns->cmd_len = data_len; |
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memcpy(cmd_buf, data_out, cmd_len); |
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data_out = 0; |
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data_len = 0; |
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__ae3xx_spi_start(ns); |
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break; |
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} |
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debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %u\n", |
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*(uint *)data_out, data_out, *(uint *)data_in, data_in, data_len); |
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num_chunks = DIV_ROUND_UP(data_len, max_tran_len); |
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din = data_in; |
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dout = data_out; |
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while (num_chunks--) { |
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tran_len = min(data_len, (size_t)max_tran_len); |
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ns->tran_len = tran_len; |
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num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE); |
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num_bytes = (tran_len) % CHUNK_SIZE; |
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if(num_bytes == 0) |
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num_bytes = CHUNK_SIZE; |
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__ae3xx_spi_start(ns); |
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while (num_blks) { |
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event = in_le32(&ns->regs->status); |
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if ((event & TXEPTY) && (data_out)) { |
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__nspi_espi_tx(ns, dout); |
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num_blks -= CHUNK_SIZE; |
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dout += CHUNK_SIZE; |
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} |
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if ((event & RXFVE_MASK) && (data_in)) { |
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rf_cnt = ((event & RXFVE_MASK)>> RXFVE_OFFSET); |
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if (rf_cnt >= CHUNK_SIZE) |
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rx_bytes = CHUNK_SIZE; |
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else if (num_blks == 1 && rf_cnt == num_bytes) |
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rx_bytes = num_bytes; |
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else |
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continue; |
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if (__nspi_espi_rx(ns, din, rx_bytes) == rx_bytes) { |
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num_blks -= CHUNK_SIZE; |
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din = (unsigned char *)din + rx_bytes; |
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} |
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} |
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} |
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data_len -= tran_len; |
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if(data_len) |
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{ |
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ns->cmd_buf[1] += ((tran_len>>16)&0xff); |
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ns->cmd_buf[2] += ((tran_len>>8)&0xff); |
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ns->cmd_buf[3] += ((tran_len)&0xff); |
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ns->data_len = data_len; |
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} |
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ret = __ae3xx_spi_stop(ns); |
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} |
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ret = __ae3xx_spi_stop(ns); |
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return ret; |
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} |
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#ifndef CONFIG_DM_SPI |
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#define to_nds_spi_slave(s) container_of(s, struct nds_spi_slave, slave) |
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
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unsigned int max_hz, unsigned int mode) |
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{ |
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struct nds_spi_slave *ns; |
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if (!spi_cs_is_valid(bus, cs)) |
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return NULL; |
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ns = spi_alloc_slave(struct nds_spi_slave, bus, cs); |
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switch (bus) { |
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case SPI0_BUS: |
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ns->regs = (struct ae3xx_spi_regs *)SPI0_BASE; |
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break; |
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case SPI1_BUS: |
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ns->regs = (struct ae3xx_spi_regs *)SPI1_BASE; |
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break; |
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default: |
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return NULL; |
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} |
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ns->freq= max_hz; |
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ns->mode = mode; |
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ns->to = SPI_TIMEOUT; |
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ns->max_transfer_length = MAX_TRANSFER_LEN; |
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ns->slave.max_write_size = MAX_TRANSFER_LEN; |
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if (!ns) |
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return NULL; |
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return &ns->slave; |
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} |
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void spi_free_slave(struct spi_slave *slave) |
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{ |
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struct nds_spi_slave *ns = to_nds_spi_slave(slave); |
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free(ns); |
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} |
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void spi_init(void) |
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{ |
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/* do nothing */ |
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} |
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int spi_claim_bus(struct spi_slave *slave) |
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{ |
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struct nds_spi_slave *ns = to_nds_spi_slave(slave); |
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return __ae3xx_spi_claim_bus(ns); |
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} |
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void spi_release_bus(struct spi_slave *slave) |
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{ |
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struct nds_spi_slave *ns = to_nds_spi_slave(slave); |
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__ae3xx_spi_release_bus(ns); |
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} |
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, |
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void *data_in, unsigned long flags) |
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{ |
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struct nds_spi_slave *ns = to_nds_spi_slave(slave); |
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return __ae3xx_spi_xfer(ns, bitlen, data_out, data_in, flags); |
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} |
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int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
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{ |
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return bus == 0 && cs < NSPI_MAX_CS_NUM; |
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} |
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void spi_cs_activate(struct spi_slave *slave) |
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{ |
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struct nds_spi_slave *ns = to_nds_spi_slave(slave); |
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__ae3xx_spi_start(ns); |
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} |
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void spi_cs_deactivate(struct spi_slave *slave) |
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{ |
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struct nds_spi_slave *ns = to_nds_spi_slave(slave); |
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__ae3xx_spi_stop(ns); |
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} |
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#else |
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static int ae3xx_spi_set_speed(struct udevice *bus, uint max_hz) |
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{ |
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struct nds_spi_slave *ns = dev_get_priv(bus); |
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debug("%s speed %u\n", __func__, max_hz); |
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ns->freq = max_hz; |
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__ae3xx_spi_set_speed(ns); |
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return 0; |
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} |
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static int ae3xx_spi_set_mode(struct udevice *bus, uint mode) |
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{ |
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struct nds_spi_slave *ns = dev_get_priv(bus); |
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debug("%s mode %u\n", __func__, mode); |
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ns->mode = mode; |
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return 0; |
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} |
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static int ae3xx_spi_claim_bus(struct udevice *dev) |
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{ |
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struct dm_spi_slave_platdata *slave_plat = |
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dev_get_parent_platdata(dev); |
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struct udevice *bus = dev->parent; |
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struct nds_spi_slave *ns = dev_get_priv(bus); |
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if (slave_plat->cs >= ns->num_cs) { |
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printf("Invalid SPI chipselect\n"); |
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return -EINVAL; |
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} |
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return __ae3xx_spi_claim_bus(ns); |
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} |
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static int ae3xx_spi_release_bus(struct udevice *dev) |
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{ |
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struct nds_spi_slave *ns = dev_get_priv(dev->parent); |
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return __ae3xx_spi_release_bus(ns); |
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} |
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static int ae3xx_spi_xfer(struct udevice *dev, unsigned int bitlen, |
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const void *dout, void *din, |
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unsigned long flags) |
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{ |
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struct udevice *bus = dev->parent; |
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struct nds_spi_slave *ns = dev_get_priv(bus); |
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return __ae3xx_spi_xfer(ns, bitlen, dout, din, flags); |
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} |
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static int ae3xx_spi_get_clk(struct udevice *bus) |
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{ |
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struct nds_spi_slave *ns = dev_get_priv(bus); |
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struct clk clk; |
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ulong clk_rate; |
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int ret; |
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ret = clk_get_by_index(bus, 0, &clk); |
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if (ret) |
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return -EINVAL; |
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clk_rate = clk_get_rate(&clk); |
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if (!clk_rate) |
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return -EINVAL; |
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ns->clock = clk_rate; |
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clk_free(&clk); |
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return 0; |
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} |
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static int ae3xx_spi_probe(struct udevice *bus) |
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{ |
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struct nds_spi_slave *ns = dev_get_priv(bus); |
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ns->to = SPI_TIMEOUT; |
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ns->max_transfer_length = MAX_TRANSFER_LEN; |
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ns->mtiming = ns->regs->timing; |
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ae3xx_spi_get_clk(bus); |
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return 0; |
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} |
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static int ae3xx_ofdata_to_platadata(struct udevice *bus) |
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{ |
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struct nds_spi_slave *ns = dev_get_priv(bus); |
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const void *blob = gd->fdt_blob; |
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int node = dev_of_offset(bus); |
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ns->regs = map_physmem(devfdt_get_addr(bus), |
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sizeof(struct ae3xx_spi_regs), |
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MAP_NOCACHE); |
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if (!ns->regs) { |
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printf("%s: could not map device address\n", __func__); |
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return -EINVAL; |
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} |
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ns->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); |
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return 0; |
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} |
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static const struct dm_spi_ops ae3xx_spi_ops = { |
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.claim_bus = ae3xx_spi_claim_bus, |
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.release_bus = ae3xx_spi_release_bus, |
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.xfer = ae3xx_spi_xfer, |
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.set_speed = ae3xx_spi_set_speed, |
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.set_mode = ae3xx_spi_set_mode, |
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}; |
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static const struct udevice_id ae3xx_spi_ids[] = { |
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{ .compatible = "andestech,atcspi200" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(ae3xx_spi) = { |
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.name = "ae3xx_spi", |
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.id = UCLASS_SPI, |
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.of_match = ae3xx_spi_ids, |
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.ops = &ae3xx_spi_ops, |
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.ofdata_to_platdata = ae3xx_ofdata_to_platadata, |
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.priv_auto_alloc_size = sizeof(struct nds_spi_slave), |
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.probe = ae3xx_spi_probe, |
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}; |
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#endif |
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