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@ -38,15 +38,15 @@ |
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#define CFG_MEMTEST_END 0x10000000 |
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#define CFG_HZ 1000 |
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#define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ |
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#define CFG_TIMERBASE 0x13000100 /* Timer1 */ |
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#define CFG_TIMERBASE 0x13000100 /* Timer1 */ |
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
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#define CONFIG_SETUP_MEMORY_TAGS 1 |
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ |
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#undef CONFIG_INIT_CRITICAL |
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#define CONFIG_CM_INIT 1 |
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#define CONFIG_CM_REMAP 1 |
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#define CONFIG_CM_INIT 1 |
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#define CONFIG_CM_REMAP 1 |
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#undef CONFIG_CM_SPD_DETECT |
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/*
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@ -60,36 +60,36 @@ |
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*/ |
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#define CFG_PL010_SERIAL |
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#define CONFIG_CONS_INDEX 0 |
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#define CONFIG_BAUDRATE 38400 |
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#define CONFIG_BAUDRATE 38400 |
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#define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) } |
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
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#define CFG_SERIAL0 0x16000000 |
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#define CFG_SERIAL1 0x17000000 |
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/*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */ |
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/*#define CONFIG_NET_MULTI */ |
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/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ |
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/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ |
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#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) |
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#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) |
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
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#include <cmd_confdefs.h> |
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#define CONFIG_BOOTDELAY 2 |
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" |
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#define CONFIG_BOOTCOMMAND "" |
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#define CONFIG_BOOTDELAY 2 |
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" |
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#define CONFIG_BOOTCOMMAND "" |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CFG_LONGHELP /* undef to save memory */ |
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#define CFG_LONGHELP /* undef to save memory */ |
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#define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ |
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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/* Print Buffer Size */ |
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
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#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ |
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@ -108,11 +108,11 @@ |
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/*-----------------------------------------------------------------------
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* Physical Memory Map |
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*/ |
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
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#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ |
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
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#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ |
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
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#define CFG_FLASH_BASE 0x24000000 |
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#define CFG_FLASH_BASE 0x24000000 |
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/*-----------------------------------------------------------------------
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* FLASH and environment organization |
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@ -123,8 +123,8 @@ |
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/* timeout values are in ticks */ |
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#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ |
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#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ |
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#define CFG_MAX_FLASH_SECT 128 |
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#define CFG_ENV_SIZE 32768 |
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#define CFG_MAX_FLASH_SECT 128 |
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#define CFG_ENV_SIZE 32768 |
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#define PHYS_FLASH_1 (CFG_FLASH_BASE) |
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@ -134,35 +134,35 @@ |
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/*#define CONFIG_PCI /--* include pci support */ |
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#undef CONFIG_PCI_PNP |
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
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#define DEBUG |
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#define CONFIG_EEPRO100 |
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
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#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 |
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#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 |
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#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 |
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/* PCI Base area */ |
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#define INTEGRATOR_PCI_BASE 0x40000000 |
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#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF |
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/* memory map as seen by the CPU on the local bus */ |
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#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ |
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#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ |
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#define CPU_PCI_IO_SIZE 0x10000 |
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#define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */ |
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#define CPU_PCI_CNFG_SIZE 0x1000000 |
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#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ |
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#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ |
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/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */ |
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#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ |
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#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ |
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/* unused (128-16)M from B1000000-B7FFFFFF */ |
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#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ |
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#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ |
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/* unused ((128-16)M - 64K) from XXX */ |
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#define PCI_V3_BASE 0x62000000 |
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#define PCI_V3_BASE 0x62000000 |
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/* V3 PCI bridge controller */ |
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#define V3_BASE 0x62000000 /* V360EPC registers */ |
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@ -171,97 +171,97 @@ |
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#define PCI_ENET0_MEMADDR (PCI_MEM_BASE) |
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#define V3_PCI_VENDOR 0x00000000 |
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#define V3_PCI_DEVICE 0x00000002 |
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#define V3_PCI_CMD 0x00000004 |
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#define V3_PCI_STAT 0x00000006 |
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#define V3_PCI_CC_REV 0x00000008 |
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#define V3_PCI_HDR_CF 0x0000000C |
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#define V3_PCI_IO_BASE 0x00000010 |
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#define V3_PCI_BASE0 0x00000014 |
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#define V3_PCI_BASE1 0x00000018 |
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#define V3_PCI_SUB_VENDOR 0x0000002C |
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#define V3_PCI_SUB_ID 0x0000002E |
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#define V3_PCI_ROM 0x00000030 |
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#define V3_PCI_BPARAM 0x0000003C |
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#define V3_PCI_MAP0 0x00000040 |
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#define V3_PCI_MAP1 0x00000044 |
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#define V3_PCI_INT_STAT 0x00000048 |
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#define V3_PCI_INT_CFG 0x0000004C |
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#define V3_LB_BASE0 0x00000054 |
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#define V3_LB_BASE1 0x00000058 |
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#define V3_LB_MAP0 0x0000005E |
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#define V3_LB_MAP1 0x00000062 |
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#define V3_LB_BASE2 0x00000064 |
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#define V3_LB_MAP2 0x00000066 |
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#define V3_LB_SIZE 0x00000068 |
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#define V3_LB_IO_BASE 0x0000006E |
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#define V3_FIFO_CFG 0x00000070 |
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#define V3_FIFO_PRIORITY 0x00000072 |
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#define V3_FIFO_STAT 0x00000074 |
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#define V3_LB_ISTAT 0x00000076 |
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#define V3_LB_IMASK 0x00000077 |
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#define V3_SYSTEM 0x00000078 |
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#define V3_LB_CFG 0x0000007A |
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#define V3_PCI_CFG 0x0000007C |
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#define V3_DMA_PCI_ADR0 0x00000080 |
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#define V3_DMA_PCI_ADR1 0x00000090 |
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#define V3_DMA_LOCAL_ADR0 0x00000084 |
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#define V3_DMA_LOCAL_ADR1 0x00000094 |
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#define V3_DMA_LENGTH0 0x00000088 |
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#define V3_DMA_LENGTH1 0x00000098 |
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#define V3_DMA_CSR0 0x0000008B |
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#define V3_DMA_CSR1 0x0000009B |
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#define V3_DMA_CTLB_ADR0 0x0000008C |
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#define V3_DMA_CTLB_ADR1 0x0000009C |
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#define V3_DMA_DELAY 0x000000E0 |
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#define V3_MAIL_DATA 0x000000C0 |
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#define V3_PCI_MAIL_IEWR 0x000000D0 |
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#define V3_PCI_MAIL_IERD 0x000000D2 |
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#define V3_LB_MAIL_IEWR 0x000000D4 |
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#define V3_LB_MAIL_IERD 0x000000D6 |
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#define V3_MAIL_WR_STAT 0x000000D8 |
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#define V3_MAIL_RD_STAT 0x000000DA |
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#define V3_QBA_MAP 0x000000DC |
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#define V3_PCI_VENDOR 0x00000000 |
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#define V3_PCI_DEVICE 0x00000002 |
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#define V3_PCI_CMD 0x00000004 |
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#define V3_PCI_STAT 0x00000006 |
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#define V3_PCI_CC_REV 0x00000008 |
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#define V3_PCI_HDR_CF 0x0000000C |
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#define V3_PCI_IO_BASE 0x00000010 |
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#define V3_PCI_BASE0 0x00000014 |
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#define V3_PCI_BASE1 0x00000018 |
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#define V3_PCI_SUB_VENDOR 0x0000002C |
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#define V3_PCI_SUB_ID 0x0000002E |
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#define V3_PCI_ROM 0x00000030 |
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#define V3_PCI_BPARAM 0x0000003C |
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#define V3_PCI_MAP0 0x00000040 |
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#define V3_PCI_MAP1 0x00000044 |
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#define V3_PCI_INT_STAT 0x00000048 |
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#define V3_PCI_INT_CFG 0x0000004C |
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#define V3_LB_BASE0 0x00000054 |
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#define V3_LB_BASE1 0x00000058 |
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#define V3_LB_MAP0 0x0000005E |
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#define V3_LB_MAP1 0x00000062 |
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#define V3_LB_BASE2 0x00000064 |
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#define V3_LB_MAP2 0x00000066 |
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#define V3_LB_SIZE 0x00000068 |
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#define V3_LB_IO_BASE 0x0000006E |
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#define V3_FIFO_CFG 0x00000070 |
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#define V3_FIFO_PRIORITY 0x00000072 |
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#define V3_FIFO_STAT 0x00000074 |
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#define V3_LB_ISTAT 0x00000076 |
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#define V3_LB_IMASK 0x00000077 |
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#define V3_SYSTEM 0x00000078 |
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#define V3_LB_CFG 0x0000007A |
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#define V3_PCI_CFG 0x0000007C |
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#define V3_DMA_PCI_ADR0 0x00000080 |
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#define V3_DMA_PCI_ADR1 0x00000090 |
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#define V3_DMA_LOCAL_ADR0 0x00000084 |
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#define V3_DMA_LOCAL_ADR1 0x00000094 |
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#define V3_DMA_LENGTH0 0x00000088 |
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#define V3_DMA_LENGTH1 0x00000098 |
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#define V3_DMA_CSR0 0x0000008B |
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#define V3_DMA_CSR1 0x0000009B |
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#define V3_DMA_CTLB_ADR0 0x0000008C |
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#define V3_DMA_CTLB_ADR1 0x0000009C |
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#define V3_DMA_DELAY 0x000000E0 |
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#define V3_MAIL_DATA 0x000000C0 |
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#define V3_PCI_MAIL_IEWR 0x000000D0 |
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#define V3_PCI_MAIL_IERD 0x000000D2 |
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#define V3_LB_MAIL_IEWR 0x000000D4 |
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#define V3_LB_MAIL_IERD 0x000000D6 |
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#define V3_MAIL_WR_STAT 0x000000D8 |
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#define V3_MAIL_RD_STAT 0x000000DA |
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#define V3_QBA_MAP 0x000000DC |
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/* SYSTEM register bits */ |
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#define V3_SYSTEM_M_RST_OUT (1 << 15) |
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#define V3_SYSTEM_M_LOCK (1 << 14) |
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#define V3_SYSTEM_M_RST_OUT (1 << 15) |
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#define V3_SYSTEM_M_LOCK (1 << 14) |
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/* PCI_CFG bits */ |
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#define V3_PCI_CFG_M_RETRY_EN (1 << 10) |
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#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) |
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#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) |
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#define V3_PCI_CFG_M_RETRY_EN (1 << 10) |
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#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) |
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#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) |
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/* PCI MAP register bits (PCI -> Local bus) */ |
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#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 |
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#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) |
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#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) |
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#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) |
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#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 |
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#define V3_PCI_MAP_M_REG_EN (1 << 1) |
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#define V3_PCI_MAP_M_ENABLE (1 << 0) |
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#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 |
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#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) |
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#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) |
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#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) |
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#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 |
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#define V3_PCI_MAP_M_REG_EN (1 << 1) |
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#define V3_PCI_MAP_M_ENABLE (1 << 0) |
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/* 9 => 512M window size */ |
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#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 |
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#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 |
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/* A => 1024M window size */ |
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#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 |
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#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 |
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/* LB_BASE register bits (Local bus -> PCI) */ |
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#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 |
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#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) |
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#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 |
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#define V3_LB_BASE_M_PREFETCH (1 << 3) |
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#define V3_LB_BASE_M_ENABLE (1 << 0) |
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#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 |
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#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) |
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#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 |
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#define V3_LB_BASE_M_PREFETCH (1 << 3) |
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#define V3_LB_BASE_M_ENABLE (1 << 0) |
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/* PCI COMMAND REGISTER bits */ |
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#define V3_COMMAND_M_FBB_EN (1 << 9) |
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#define V3_COMMAND_M_SERR_EN (1 << 8) |
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#define V3_COMMAND_M_PAR_EN (1 << 6) |
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#define V3_COMMAND_M_MASTER_EN (1 << 2) |
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#define V3_COMMAND_M_MEM_EN (1 << 1) |
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#define V3_COMMAND_M_IO_EN (1 << 0) |
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#define V3_COMMAND_M_FBB_EN (1 << 9) |
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#define V3_COMMAND_M_SERR_EN (1 << 8) |
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#define V3_COMMAND_M_PAR_EN (1 << 6) |
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#define V3_COMMAND_M_MASTER_EN (1 << 2) |
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#define V3_COMMAND_M_MEM_EN (1 << 1) |
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#define V3_COMMAND_M_IO_EN (1 << 0) |
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#define INTEGRATOR_SC_BASE 0x11000000 |
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#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 |
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@ -280,38 +280,37 @@ |
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/* CM registers common to all integrator/CP CMs */ |
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#define OS_CTRL 0x0000000C |
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#define CMMASK_REMAP 0x00000005 /* Set remap & led */ |
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#define CMMASK_REMAP 0x00000005 /* Set remap & led */ |
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#define CMMASK_RESET 0x00000008 |
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#define OS_LOCK 0x00000014 |
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#define CMVAL_LOCK 0x0000A000 /* Locking value */ |
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#define CMMASK_LOCK 0x0000005F /* Locking value */ |
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#define CMVAL_LOCK 0x0000A000 /* Locking value */ |
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#define CMMASK_LOCK 0x0000005F /* Locking value */ |
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#define CMVAL_UNLOCK 0x00000000 /* Any value != CM_LOCKVAL */ |
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#define OS_SDRAM 0x00000020 |
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#define OS_INIT 0x00000024 |
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#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */ |
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#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */ |
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#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */ |
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#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */ |
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#ifdef CONFIG_CM_SPD_DETECT |
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#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */ |
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#endif |
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#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) |
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#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual |
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* - PLL test clock bypassed |
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* - bus clock ratio 2 |
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* - little endian |
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* - vectors at zero |
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*/ |
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#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual |
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* - PLL test clock bypassed |
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* - bus clock ratio 2 |
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* - little endian |
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* - vectors at zero |
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*/ |
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#endif /* CM1022xx */ |
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#define CMMASK_LE 0x00000008 /* little endian */ |
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#define CMMASK_LE 0x00000008 /* little endian */ |
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#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6 |
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* - divisor/ratio b00000001 |
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* bx |
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* - HCLKDIV b000 |
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* bxx |
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* - PLL BYPASS b00 |
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*/ |
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#endif /* __CONFIG_H */ |
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* - divisor/ratio b00000001 |
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* bx |
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* - HCLKDIV b000 |
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* bxx |
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* - PLL BYPASS b00 |
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*/ |
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#endif /* __CONFIG_H */ |
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Wolfgang Denk
20 years ago