This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.netmaster
Sergey Kostanbaev
11 years ago
committed by
Albert ARIBAUD
parent
c0c374024d
commit
7237d22baa
@ -0,0 +1,11 @@ |
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#
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# (C) Copyright 2013
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# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
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#
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# * SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := edb93xx.o
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@ -0,0 +1,382 @@ |
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/*
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* Board initialization for EP93xx |
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* |
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* Copyright (C) 2013 |
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* Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru> |
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* |
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* Copyright (C) 2009 |
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* Matthias Kaehlcke <matthias <at> kaehlcke.net> |
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* |
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* (C) Copyright 2002 2003 |
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* Network Audio Technologies, Inc. <www.netaudiotech.com> |
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* Adam Bezanson <bezanson <at> netaudiotech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/io.h> |
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#include <asm/arch/ep93xx.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* usb_div: 4, nbyp2: 1, pll2_en: 1 |
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* pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, |
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* pll2_x2: 384000000.000000, pll2_out: 192000000.000000 |
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*/ |
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#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ |
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24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
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24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
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1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
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SYSCON_CLKSET2_PLL2_EN | \
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SYSCON_CLKSET2_NBYP2 | \
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3 << SYSCON_CLKSET2_USB_DIV_SHIFT) |
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#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ |
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SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
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1 << SMC_BCR_MW_SHIFT) |
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/* delay execution before timers are initialized */ |
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static inline void early_udelay(uint32_t usecs) |
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{ |
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/* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ |
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register uint32_t loops = (usecs * 1000) / 20; |
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__asm__ volatile ("1:\n" |
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"subs %0, %1, #1\n" |
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"bne 1b" : "=r" (loops) : "0" (loops)); |
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} |
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#ifndef CONFIG_EP93XX_NO_FLASH_CFG |
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static void flash_cfg(void) |
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{ |
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struct smc_regs *smc = (struct smc_regs *)SMC_BASE; |
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writel(SMC_BCR6_VALUE, &smc->bcr6); |
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} |
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#else |
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#define flash_cfg() |
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#endif |
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int board_init(void) |
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{ |
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/*
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* Setup PLL2, PPL1 has been set during lowlevel init |
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*/ |
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; |
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writel(CLKSET2_VAL, &syscon->clkset2); |
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/*
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* the user's guide recommends to wait at least 1 ms for PLL2 to |
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* stabilize |
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*/ |
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early_udelay(1000); |
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/* Go to Async mode */ |
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__asm__ volatile ("mrc p15, 0, r0, c1, c0, 0"); |
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__asm__ volatile ("orr r0, r0, #0xc0000000"); |
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__asm__ volatile ("mcr p15, 0, r0, c1, c0, 0"); |
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icache_enable(); |
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#ifdef USE_920T_MMU |
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dcache_enable(); |
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#endif |
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/* Machine number, as defined in linux/arch/arm/tools/mach-types */ |
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gd->bd->bi_arch_number = CONFIG_MACH_TYPE; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; |
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/* We have a console */ |
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gd->have_console = 1; |
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enable_interrupts(); |
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flash_cfg(); |
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green_led_on(); |
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red_led_off(); |
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return 0; |
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} |
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int board_early_init_f(void) |
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{ |
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/*
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* set UARTBAUD bit to drive UARTs with 14.7456MHz instead of |
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* 14.7456/2 MHz |
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*/ |
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; |
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writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt); |
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return 0; |
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} |
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int board_eth_init(bd_t *bd) |
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{ |
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return ep93xx_eth_initialize(0, MAC_BASE); |
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} |
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static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt, |
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unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS]) |
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{ |
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if (dram_bank_cnt == 1) { |
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dram_bank_base[0] = PHYS_SDRAM_1; |
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} else { |
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/* Table lookup for holes in address space. Maximum memory
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* for the single SDCS may be up to 256Mb. We start scanning |
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* banks from 1Mb, so it could be up to 128 banks theoretically. |
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* We need at maximum 7 bits for the loockup, 8 slots is |
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* enough for the worst case. |
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*/ |
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unsigned tbl[8]; |
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unsigned i = dram_bank_cnt / 2; |
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unsigned j = 0x00100000; /* 1 Mb */ |
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unsigned *ptbl = tbl; |
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do { |
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while (!(dram_addr_mask & j)) { |
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j <<= 1; |
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} |
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*ptbl++ = j; |
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j <<= 1; |
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i >>= 1; |
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} while (i != 0); |
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for (i = dram_bank_cnt, j = 0; |
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(i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) { |
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unsigned addr = PHYS_SDRAM_1; |
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unsigned k; |
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unsigned bit; |
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for (k = 0, bit = 1; k < 8; k++, bit <<= 1) { |
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if (bit & j) |
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addr |= tbl[k]; |
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} |
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dram_bank_base[j] = addr; |
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} |
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} |
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} |
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/* called in board_init_f (before relocation) */ |
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static unsigned dram_init_banksize_int(int print) |
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{ |
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/*
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* Collect information of banks that has been filled during lowlevel |
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* initialization |
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*/ |
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unsigned i; |
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unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS]; |
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unsigned dram_total = 0; |
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unsigned dram_bank_size = *(unsigned *) |
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(PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE); |
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unsigned dram_addr_mask = *(unsigned *) |
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(PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK); |
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unsigned dram_bank_cnt = *(unsigned *) |
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(PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT); |
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dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base); |
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for (i = 0; i < dram_bank_cnt; i++) { |
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gd->bd->bi_dram[i].start = dram_bank_base[i]; |
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gd->bd->bi_dram[i].size = dram_bank_size; |
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dram_total += dram_bank_size; |
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} |
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for (; i < CONFIG_NR_DRAM_BANKS; i++) { |
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gd->bd->bi_dram[i].start = 0; |
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gd->bd->bi_dram[i].size = 0; |
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} |
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if (print) { |
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printf("DRAM mask: %08x\n", dram_addr_mask); |
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printf("DRAM total %u banks:\n", dram_bank_cnt); |
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printf("bank base-address size\n"); |
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if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) { |
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printf("WARNING! UBoot was configured for %u banks,\n" |
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"but %u has been found. " |
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"Supressing extra memory banks\n", |
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CONFIG_NR_DRAM_BANKS, dram_bank_cnt); |
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dram_bank_cnt = CONFIG_NR_DRAM_BANKS; |
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} |
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for (i = 0; i < dram_bank_cnt; i++) { |
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printf(" %u %08x %08x\n", |
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i, dram_bank_base[i], dram_bank_size); |
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} |
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printf(" ------------------------------------------\n" |
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"Total %9d\n\n", |
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dram_total); |
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} |
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return dram_total; |
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} |
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void dram_init_banksize(void) |
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{ |
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dram_init_banksize_int(0); |
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} |
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/* called in board_init_f (before relocation) */ |
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int dram_init(void) |
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{ |
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; |
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unsigned sec_id = readl(SECURITY_EXTENSIONID); |
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unsigned chip_id = readl(&syscon->chipid); |
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printf("CPU: Cirrus Logic "); |
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switch (sec_id & 0x000001FE) { |
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case 0x00000008: |
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printf("EP9301"); |
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break; |
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case 0x00000004: |
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printf("EP9307"); |
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break; |
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case 0x00000002: |
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printf("EP931x"); |
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break; |
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case 0x00000000: |
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printf("EP9315"); |
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break; |
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default: |
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printf("<unknown>"); |
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break; |
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} |
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printf(" - Rev. "); |
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switch (chip_id & 0xF0000000) { |
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case 0x00000000: |
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printf("A"); |
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break; |
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case 0x10000000: |
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printf("B"); |
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break; |
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case 0x20000000: |
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printf("C"); |
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break; |
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case 0x30000000: |
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printf("D0"); |
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break; |
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case 0x40000000: |
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printf("D1"); |
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break; |
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case 0x50000000: |
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printf("E0"); |
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break; |
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case 0x60000000: |
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printf("E1"); |
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break; |
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case 0x70000000: |
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printf("E2"); |
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break; |
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default: |
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printf("?"); |
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break; |
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} |
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printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id); |
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gd->ram_size = dram_init_banksize_int(1); |
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return 0; |
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} |
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#ifdef CONFIG_EP93XX_SPI |
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#include <spi.h> |
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/*
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* EGIO0-EGIPO7 -> port A |
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* EGIO8-EGIP15 -> port B |
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*/ |
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static void ep93xx_set_epgio(unsigned num) |
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{ |
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struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; |
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if (num < 8) |
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writel(readl(®s->padr) | (1<<num), ®s->padr); |
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else |
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writel(readl(®s->pbdr) | (1<<(num-8)), ®s->pbdr); |
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} |
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static void ep93xx_clear_epgio(unsigned num) |
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{ |
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struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; |
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if (num < 8) |
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writel(readl(®s->padr) & (~(1<<num)), ®s->padr); |
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else |
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writel(readl(®s->pbdr) & (~(1<<(num-8))), ®s->pbdr); |
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} |
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static void ep93xx_dir_epgio_out(unsigned num) |
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{ |
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struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; |
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if (num < 8) |
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writel(readl(®s->paddr) | (1<<num), ®s->paddr); |
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else |
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writel(readl(®s->pbddr) | (1<<(num-8)), ®s->pbddr); |
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} |
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int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
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{ |
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if (bus == 0 && cs < 16) |
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return 1; |
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return 0; |
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} |
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void spi_cs_activate(struct spi_slave *slave) |
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{ |
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ep93xx_clear_epgio(slave->cs); |
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} |
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void spi_cs_deactivate(struct spi_slave *slave) |
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{ |
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ep93xx_set_epgio(slave->cs); |
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} |
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#ifdef CONFIG_MMC_SPI |
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#include <mmc.h> |
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#ifndef CONFIG_MMC_SPI_CS_EPGIO |
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# define CONFIG_MMC_SPI_CS_EPGIO 4 |
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#endif |
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#ifndef CONFIG_MMC_SPI_SPEED |
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# define CONFIG_MMC_SPI_SPEED 25000000 |
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#endif |
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#ifndef CONFIG_MMC_SPI_MODE |
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# define CONFIG_MMC_SPI_MODE SPI_MODE_0 |
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#endif |
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int board_mmc_init(bd_t *bis) |
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{ |
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struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; |
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ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO); |
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ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO); |
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#ifdef CONFIG_MMC_SPI_POWER_EGPIO |
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ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO); |
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ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO); |
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#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO) |
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ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO); |
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ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO); |
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#endif |
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struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO, |
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CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE); |
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if (!mmc) { |
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printf("Failed to create MMC Device\n"); |
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return 1; |
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} |
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mmc_init(mmc); |
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return 0; |
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} |
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#endif /* CONFIG_MMC_SPI */ |
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#endif /* CONFIG_EP93XX_SPI */ |
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@ -0,0 +1,115 @@ |
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/* |
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* |
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* Copyright (C) 2013 |
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* Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru> |
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* |
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* Copyright (c) 2004-2008 Texas Instruments |
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* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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. = 0x00000000; |
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. = ALIGN(4); |
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.text : { |
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*(.__image_copy_start) |
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arch/arm/cpu/arm920t/start.o (.text*) |
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. = 0x1000; |
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LONG(0x53555243) |
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*(.text*) |
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} |
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. = ALIGN(4); |
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.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
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. = ALIGN(4); |
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.data : { |
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*(.data*) |
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} |
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. = ALIGN(4); |
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. = .; |
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. = ALIGN(4); |
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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. = ALIGN(4); |
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.image_copy_end : |
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{ |
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*(.__image_copy_end) |
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} |
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.rel_dyn_start : |
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{ |
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*(.__rel_dyn_start) |
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} |
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.rel.dyn : { |
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*(.rel*) |
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} |
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.rel_dyn_end : |
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{ |
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*(.__rel_dyn_end) |
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} |
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|
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.end : |
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{ |
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*(.__end) |
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} |
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_image_binary_end = .; |
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|
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/* |
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* Deprecated: this MMU section is used by pxa at present but |
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* should not be used by new boards/CPUs. |
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*/ |
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. = ALIGN(4096); |
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.mmutable : { |
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*(.mmutable) |
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} |
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|
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/* |
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* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c |
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* __bss_base and __bss_limit are for linker only (overlay ordering) |
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*/ |
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|
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.bss_start __rel_dyn_start (OVERLAY) : { |
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KEEP(*(.__bss_start)); |
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__bss_base = .; |
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} |
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|
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.bss __bss_base (OVERLAY) : { |
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*(.bss*) |
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. = ALIGN(4); |
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__bss_limit = .; |
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} |
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|
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.bss_end __bss_limit (OVERLAY) : { |
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KEEP(*(.__bss_end)); |
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} |
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|
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.dynsym _image_binary_end : { *(.dynsym) } |
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.dynbss : { *(.dynbss) } |
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.dynstr : { *(.dynstr*) } |
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.dynamic : { *(.dynamic*) } |
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.plt : { *(.plt*) } |
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.interp : { *(.interp*) } |
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.gnu.hash : { *(.gnu.hash) } |
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.gnu : { *(.gnu*) } |
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.ARM.exidx : { *(.ARM.exidx*) } |
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.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } |
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} |
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@ -0,0 +1,274 @@ |
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/*
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* SPI Driver for EP93xx |
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* |
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* Copyright (C) 2013 Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru> |
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* |
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* Inspired form linux kernel driver and atmel uboot driver |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <spi.h> |
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#include <malloc.h> |
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|
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#include <asm/io.h> |
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|
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#include <asm/arch/ep93xx.h> |
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|
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#define BIT(x) (1<<(x)) |
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#define SSPBASE SPI_BASE |
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|
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#define SSPCR0 0x0000 |
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#define SSPCR0_MODE_SHIFT 6 |
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#define SSPCR0_SCR_SHIFT 8 |
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#define SSPCR0_SPH BIT(7) |
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#define SSPCR0_SPO BIT(6) |
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#define SSPCR0_FRF_SPI 0 |
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#define SSPCR0_DSS_8BIT 7 |
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|
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#define SSPCR1 0x0004 |
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#define SSPCR1_RIE BIT(0) |
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#define SSPCR1_TIE BIT(1) |
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#define SSPCR1_RORIE BIT(2) |
||||
#define SSPCR1_LBM BIT(3) |
||||
#define SSPCR1_SSE BIT(4) |
||||
#define SSPCR1_MS BIT(5) |
||||
#define SSPCR1_SOD BIT(6) |
||||
|
||||
#define SSPDR 0x0008 |
||||
|
||||
#define SSPSR 0x000c |
||||
#define SSPSR_TFE BIT(0) |
||||
#define SSPSR_TNF BIT(1) |
||||
#define SSPSR_RNE BIT(2) |
||||
#define SSPSR_RFF BIT(3) |
||||
#define SSPSR_BSY BIT(4) |
||||
#define SSPCPSR 0x0010 |
||||
|
||||
#define SSPIIR 0x0014 |
||||
#define SSPIIR_RIS BIT(0) |
||||
#define SSPIIR_TIS BIT(1) |
||||
#define SSPIIR_RORIS BIT(2) |
||||
#define SSPICR SSPIIR |
||||
|
||||
#define SSPCLOCK 14745600 |
||||
#define SSP_MAX_RATE (SSPCLOCK / 2) |
||||
#define SSP_MIN_RATE (SSPCLOCK / (254 * 256)) |
||||
|
||||
/* timeout in milliseconds */ |
||||
#define SPI_TIMEOUT 5 |
||||
/* maximum depth of RX/TX FIFO */ |
||||
#define SPI_FIFO_SIZE 8 |
||||
|
||||
struct ep93xx_spi_slave { |
||||
struct spi_slave slave; |
||||
|
||||
unsigned sspcr0; |
||||
unsigned sspcpsr; |
||||
}; |
||||
|
||||
static inline struct ep93xx_spi_slave *to_ep93xx_spi(struct spi_slave *slave) |
||||
{ |
||||
return container_of(slave, struct ep93xx_spi_slave, slave); |
||||
} |
||||
|
||||
void spi_init() |
||||
{ |
||||
} |
||||
|
||||
static inline void ep93xx_spi_write_u8(u16 reg, u8 value) |
||||
{ |
||||
writel(value, (unsigned int *)(SSPBASE + reg)); |
||||
} |
||||
|
||||
static inline u8 ep93xx_spi_read_u8(u16 reg) |
||||
{ |
||||
return readl((unsigned int *)(SSPBASE + reg)); |
||||
} |
||||
|
||||
static inline void ep93xx_spi_write_u16(u16 reg, u16 value) |
||||
{ |
||||
writel(value, (unsigned int *)(SSPBASE + reg)); |
||||
} |
||||
|
||||
static inline u16 ep93xx_spi_read_u16(u16 reg) |
||||
{ |
||||
return (u16)readl((unsigned int *)(SSPBASE + reg)); |
||||
} |
||||
|
||||
static int ep93xx_spi_init_hw(unsigned int rate, unsigned int mode, |
||||
struct ep93xx_spi_slave *slave) |
||||
{ |
||||
unsigned cpsr, scr; |
||||
|
||||
if (rate > SSP_MAX_RATE) |
||||
rate = SSP_MAX_RATE; |
||||
|
||||
if (rate < SSP_MIN_RATE) |
||||
return -1; |
||||
|
||||
/* Calculate divisors so that we can get speed according the
|
||||
* following formula: |
||||
* rate = spi_clock_rate / (cpsr * (1 + scr)) |
||||
* |
||||
* cpsr must be even number and starts from 2, scr can be any number |
||||
* between 0 and 255. |
||||
*/ |
||||
for (cpsr = 2; cpsr <= 254; cpsr += 2) { |
||||
for (scr = 0; scr <= 255; scr++) { |
||||
if ((SSPCLOCK / (cpsr * (scr + 1))) <= rate) { |
||||
/* Set CHPA and CPOL, SPI format and 8bit */ |
||||
unsigned sspcr0 = (scr << SSPCR0_SCR_SHIFT) | |
||||
SSPCR0_FRF_SPI | SSPCR0_DSS_8BIT; |
||||
if (mode & SPI_CPHA) |
||||
sspcr0 |= SSPCR0_SPH; |
||||
if (mode & SPI_CPOL) |
||||
sspcr0 |= SSPCR0_SPO; |
||||
|
||||
slave->sspcr0 = sspcr0; |
||||
slave->sspcpsr = cpsr; |
||||
return 0; |
||||
} |
||||
} |
||||
} |
||||
|
||||
return -1; |
||||
} |
||||
|
||||
void spi_set_speed(struct spi_slave *slave, unsigned int hz) |
||||
{ |
||||
struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); |
||||
|
||||
unsigned int mode = 0; |
||||
if (as->sspcr0 & SSPCR0_SPH) |
||||
mode |= SPI_CPHA; |
||||
if (as->sspcr0 & SSPCR0_SPO) |
||||
mode |= SPI_CPOL; |
||||
|
||||
ep93xx_spi_init_hw(hz, mode, as); |
||||
} |
||||
|
||||
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
||||
unsigned int max_hz, unsigned int mode) |
||||
{ |
||||
struct ep93xx_spi_slave *as; |
||||
|
||||
if (!spi_cs_is_valid(bus, cs)) |
||||
return NULL; |
||||
|
||||
as = spi_alloc_slave(struct ep93xx_spi_slave, bus, cs); |
||||
if (!as) |
||||
return NULL; |
||||
|
||||
if (ep93xx_spi_init_hw(max_hz, mode, as)) { |
||||
free(as); |
||||
return NULL; |
||||
} |
||||
|
||||
return &as->slave; |
||||
} |
||||
|
||||
void spi_free_slave(struct spi_slave *slave) |
||||
{ |
||||
struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); |
||||
|
||||
free(as); |
||||
} |
||||
|
||||
int spi_claim_bus(struct spi_slave *slave) |
||||
{ |
||||
struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); |
||||
|
||||
/* Enable the SPI hardware */ |
||||
ep93xx_spi_write_u8(SSPCR1, SSPCR1_SSE); |
||||
|
||||
|
||||
ep93xx_spi_write_u8(SSPCPSR, as->sspcpsr); |
||||
ep93xx_spi_write_u16(SSPCR0, as->sspcr0); |
||||
|
||||
debug("Select CS:%d SSPCPSR=%02x SSPCR0=%04x\n", |
||||
slave->cs, as->sspcpsr, as->sspcr0); |
||||
return 0; |
||||
} |
||||
|
||||
void spi_release_bus(struct spi_slave *slave) |
||||
{ |
||||
/* Disable the SPI hardware */ |
||||
ep93xx_spi_write_u8(SSPCR1, 0); |
||||
} |
||||
|
||||
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, |
||||
const void *dout, void *din, unsigned long flags) |
||||
{ |
||||
unsigned int len_tx; |
||||
unsigned int len_rx; |
||||
unsigned int len; |
||||
u32 status; |
||||
const u8 *txp = dout; |
||||
u8 *rxp = din; |
||||
u8 value; |
||||
|
||||
debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n", |
||||
slave->bus, slave->cs, (uint *)dout, (uint *)din, bitlen); |
||||
|
||||
|
||||
if (bitlen == 0) |
||||
/* Finish any previously submitted transfers */ |
||||
goto out; |
||||
|
||||
if (bitlen % 8) { |
||||
/* Errors always terminate an ongoing transfer */ |
||||
flags |= SPI_XFER_END; |
||||
goto out; |
||||
} |
||||
|
||||
len = bitlen / 8; |
||||
|
||||
|
||||
if (flags & SPI_XFER_BEGIN) { |
||||
/* Empty RX FIFO */ |
||||
while ((ep93xx_spi_read_u8(SSPSR) & SSPSR_RNE)) |
||||
ep93xx_spi_read_u8(SSPDR); |
||||
|
||||
spi_cs_activate(slave); |
||||
} |
||||
|
||||
for (len_tx = 0, len_rx = 0; len_rx < len; ) { |
||||
status = ep93xx_spi_read_u8(SSPSR); |
||||
|
||||
if ((len_tx < len) && (status & SSPSR_TNF)) { |
||||
if (txp) |
||||
value = *txp++; |
||||
else |
||||
value = 0xff; |
||||
|
||||
ep93xx_spi_write_u8(SSPDR, value); |
||||
len_tx++; |
||||
} |
||||
|
||||
if (status & SSPSR_RNE) { |
||||
value = ep93xx_spi_read_u8(SSPDR); |
||||
|
||||
if (rxp) |
||||
*rxp++ = value; |
||||
len_rx++; |
||||
} |
||||
} |
||||
|
||||
out: |
||||
if (flags & SPI_XFER_END) { |
||||
/*
|
||||
* Wait until the transfer is completely done before |
||||
* we deactivate CS. |
||||
*/ |
||||
do { |
||||
status = ep93xx_spi_read_u8(SSPSR); |
||||
} while (status & SSPSR_BSY); |
||||
|
||||
spi_cs_deactivate(slave); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,38 @@ |
||||
/*
|
||||
* (C) Copyright 2013 |
||||
* Sergey Kostanbaev < sergey.kostanbaev <at> fairwaves.ru > |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
|
||||
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) |
||||
#include <asm/io.h> |
||||
#include <asm/arch/ep93xx.h> |
||||
|
||||
int usb_cpu_init(void) |
||||
{ |
||||
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; |
||||
unsigned long pwr = readl(&syscon->pwrcnt); |
||||
writel(pwr | SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int usb_cpu_stop(void) |
||||
{ |
||||
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; |
||||
unsigned long pwr = readl(&syscon->pwrcnt); |
||||
writel(pwr & ~SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int usb_cpu_init_fail(void) |
||||
{ |
||||
return usb_cpu_stop(); |
||||
} |
||||
|
||||
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ |
||||
@ -0,0 +1,292 @@ |
||||
/*
|
||||
* U-boot - Configuration file for Cirrus Logic EDB93xx boards |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#ifdef CONFIG_MK_edb9301 |
||||
#define CONFIG_EDB9301 |
||||
#elif defined(CONFIG_MK_edb9302) |
||||
#define CONFIG_EDB9302 |
||||
#elif defined(CONFIG_MK_edb9302a) |
||||
#define CONFIG_EDB9302A |
||||
#elif defined(CONFIG_MK_edb9307) |
||||
#define CONFIG_EDB9307 |
||||
#elif defined(CONFIG_MK_edb9307a) |
||||
#define CONFIG_EDB9307A |
||||
#elif defined(CONFIG_MK_edb9312) |
||||
#define CONFIG_EDB9312 |
||||
#elif defined(CONFIG_MK_edb9315) |
||||
#define CONFIG_EDB9315 |
||||
#elif defined(CONFIG_MK_edb9315a) |
||||
#define CONFIG_EDB9315A |
||||
#else |
||||
#error "no board defined" |
||||
#endif |
||||
|
||||
/* Initial environment and monitor configuration options. */ |
||||
#define CONFIG_BOOTDELAY 2 |
||||
#define CONFIG_CMDLINE_TAG 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp" |
||||
#define CONFIG_BOOTFILE "edb93xx.img" |
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER 1 |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
|
||||
#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds" |
||||
|
||||
|
||||
#ifdef CONFIG_EDB9301 |
||||
#define CONFIG_EP9301 |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301 |
||||
#define CONFIG_SYS_PROMPT "EDB9301> " |
||||
#define CONFIG_ENV_SECT_SIZE 0x00020000 |
||||
#elif defined(CONFIG_EDB9302) |
||||
#define CONFIG_EP9302 |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302 |
||||
#define CONFIG_SYS_PROMPT "EDB9302> " |
||||
#define CONFIG_ENV_SECT_SIZE 0x00020000 |
||||
#elif defined(CONFIG_EDB9302A) |
||||
#define CONFIG_EP9302 |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A |
||||
#define CONFIG_SYS_PROMPT "EDB9302A> " |
||||
#define CONFIG_ENV_SECT_SIZE 0x00020000 |
||||
#elif defined(CONFIG_EDB9307) |
||||
#define CONFIG_EP9307 |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307 |
||||
#define CONFIG_SYS_PROMPT "EDB9307> " |
||||
#define CONFIG_ENV_SECT_SIZE 0x00040000 |
||||
#elif defined(CONFIG_EDB9307A) |
||||
#define CONFIG_EP9307 |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A |
||||
#define CONFIG_SYS_PROMPT "EDB9307A> " |
||||
#define CONFIG_ENV_SECT_SIZE 0x00020000 |
||||
#elif defined(CONFIG_EDB9312) |
||||
#define CONFIG_EP9312 |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312 |
||||
#define CONFIG_SYS_PROMPT "EDB9312> " |
||||
#define CONFIG_ENV_SECT_SIZE 0x00040000 |
||||
#elif defined(CONFIG_EDB9315) |
||||
#define CONFIG_EP9315 |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315 |
||||
#define CONFIG_SYS_PROMPT "EDB9315> " |
||||
#define CONFIG_ENV_SECT_SIZE 0x00040000 |
||||
#elif defined(CONFIG_EDB9315A) |
||||
#define CONFIG_EP9315 |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A |
||||
#define CONFIG_SYS_PROMPT "EDB9315A> " |
||||
#define CONFIG_ENV_SECT_SIZE 0x00020000 |
||||
#else |
||||
#error "no board defined" |
||||
#endif |
||||
|
||||
/* High-level configuration options */ |
||||
#define CONFIG_ARM920T 1 /* This is an ARM920T core... */ |
||||
#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ |
||||
#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */ |
||||
#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ |
||||
|
||||
/* Monitor configuration */ |
||||
#include <config_cmd_default.h> |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_SETGETDCR |
||||
#undef CONFIG_CMD_XIMG |
||||
|
||||
#undef CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_JFFS2 |
||||
|
||||
#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */ |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ |
||||
/* Print buffer size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
/* Boot argument buffer size */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ |
||||
|
||||
/* Serial port hardware configuration */ |
||||
#define CONFIG_PL010_SERIAL |
||||
#define CONFIG_CONS_INDEX 0 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \ |
||||
115200, 230400} |
||||
#define CONFIG_SYS_SERIAL0 0x808C0000 |
||||
#define CONFIG_SYS_SERIAL1 0x808D0000 |
||||
/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
|
||||
(void *)CONFIG_SYS_SERIAL1} */ |
||||
|
||||
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} |
||||
|
||||
/* Status LED */ |
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
#define CONFIG_BOARD_SPECIFIC_LED 1 |
||||
#define STATUS_LED_GREEN 0 |
||||
#define STATUS_LED_RED 1 |
||||
/* Green */ |
||||
#define STATUS_LED_BIT STATUS_LED_GREEN |
||||
#define STATUS_LED_STATE STATUS_LED_ON |
||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
||||
/* Red */ |
||||
#define STATUS_LED_BIT1 STATUS_LED_RED |
||||
#define STATUS_LED_STATE1 STATUS_LED_OFF |
||||
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) |
||||
/* Optional value */ |
||||
#define STATUS_LED_BOOT STATUS_LED_BIT |
||||
|
||||
/* Network hardware configuration */ |
||||
#define CONFIG_DRIVER_EP93XX_MAC |
||||
#define CONFIG_MII_SUPPRESS_PREAMBLE |
||||
#define CONFIG_MII |
||||
#define CONFIG_PHY_ADDR 1 |
||||
#define CONFIG_NET_MULTI |
||||
#undef CONFIG_NETCONSOLE |
||||
|
||||
/* SDRAM configuration */ |
||||
#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ |
||||
defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
|
||||
defined(CONFIG_EDB9315) |
||||
/*
|
||||
* EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 |
||||
* 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set |
||||
* the SROMLL bit on the processor, resulting in this non-contiguous memory map. |
||||
* |
||||
* The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of |
||||
* 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of |
||||
* 64 MB of SDRAM. |
||||
*/ |
||||
|
||||
#define CONFIG_EDB93XX_SDCS3 |
||||
|
||||
#elif defined(CONFIG_EDB9302A) || \ |
||||
defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) |
||||
/*
|
||||
* EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 |
||||
* 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set |
||||
* the SROMLL bit on the processor, resulting in this non-contiguous memory map. |
||||
* |
||||
* The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung |
||||
* K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM. |
||||
*/ |
||||
#define CONFIG_EDB93XX_SDCS0 |
||||
|
||||
#else |
||||
#error "no SDCS configuration for this board" |
||||
#endif |
||||
|
||||
|
||||
#if defined(CONFIG_EDB93XX_SDCS3) |
||||
#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */ |
||||
#define PHYS_SDRAM_1 0x00000000 |
||||
#elif defined(CONFIG_EDB93XX_SDCS0) |
||||
#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */ |
||||
#define PHYS_SDRAM_1 0xc0000000 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_NR_DRAM_BANKS 8 |
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE) |
||||
|
||||
|
||||
/* Must match kernel config */ |
||||
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) |
||||
|
||||
/* Run-time memory allocatons */ |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 |
||||
#define CONFIG_STACKSIZE (128 * 1024) |
||||
|
||||
#if defined(CONFIG_USE_IRQ) |
||||
#define CONFIG_STACKSIZE_IRQ (4 * 1024) |
||||
#define CONFIG_STACKSIZE_FIQ (4 * 1024) |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
* |
||||
* The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at |
||||
* 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit |
||||
* data bus, for a total of 16 MB of CFI-compatible flash. |
||||
* |
||||
* The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at |
||||
* 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit |
||||
* data bus, for a total of 32 MB of CFI-compatible flash. |
||||
* |
||||
* |
||||
* EDB9301/02(a)7a/15a EDB9307/12/15 |
||||
* 0x60000000 - 0x0003FFFF u-boot u-boot |
||||
* 0x60040000 - 0x0005FFFF environment #1 environment #1 |
||||
* 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued) |
||||
* 0x60080000 - 0x0009FFFF unused environment #2 |
||||
* 0x600A0000 - 0x000BFFFF unused environment #2 (continued) |
||||
* 0x600C0000 - 0x00FFFFFF unused unused |
||||
* 0x61000000 - 0x01FFFFFF not present unused |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
|
||||
|
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT (256+8) |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x60000000 |
||||
#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
||||
|
||||
#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */ |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
|
||||
#define CONFIG_ENV_ADDR 0x60040000 |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
||||
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
|
||||
/* Define to enable MMC on SPI support */ |
||||
/* #define CONFIG_EP93XX_SPI_MMC */ |
||||
|
||||
#ifdef CONFIG_EP93XX_SPI_MMC |
||||
#define CONFIG_EP93XX_SPI |
||||
#define CONFIG_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_MMC_SPI |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_MMC_SPI_NPOWER_EGPIO 9 |
||||
#endif |
||||
|
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_USB_OHCI_NEW |
||||
#define CONFIG_USB_OHCI_EP93XX |
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT |
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 |
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci" |
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000 |
||||
|
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_EXT4 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_USB |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_CMD_BOOTZ |
||||
|
||||
/* Define to disable flash configuration*/ |
||||
/* #define CONFIG_EP93XX_NO_FLASH_CFG */ |
||||
|
||||
/* Define this for indusrial rated chips */ |
||||
/* #define CONFIG_EDB93XX_INDUSTRIAL */ |
||||
|
||||
#endif /* !defined (__CONFIG_H) */ |
||||
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Reference in new issue