The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>master
York Sun
9 years ago
parent
9cc2c4713a
commit
7288c2c2b0
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if TARGET_LS2085AQDS |
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config SYS_BOARD |
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default "ls2085aqds" |
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config SYS_VENDOR |
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default "freescale" |
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config SYS_SOC |
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default "fsl-lsch3" |
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config SYS_CONFIG_NAME |
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default "ls2085aqds" |
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endif |
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@ -0,0 +1,7 @@ |
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LS2085A BOARD |
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M: Prabhakar Kushwaha <prabhakar@freescale.com> |
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S: Maintained |
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F: board/freescale/ls2085aqds/ |
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F: board/freescale/ls2085a/ls2085aqds.c |
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F: include/configs/ls2085aqds.h |
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F: configs/ls2085aqds_defconfig |
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@ -0,0 +1,8 @@ |
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#
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# Copyright 2015 Freescale Semiconductor
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += ls2085aqds.o
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obj-y += ddr.o
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@ -0,0 +1,129 @@ |
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Overview |
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-------- |
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The LS2085A Development System (QDS) is a high-performance computing, |
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evaluation, and development platform that supports the QorIQ LS2085A |
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Layerscape Architecture processor. The LS2085AQDS provides validation and |
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SW development platform for the Freescale LS2085A processor series, with |
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a complete debugging environment. |
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|
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LS2085A SoC Overview |
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------------------ |
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The LS2085A integrated multicore processor combines eight ARM Cortex-A57 |
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processor cores with high-performance data path acceleration logic and network |
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and peripheral bus interfaces required for networking, telecom/datacom, |
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wireless infrastructure, and mil/aerospace applications. |
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|
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The LS2085A SoC includes the following function and features: |
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- Eight 64-bit ARM Cortex-A57 CPUs |
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- 1 MB platform cache with ECC |
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- Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support |
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- One secondary 32-bit DDR4 SDRAM memory controller, intended for use by |
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the AIOP |
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- Data path acceleration architecture (DPAA2) incorporating acceleration for |
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the following functions: |
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- Packet parsing, classification, and distribution (WRIOP) |
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- Queue and Hardware buffer management for scheduling, packet sequencing, and |
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congestion management, buffer allocation and de-allocation (QBMan) |
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- Cryptography acceleration (SEC) at up to 10 Gbps |
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- RegEx pattern matching acceleration (PME) at up to 10 Gbps |
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- Decompression/compression acceleration (DCE) at up to 20 Gbps |
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- Accelerated I/O processing (AIOP) at up to 20 Gbps |
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- QDMA engine |
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- 16 SerDes lanes at up to 10.3125 GHz |
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- Ethernet interfaces |
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- Up to eight 10 Gbps Ethernet MACs |
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- Up to eight 1 / 2.5 Gbps Ethernet MACs |
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- High-speed peripheral interfaces |
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- Four PCIe 3.0 controllers, one supporting SR-IOV |
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- Additional peripheral interfaces |
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- Two serial ATA (SATA 3.0) controllers |
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- Two high-speed USB 3.0 controllers with integrated PHY |
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- Enhanced secure digital host controller (eSDXC/eMMC) |
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- Serial peripheral interface (SPI) controller |
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- Quad Serial Peripheral Interface (QSPI) Controller |
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- Four I2C controllers |
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- Two DUARTs |
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- Integrated flash controller (IFC 2.0) supporting NAND and NOR flash |
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- Support for hardware virtualization and partitioning enforcement |
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- QorIQ platform's trust architecture 3.0 |
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- Service processor (SP) provides pre-boot initialization and secure-boot |
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capabilities |
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LS2085AQDS board Overview |
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----------------------- |
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- SERDES Connections, 16 lanes supporting: |
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- PCI Express - 3.0 |
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- SGMII, SGMII 2.5 |
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- QSGMII |
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- SATA 3.0 |
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- XAUI |
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- XFI |
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- DDR Controller |
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- Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four |
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chip-selects and two DIMM connectors. Support is up to 2133MT/s. |
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- One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects |
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and two DIMM connectors. Support is up to 1600MT/s. |
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-IFC/Local Bus |
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- IFC rev. 2.0 implementation supporting Little Endian connection scheme. |
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- One in-socket 128 MB NOR flash 16-bit data bus |
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- One 512 MB NAND flash with ECC support |
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- IFC Test Port |
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- PromJet Port |
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- FPGA connection |
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- USB 3.0 |
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- Two high speed USB 3.0 ports |
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- First USB 3.0 port configured as Host with Type-A connector |
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- Second USB 3.0 port configured as OTG with micro-AB connector |
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- SDHC: PCIe x1 Right Angle connector for supporting following cards |
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- 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only |
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- 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only |
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- 4-bit eMMC Card Rev 4.4 (1.8V only) |
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- 8-bit eMMC Card Rev 4.5 (1.8V only) |
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- SD Card Rev 2.0 and Rev 3.0 |
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- DSPI: 3 high-speed flash Memory for storage |
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- 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) |
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- 8 MB high-speed flash Memory (up to 104 MHz) |
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- 512 MB low-speed flash Memory (up to 40 MHz) |
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- QSPI: via NAND/QSPI Card |
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- 4 I2C controllers |
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- Two SATA onboard connectors |
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- UART |
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- Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s |
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- Two DB9 D-Type connectors supporting one Serial port each |
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- ARM JTAG support |
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Memory map from core's view |
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---------------------------- |
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0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom |
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0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR |
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0x00_1800_0000 .. 0x00_181F_FFFF OCRAM |
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0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 |
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0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 |
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0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 |
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0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 |
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Other addresses are either reserved, or not used directly by u-boot. |
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This list should be updated when more addresses are used. |
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IFC region map from core's view |
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------------------------------- |
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During boot i.e. IFC Region #1:- |
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0x30000000 - 0x37ffffff : 128MB : NOR flash |
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0x38000000 - 0x3BFFFFFF : 64MB : Promjet |
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0x3C000000 - 0x40000000 : 64MB : FPGA etc |
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After relocate to DDR i.e. IFC Region #2:- |
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0x5_1000_0000..0x5_1fff_ffff Memory Hole |
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0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) |
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0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB |
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0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) |
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0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) |
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Booting Options |
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--------------- |
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a) Promjet Boot |
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b) NOR boot |
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c) NAND boot |
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d) SD boot |
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e) QSPI boot |
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@ -0,0 +1,192 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <fsl_ddr_sdram.h> |
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#include <fsl_ddr_dimm_params.h> |
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#include "ddr.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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void fsl_ddr_board_options(memctl_options_t *popts, |
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dimm_params_t *pdimm, |
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unsigned int ctrl_num) |
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{ |
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u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; |
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
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ulong ddr_freq; |
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int slot; |
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if (ctrl_num > 2) { |
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printf("Not supported controller number %d\n", ctrl_num); |
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return; |
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} |
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for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) { |
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if (pdimm[slot].n_ranks) |
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break; |
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} |
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if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR) |
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return; |
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/*
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* we use identical timing for all slots. If needed, change the code |
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* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; |
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*/ |
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if (popts->registered_dimm_en) |
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pbsp = rdimms[ctrl_num]; |
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else |
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pbsp = udimms[ctrl_num]; |
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/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table. |
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*/ |
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ddr_freq = get_ddr_freq(ctrl_num) / 1000000; |
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while (pbsp->datarate_mhz_high) { |
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if (pbsp->n_ranks == pdimm[slot].n_ranks && |
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(pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) { |
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if (ddr_freq <= pbsp->datarate_mhz_high) { |
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popts->clk_adjust = pbsp->clk_adjust; |
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popts->wrlvl_start = pbsp->wrlvl_start; |
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
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goto found; |
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} |
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pbsp_highest = pbsp; |
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} |
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pbsp++; |
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} |
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if (pbsp_highest) { |
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printf("Error: board specific timing not found for data rate %lu MT/s\n" |
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"Trying to use the highest speed (%u) parameters\n", |
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ddr_freq, pbsp_highest->datarate_mhz_high); |
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popts->clk_adjust = pbsp_highest->clk_adjust; |
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popts->wrlvl_start = pbsp_highest->wrlvl_start; |
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
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} else { |
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panic("DIMM is not supported by this board"); |
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} |
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found: |
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" |
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"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", |
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, |
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pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, |
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pbsp->wrlvl_ctl_3); |
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if (ctrl_num == CONFIG_DP_DDR_CTRL) { |
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/* force DDR bus width to 32 bits */ |
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popts->data_bus_width = 1; |
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popts->otf_burst_chop_en = 0; |
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popts->burst_length = DDR_BL8; |
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popts->bstopre = 0; /* enable auto precharge */ |
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/*
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* Layout optimization results byte mapping |
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* Byte 0 -> Byte ECC |
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* Byte 1 -> Byte 3 |
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* Byte 2 -> Byte 2 |
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* Byte 3 -> Byte 1 |
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* Byte ECC -> Byte 0 |
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*/ |
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dq_mapping_0 = pdimm[slot].dq_mapping[0]; |
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dq_mapping_2 = pdimm[slot].dq_mapping[2]; |
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dq_mapping_3 = pdimm[slot].dq_mapping[3]; |
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pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8]; |
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pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9]; |
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pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6]; |
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pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7]; |
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pdimm[slot].dq_mapping[6] = dq_mapping_2; |
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pdimm[slot].dq_mapping[7] = dq_mapping_3; |
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pdimm[slot].dq_mapping[8] = dq_mapping_0; |
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pdimm[slot].dq_mapping[9] = 0; |
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pdimm[slot].dq_mapping[10] = 0; |
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pdimm[slot].dq_mapping[11] = 0; |
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pdimm[slot].dq_mapping[12] = 0; |
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pdimm[slot].dq_mapping[13] = 0; |
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pdimm[slot].dq_mapping[14] = 0; |
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pdimm[slot].dq_mapping[15] = 0; |
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pdimm[slot].dq_mapping[16] = 0; |
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pdimm[slot].dq_mapping[17] = 0; |
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} |
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/* To work at higher than 1333MT/s */ |
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popts->half_strength_driver_enable = 0; |
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/*
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* Write leveling override |
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*/ |
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popts->wrlvl_override = 1; |
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popts->wrlvl_sample = 0x0; /* 32 clocks */ |
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/*
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* Rtt and Rtt_WR override |
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*/ |
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popts->rtt_override = 0; |
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/* Enable ZQ calibration */ |
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popts->zq_en = 1; |
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if (ddr_freq < 2350) { |
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | |
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DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); |
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | |
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DDR_CDR2_VREF_RANGE_2; |
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} else { |
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | |
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DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); |
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) | |
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DDR_CDR2_VREF_RANGE_2; |
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} |
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} |
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phys_size_t initdram(int board_type) |
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{ |
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phys_size_t dram_size; |
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puts("Initializing DDR....using SPD\n"); |
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dram_size = fsl_ddr_sdram(); |
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return dram_size; |
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} |
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void dram_init_banksize(void) |
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{ |
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#ifdef CONFIG_SYS_DP_DDR_BASE_PHY |
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phys_size_t dp_ddr_size; |
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#endif |
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
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if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { |
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gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; |
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gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; |
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gd->bd->bi_dram[1].size = gd->ram_size - |
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CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; |
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} else { |
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gd->bd->bi_dram[0].size = gd->ram_size; |
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} |
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#ifdef CONFIG_SYS_DP_DDR_BASE_PHY |
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/* initialize DP-DDR here */ |
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puts("DP-DDR: "); |
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/*
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* DDR controller use 0 as the base address for binding. |
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* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. |
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*/ |
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dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, |
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CONFIG_DP_DDR_CTRL, |
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CONFIG_DP_DDR_NUM_CTRLS, |
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CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, |
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NULL, NULL, NULL); |
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if (dp_ddr_size) { |
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gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; |
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gd->bd->bi_dram[2].size = dp_ddr_size; |
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} else { |
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puts("Not detected"); |
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} |
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#endif |
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} |
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@ -0,0 +1,92 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __DDR_H__ |
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#define __DDR_H__ |
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struct board_specific_parameters { |
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u32 n_ranks; |
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u32 datarate_mhz_high; |
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u32 rank_gb; |
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u32 clk_adjust; |
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u32 wrlvl_start; |
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u32 wrlvl_ctl_2; |
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u32 wrlvl_ctl_3; |
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}; |
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/*
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* These tables contain all valid speeds we want to override with board |
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* specific parameters. datarate_mhz_high values need to be in ascending order |
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* for each n_ranks group. |
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*/ |
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static const struct board_specific_parameters udimm0[] = { |
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/*
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* memory controller 0 |
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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*/ |
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{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, |
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{2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,}, |
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{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, |
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{2, 2300, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, |
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{} |
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}; |
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/* DP-DDR DIMM */ |
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static const struct board_specific_parameters udimm2[] = { |
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/*
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* memory controller 2 |
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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*/ |
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{2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, |
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{2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, |
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{2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, |
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{2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, |
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{} |
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}; |
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static const struct board_specific_parameters rdimm0[] = { |
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/*
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* memory controller 0 |
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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*/ |
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{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, |
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{2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,}, |
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{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, |
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{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, |
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{} |
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}; |
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/* DP-DDR DIMM */ |
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static const struct board_specific_parameters rdimm2[] = { |
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/*
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* memory controller 2 |
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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*/ |
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{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, |
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{2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,}, |
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{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, |
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{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, |
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{} |
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}; |
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static const struct board_specific_parameters *udimms[] = { |
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udimm0, |
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udimm0, |
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udimm2, |
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}; |
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static const struct board_specific_parameters *rdimms[] = { |
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rdimm0, |
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rdimm0, |
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rdimm2, |
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}; |
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#endif |
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@ -0,0 +1,287 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
||||
#include <malloc.h> |
||||
#include <errno.h> |
||||
#include <netdev.h> |
||||
#include <fsl_ifc.h> |
||||
#include <fsl_ddr.h> |
||||
#include <asm/io.h> |
||||
#include <fdt_support.h> |
||||
#include <libfdt.h> |
||||
#include <fsl_debug_server.h> |
||||
#include <fsl-mc/fsl_mc.h> |
||||
#include <environment.h> |
||||
#include <i2c.h> |
||||
#include <asm/arch-fsl-lsch3/soc.h> |
||||
|
||||
#include "../common/qixis.h" |
||||
#include "ls2085aqds_qixis.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
unsigned long long get_qixis_addr(void) |
||||
{ |
||||
unsigned long long addr; |
||||
|
||||
if (gd->flags & GD_FLG_RELOC) |
||||
addr = QIXIS_BASE_PHYS; |
||||
else |
||||
addr = QIXIS_BASE_PHYS_EARLY; |
||||
|
||||
/*
|
||||
* IFC address under 256MB is mapped to 0x30000000, any address above |
||||
* is mapped to 0x5_10000000 up to 4GB. |
||||
*/ |
||||
addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; |
||||
|
||||
return addr; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
char buf[64]; |
||||
u8 sw; |
||||
static const char *const freq[] = {"100", "125", "156.25", |
||||
"100 separate SSCG"}; |
||||
int clock; |
||||
|
||||
sw = QIXIS_READ(arch); |
||||
printf("Board: %s, ", CONFIG_IDENT_STRING); |
||||
printf("Board Arch: V%d, ", sw >> 4); |
||||
printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); |
||||
|
||||
sw = QIXIS_READ(brdcfg[0]); |
||||
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
||||
|
||||
if (sw < 0x8) |
||||
printf("vBank: %d\n", sw); |
||||
else if (sw == 0x8) |
||||
puts("PromJet\n"); |
||||
else if (sw == 0x9) |
||||
puts("NAND\n"); |
||||
else if (sw == 0x15) |
||||
printf("IFCCard\n"); |
||||
else |
||||
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
||||
|
||||
printf("FPGA: v%d (%s), build %d", |
||||
(int)QIXIS_READ(scver), qixis_read_tag(buf), |
||||
(int)qixis_read_minor()); |
||||
/* the timestamp string contains "\n" at the end */ |
||||
printf(" on %s", qixis_read_time(buf)); |
||||
|
||||
/*
|
||||
* Display the actual SERDES reference clocks as configured by the |
||||
* dip switches on the board. Note that the SWx registers could |
||||
* technically be set to force the reference clocks to match the |
||||
* values that the SERDES expects (or vice versa). For now, however, |
||||
* we just display both values and hope the user notices when they |
||||
* don't match. |
||||
*/ |
||||
puts("SERDES1 Reference : "); |
||||
sw = QIXIS_READ(brdcfg[2]); |
||||
clock = (sw >> 6) & 3; |
||||
printf("Clock1 = %sMHz ", freq[clock]); |
||||
clock = (sw >> 4) & 3; |
||||
printf("Clock2 = %sMHz", freq[clock]); |
||||
|
||||
puts("\nSERDES2 Reference : "); |
||||
clock = (sw >> 2) & 3; |
||||
printf("Clock1 = %sMHz ", freq[clock]); |
||||
clock = (sw >> 0) & 3; |
||||
printf("Clock2 = %sMHz\n", freq[clock]); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
unsigned long get_board_sys_clk(void) |
||||
{ |
||||
u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
||||
|
||||
switch (sysclk_conf & 0x0F) { |
||||
case QIXIS_SYSCLK_83: |
||||
return 83333333; |
||||
case QIXIS_SYSCLK_100: |
||||
return 100000000; |
||||
case QIXIS_SYSCLK_125: |
||||
return 125000000; |
||||
case QIXIS_SYSCLK_133: |
||||
return 133333333; |
||||
case QIXIS_SYSCLK_150: |
||||
return 150000000; |
||||
case QIXIS_SYSCLK_160: |
||||
return 160000000; |
||||
case QIXIS_SYSCLK_166: |
||||
return 166666666; |
||||
} |
||||
return 66666666; |
||||
} |
||||
|
||||
unsigned long get_board_ddr_clk(void) |
||||
{ |
||||
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
||||
|
||||
switch ((ddrclk_conf & 0x30) >> 4) { |
||||
case QIXIS_DDRCLK_100: |
||||
return 100000000; |
||||
case QIXIS_DDRCLK_125: |
||||
return 125000000; |
||||
case QIXIS_DDRCLK_133: |
||||
return 133333333; |
||||
} |
||||
return 66666666; |
||||
} |
||||
|
||||
int select_i2c_ch_pca9547(u8 ch) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); |
||||
if (ret) { |
||||
puts("PCA: failed to select proper channel\n"); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
init_final_memctl_regs(); |
||||
|
||||
#ifdef CONFIG_ENV_IS_NOWHERE |
||||
gd->env_addr = (ulong)&default_environment[0]; |
||||
#endif |
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
fsl_lsch3_early_init_f(); |
||||
return 0; |
||||
} |
||||
|
||||
void detail_board_ddr_info(void) |
||||
{ |
||||
puts("\nDDR "); |
||||
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); |
||||
print_ddr_info(0); |
||||
if (gd->bd->bi_dram[2].size) { |
||||
puts("\nDP-DDR "); |
||||
print_size(gd->bd->bi_dram[2].size, ""); |
||||
print_ddr_info(CONFIG_DP_DDR_CTRL); |
||||
} |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = initdram(0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_ARCH_MISC_INIT) |
||||
int arch_misc_init(void) |
||||
{ |
||||
#ifdef CONFIG_FSL_DEBUG_SERVER |
||||
debug_server_init(); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
unsigned long get_dram_size_to_hide(void) |
||||
{ |
||||
unsigned long dram_to_hide = 0; |
||||
|
||||
/* Carve the Debug Server private DRAM block from the end of DRAM */ |
||||
#ifdef CONFIG_FSL_DEBUG_SERVER |
||||
dram_to_hide += debug_server_get_dram_block_size(); |
||||
#endif |
||||
|
||||
/* Carve the MC private DRAM block from the end of DRAM */ |
||||
#ifdef CONFIG_FSL_MC_ENET |
||||
dram_to_hide += mc_get_dram_block_size(); |
||||
#endif |
||||
|
||||
return dram_to_hide; |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
int error = 0; |
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET |
||||
error = cpu_eth_init(bis); |
||||
#endif |
||||
|
||||
error = pci_eth_init(bis); |
||||
|
||||
return error; |
||||
} |
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET |
||||
void fdt_fixup_board_enet(void *fdt) |
||||
{ |
||||
int offset; |
||||
|
||||
offset = fdt_path_offset(fdt, "/fsl-mc"); |
||||
|
||||
if (offset < 0) |
||||
offset = fdt_path_offset(fdt, "/fsl,dprc@0"); |
||||
|
||||
if (offset < 0) { |
||||
printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", |
||||
__func__, offset); |
||||
return; |
||||
} |
||||
|
||||
if (get_mc_boot_status() == 0) |
||||
fdt_status_okay(fdt, offset); |
||||
else |
||||
fdt_status_fail(fdt, offset); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP |
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
phys_addr_t base; |
||||
phys_size_t size; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
/* limit the memory size to bank 1 until Linux can handle 40-bit PA */ |
||||
base = getenv_bootm_low(); |
||||
size = getenv_bootm_size(); |
||||
fdt_fixup_memory(blob, (u64)base, (u64)size); |
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET |
||||
fdt_fixup_board_enet(blob); |
||||
fsl_mc_ldpaa_exit(bd); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
void qixis_dump_switch(void) |
||||
{ |
||||
int i, nr_of_cfgsw; |
||||
|
||||
QIXIS_WRITE(cms[0], 0x00); |
||||
nr_of_cfgsw = QIXIS_READ(cms[1]); |
||||
|
||||
puts("DIP switch settings dump:\n"); |
||||
for (i = 1; i <= nr_of_cfgsw; i++) { |
||||
QIXIS_WRITE(cms[0], i); |
||||
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); |
||||
} |
||||
} |
||||
@ -0,0 +1,26 @@ |
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __LS2_QDS_QIXIS_H__ |
||||
#define __LS2_QDS_QIXIS_H__ |
||||
|
||||
/* SYSCLK */ |
||||
#define QIXIS_SYSCLK_66 0x0 |
||||
#define QIXIS_SYSCLK_83 0x1 |
||||
#define QIXIS_SYSCLK_100 0x2 |
||||
#define QIXIS_SYSCLK_125 0x3 |
||||
#define QIXIS_SYSCLK_133 0x4 |
||||
#define QIXIS_SYSCLK_150 0x5 |
||||
#define QIXIS_SYSCLK_160 0x6 |
||||
#define QIXIS_SYSCLK_166 0x7 |
||||
|
||||
/* DDRCLK */ |
||||
#define QIXIS_DDRCLK_66 0x0 |
||||
#define QIXIS_DDRCLK_100 0x1 |
||||
#define QIXIS_DDRCLK_125 0x2 |
||||
#define QIXIS_DDRCLK_133 0x3 |
||||
|
||||
#endif /*__LS2_QDS_QIXIS_H__*/ |
||||
@ -0,0 +1,3 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS2085AQDS=y |
||||
@ -0,0 +1,283 @@ |
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __LS2_QDS_H |
||||
#define __LS2_QDS_H |
||||
|
||||
#include "ls2085a_common.h" |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_IDENT_STRING " LS2085A-QDS" |
||||
#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-QDS" |
||||
|
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
unsigned long get_board_sys_clk(void); |
||||
unsigned long get_board_ddr_clk(void); |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
||||
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) |
||||
|
||||
#define CONFIG_DDR_SPD |
||||
#define CONFIG_DDR_ECC |
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
||||
#define SPD_EEPROM_ADDRESS1 0x51 |
||||
#define SPD_EEPROM_ADDRESS2 0x52 |
||||
#define SPD_EEPROM_ADDRESS3 0x53 |
||||
#define SPD_EEPROM_ADDRESS4 0x54 |
||||
#define SPD_EEPROM_ADDRESS5 0x55 |
||||
#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ |
||||
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 |
||||
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ |
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
||||
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 |
||||
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ |
||||
|
||||
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ |
||||
|
||||
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) |
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
||||
#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) |
||||
|
||||
#define CONFIG_SYS_NOR0_CSPR \ |
||||
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR0_CSPR_EARLY \ |
||||
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR1_CSPR \ |
||||
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR1_CSPR_EARLY \ |
||||
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) |
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
||||
FTIM0_NOR_TEADC(0x5) | \
|
||||
FTIM0_NOR_TEAHC(0x5)) |
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
||||
FTIM1_NOR_TRAD_NOR(0x1a) |\
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x13)) |
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
||||
FTIM2_NOR_TCH(0x4) | \
|
||||
FTIM2_NOR_TWPH(0x0E) | \
|
||||
FTIM2_NOR_TWP(0x1c)) |
||||
#define CONFIG_SYS_NOR_FTIM3 0x04000000 |
||||
#define CONFIG_SYS_IFC_CCR 0x01000000 |
||||
|
||||
#ifndef CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
#define CONFIG_SYS_FLASH_QUIET_TEST |
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ |
||||
CONFIG_SYS_FLASH_BASE + 0x40000000} |
||||
#endif |
||||
|
||||
#define CONFIG_NAND_FSL_IFC |
||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 256 |
||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2 |
||||
|
||||
|
||||
#define CONFIG_SYS_NAND_CSPR_EXT (0x0) |
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V) |
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) |
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
|
||||
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
||||
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
|
||||
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION |
||||
|
||||
/* ONFI NAND Flash mode0 Timing Params */ |
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x07) | \
|
||||
FTIM0_NAND_TWH(0x0a)) |
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0x0e) | \
|
||||
FTIM1_NAND_TRP(0x18)) |
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
||||
FTIM2_NAND_TREH(0x0a) | \
|
||||
FTIM2_NAND_TWHRE(0x1e)) |
||||
#define CONFIG_SYS_NAND_FTIM3 0x0 |
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
#define CONFIG_CMD_NAND |
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
||||
|
||||
#define CONFIG_FSL_QIXIS /* use common QIXIS code */ |
||||
#define QIXIS_LBMAP_SWITCH 0x06 |
||||
#define QIXIS_LBMAP_MASK 0x0f |
||||
#define QIXIS_LBMAP_SHIFT 0 |
||||
#define QIXIS_LBMAP_DFLTBANK 0x00 |
||||
#define QIXIS_LBMAP_ALTBANK 0x04 |
||||
#define QIXIS_RST_CTL_RESET 0x31 |
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 |
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |
||||
#define QIXIS_RST_FORCE_MEM 0x01 |
||||
|
||||
#define CONFIG_SYS_CSPR3_EXT (0x0) |
||||
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ |
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V) |
||||
#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ |
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V) |
||||
|
||||
#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) |
||||
#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) |
||||
/* QIXIS Timing parameters for IFC CS3 */ |
||||
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
||||
FTIM0_GPCM_TEADC(0x0e) | \
|
||||
FTIM0_GPCM_TEAHC(0x0e)) |
||||
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
||||
FTIM1_GPCM_TRAD(0x3f)) |
||||
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
||||
FTIM2_GPCM_TCH(0xf) | \
|
||||
FTIM2_GPCM_TWP(0x3E)) |
||||
#define CONFIG_SYS_CS3_FTIM3 0x0 |
||||
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY |
||||
#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR |
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY |
||||
#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR |
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY |
||||
#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR |
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK |
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR |
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 |
||||
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 |
||||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 |
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 |
||||
|
||||
/* Debug Server firmware */ |
||||
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR |
||||
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL |
||||
|
||||
/* MC firmware */ |
||||
#define CONFIG_SYS_LS_MC_FW_IN_NOR |
||||
#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL |
||||
|
||||
#define CONFIG_SYS_LS_MC_DPL_IN_NOR |
||||
#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL |
||||
|
||||
#define CONFIG_SYS_LS_MC_DPC_IN_NOR |
||||
#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL |
||||
|
||||
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 |
||||
|
||||
/*
|
||||
* I2C |
||||
*/ |
||||
#define I2C_MUX_PCA_ADDR 0x77 |
||||
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ |
||||
|
||||
/* I2C bus multiplexer */ |
||||
#define I2C_MUX_CH_DEFAULT 0x8 |
||||
|
||||
/*
|
||||
* RTC configuration |
||||
*/ |
||||
#define RTC |
||||
#define CONFIG_RTC_DS3231 1 |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||
|
||||
/* EEPROM */ |
||||
#define CONFIG_ID_EEPROM |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_SYS_I2C_EEPROM_NXID |
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
|
||||
#define CONFIG_FSL_MEMAC |
||||
#define CONFIG_PCI /* Enable PCIE */ |
||||
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ |
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP |
||||
#define CONFIG_E1000 |
||||
#define CONFIG_PCI_SCAN_SHOW |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_NET |
||||
#endif |
||||
|
||||
|
||||
|
||||
/* Initial environment variables */ |
||||
#undef CONFIG_EXTRA_ENV_SETTINGS |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||
"loadaddr=0x80100000\0" \
|
||||
"kernel_addr=0x100000\0" \
|
||||
"ramdisk_addr=0x800000\0" \
|
||||
"ramdisk_size=0x2000000\0" \
|
||||
"fdt_high=0xa0000000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"kernel_start=0x581100000\0" \
|
||||
"kernel_load=0xa0000000\0" \
|
||||
"kernel_size=0x1000000\0" |
||||
|
||||
#endif /* __LS2_QDS_H */ |
||||
Loading…
Reference in new issue