Support for Zoom MDK with OMAP3430. Details of Zoom MDK available here: http://www.logicpd.com/products/devkit/ti/zoom_mobile_development_kit Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Jason Kridner <jkridner@beagleboard.org>master
parent
2be2c6cc67
commit
7379f45a7b
@ -0,0 +1,49 @@ |
||||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := zoom1.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,33 @@ |
||||
#
|
||||
# (C) Copyright 2006-2008
|
||||
# Texas Instruments, <www.ti.com>
|
||||
#
|
||||
# Zoom MDK uses OMAP3 (ARM-CortexA8) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
# Physical Address:
|
||||
# 8000'0000 (bank0)
|
||||
# A000/0000 (bank1)
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
|
||||
# For use with external or internal boots.
|
||||
TEXT_BASE = 0x80e80000
|
@ -0,0 +1,63 @@ |
||||
/* |
||||
* January 2004 - Changed to support H4 device |
||||
* Copyright (c) 2004-2008 Texas Instruments |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm_cortexa8/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } |
||||
__exidx_start = .; |
||||
.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } |
||||
__exidx_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
@ -0,0 +1,77 @@ |
||||
/*
|
||||
* (C) Copyright 2004-2008 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* Author : |
||||
* Nishanth Menon <nm@ti.com> |
||||
* |
||||
* Derived from Beagle Board and 3430 SDP code by |
||||
* Sunil Kumar <sunilsaini05@gmail.com> |
||||
* Shashi Ranjan <shashiranjanmca05@gmail.com> |
||||
* Richard Woodruff <r-woodruff2@ti.com> |
||||
* Syed Mohammed Khasim <khasim@ti.com> |
||||
* |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/mux.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/mach-types.h> |
||||
#include "zoom1.h" |
||||
|
||||
/******************************************************************************
|
||||
* Routine: board_init |
||||
* Description: Early hardware init. |
||||
*****************************************************************************/ |
||||
int board_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
||||
/* board id for Linux */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP; |
||||
/* boot param addr */ |
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/******************************************************************************
|
||||
* Routine: misc_init_r |
||||
* Description: Configure zoom board specific configurations |
||||
*****************************************************************************/ |
||||
int misc_init_r(void) |
||||
{ |
||||
power_init_r(); |
||||
return 0; |
||||
} |
||||
|
||||
/******************************************************************************
|
||||
* Routine: set_muxconf_regs |
||||
* Description: Setting up the configuration Mux registers specific to the |
||||
* hardware. Many pins need to be moved from protect to primary |
||||
* mode. |
||||
*****************************************************************************/ |
||||
void set_muxconf_regs(void) |
||||
{ |
||||
/* platform specific muxes */ |
||||
MUX_ZOOM1_MDK(); |
||||
} |
@ -0,0 +1,135 @@ |
||||
/*
|
||||
* (C) Copyright 2008 |
||||
* Texas Instruments |
||||
* Nishanth Menon <nm@ti.com> |
||||
* |
||||
* Derived from: board/omap3/beagle/beagle.h |
||||
* Dirk Behme <dirk.behme@gmail.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef _BOARD_ZOOM1_H_ |
||||
#define _BOARD_ZOOM1_H_ |
||||
|
||||
const omap3_sysinfo sysinfo = { |
||||
SDP_3430_V1, |
||||
SDP_3430_V2, |
||||
DDR_STACKED, |
||||
"3430", |
||||
"OMAP3 Zoom MDK Rev 1", |
||||
"NAND", |
||||
}; |
||||
|
||||
/*
|
||||
* IEN - Input Enable |
||||
* IDIS - Input Disable |
||||
* PTD - Pull type Down |
||||
* PTU - Pull type Up |
||||
* DIS - Pull type selection is inactive |
||||
* EN - Pull type selection is active |
||||
* M0 - Mode 0 |
||||
* The commented string gives the final mux configuration for that pin |
||||
*/ |
||||
#define MUX_ZOOM1_MDK() \ |
||||
/*SDRC*/\
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
|
||||
/*GPMC*/\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /*GPMC_nCS1*/\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /*GPMC_nCS2*/\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /*GPMC_nCS3*/\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /*GPMC_nCS4*/\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /*GPMC_nCS5*/\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /*GPMC_nCS7*/\
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
|
||||
MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /*GPMC_nWP*/\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /*GPMC_WAIT0*/\
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/ |
||||
|
||||
#endif /* _BOARD_ZOOM_H_ */ |
@ -0,0 +1,326 @@ |
||||
/*
|
||||
* (C) Copyright 2006-2008 |
||||
* Texas Instruments. |
||||
* Richard Woodruff <r-woodruff2@ti.com> |
||||
* Syed Mohammed Khasim <x0khasim@ti.com> |
||||
* Nishanth Menon <nm@ti.com> |
||||
* |
||||
* Configuration settings for the TI OMAP3430 Zoom MDK board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
#include <asm/sizes.h> |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ |
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
||||
#define CONFIG_OMAP34XX 1 /* which is a 34XX */ |
||||
#define CONFIG_OMAP3430 1 /* which is in a 3430 */ |
||||
#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ |
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */ |
||||
#include <asm/arch/omap3.h> |
||||
|
||||
/* Clock Defines */ |
||||
#define V_OSCK 26000000 /* Clock output from T2 */ |
||||
#define V_SCLK (V_OSCK >> 1) |
||||
|
||||
#undef CONFIG_USE_IRQ /* no support for IRQs */ |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
#define CONFIG_REVISION_TAG 1 |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ |
||||
/* Sector */ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ |
||||
/* initial data */ |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ |
||||
|
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 3 |
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
||||
#define CONFIG_SERIAL3 3 /* UART3 */ |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
||||
115200} |
||||
#define CONFIG_MMC 1 |
||||
#define CONFIG_OMAP3_MMC 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
|
||||
/* commands to include */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_EXT2 /* EXT2 Support */ |
||||
#define CONFIG_CMD_FAT /* FAT support */ |
||||
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ |
||||
|
||||
#define CONFIG_CMD_I2C /* I2C serial bus support */ |
||||
#define CONFIG_CMD_MMC /* MMC support */ |
||||
#define CONFIG_CMD_NAND /* NAND support */ |
||||
|
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ |
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ |
||||
#undef CONFIG_CMD_IMI /* iminfo */ |
||||
#undef CONFIG_CMD_IMLS /* List all found images */ |
||||
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ |
||||
#undef CONFIG_CMD_NFS /* NFS support */ |
||||
|
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#define CONFIG_SYS_I2C_SLAVE 1 |
||||
#define CONFIG_SYS_I2C_BUS 0 |
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1 |
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1 |
||||
|
||||
/*
|
||||
* Board NAND Info. |
||||
*/ |
||||
#define CONFIG_NAND_OMAP_GPMC |
||||
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ |
||||
/* to access nand */ |
||||
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ |
||||
/* to access nand at */ |
||||
/* CS0 */ |
||||
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 |
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
||||
/* devices */ |
||||
#define SECTORSIZE 512 |
||||
|
||||
#define NAND_ALLOW_ERASE_ALL |
||||
#define ADDR_COLUMN 1 |
||||
#define ADDR_PAGE 2 |
||||
#define ADDR_COLUMN_PAGE 3 |
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00 |
||||
#define NAND_MAX_FLOORS 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define NAND_NO_RB 1 |
||||
#define CONFIG_SYS_NAND_WP |
||||
|
||||
#define CONFIG_JFFS2_NAND |
||||
/* nand device jffs2 lives on */ |
||||
#define CONFIG_JFFS2_DEV "nand0" |
||||
/* start of jffs2 partition */ |
||||
#define CONFIG_JFFS2_PART_OFFSET 0x680000 |
||||
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ |
||||
/* partition */ |
||||
|
||||
/* Environment information */ |
||||
#define CONFIG_BOOTDELAY 10 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"loadaddr=0x82000000\0" \
|
||||
"console=ttyS2,115200n8\0" \
|
||||
"videomode=1024x768@60,vxres=1024,vyres=768\0" \
|
||||
"videospec=omapfb:vram:2M,vram:4M\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"video=${videospec},mode:${videomode} " \
|
||||
"root=/dev/mmcblk0p2 rw " \
|
||||
"rootfstype=ext3 rootwait\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"video=${videospec},mode:${videomode} " \
|
||||
"root=/dev/mtdblock4 rw " \
|
||||
"rootfstype=jffs2\0" \
|
||||
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"autoscr ${loadaddr}\0" \
|
||||
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${loadaddr} 280000 400000; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"if mmcinit; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run nandboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run nandboot; fi" |
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 |
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define V_PROMPT "OMAP3 Zoom1# " |
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_SYS_PROMPT V_PROMPT |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ |
||||
/* works on */ |
||||
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ |
||||
0x01F00000) /* 31MB */ |
||||
|
||||
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ |
||||
/* load address */ |
||||
|
||||
/*
|
||||
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by |
||||
* 32KHz clk, or from external sig. This rate is divided by a local divisor. |
||||
*/ |
||||
#define V_PVT 7 |
||||
|
||||
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) |
||||
#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ |
||||
#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE SZ_128K /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ |
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 |
||||
#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ |
||||
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
||||
|
||||
/* SDRAM Bank Allocation method */ |
||||
#define SDRC_R_B_C 1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
|
||||
/* **** PISMO SUPPORT *** */ |
||||
|
||||
/* Configure the PISMO */ |
||||
#define PISMO1_NAND_SIZE GPMC_SIZE_128M |
||||
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ |
||||
/* one chip */ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ |
||||
#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE boot_flash_base |
||||
|
||||
/* Monitor at start of flash */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP |
||||
|
||||
#define CONFIG_ENV_IS_IN_NAND 1 |
||||
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ |
||||
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ |
||||
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec |
||||
#define CONFIG_ENV_OFFSET boot_flash_off |
||||
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* CFI FLASH driver setup |
||||
*/ |
||||
/* timeout values are in ticks */ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) |
||||
|
||||
/* Flash banks JFFS2 should use */ |
||||
#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ |
||||
CONFIG_SYS_MAX_NAND_DEVICE) |
||||
#define CONFIG_SYS_JFFS2_MEM_NAND |
||||
/* use flash_info[2] */ |
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS |
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1 |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
extern gpmc_csx_t *nand_cs_base; |
||||
extern gpmc_t *gpmc_cfg_base; |
||||
extern unsigned int boot_flash_base; |
||||
extern volatile unsigned int boot_flash_env_addr; |
||||
extern unsigned int boot_flash_off; |
||||
extern unsigned int boot_flash_sec; |
||||
extern unsigned int boot_flash_type; |
||||
#endif |
||||
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr)\ |
||||
writel(d, &nand_cs_base->nand_cmd) |
||||
#define WRITE_NAND_ADDRESS(d, adr)\ |
||||
writel(d, &nand_cs_base->nand_adr) |
||||
#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) |
||||
#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) |
||||
|
||||
/* Other NAND Access APIs */ |
||||
#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ |
||||
while (0) |
||||
#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ |
||||
while (0) |
||||
#define NAND_DISABLE_CE(nand) |
||||
#define NAND_ENABLE_CE(nand) |
||||
#define NAND_WAIT_READY(nand) udelay(10) |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue