Add bits to support yet another board, the R8A77995 D3 Draak. The DT file is from Linux 4.15-rc1 , commit b35334447513c14a4dd55a67c269a743d4a4824b . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master
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/* |
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* Device Tree Source for the Draak board |
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* |
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* Copyright (C) 2016 Renesas Electronics Corp. |
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* Copyright (C) 2017 Glider bvba |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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|
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/dts-v1/; |
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#include "r8a77995.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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|
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/ { |
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model = "Renesas Draak board based on r8a77995"; |
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compatible = "renesas,draak", "renesas,r8a77995"; |
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|
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aliases { |
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serial0 = &scif2; |
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ethernet0 = &avb; |
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}; |
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chosen { |
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bootargs = "ignore_loglevel"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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memory@48000000 { |
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device_type = "memory"; |
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/* first 128MB is reserved for secure area. */ |
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reg = <0x0 0x48000000 0x0 0x18000000>; |
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}; |
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}; |
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|
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&extal_clk { |
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clock-frequency = <48000000>; |
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}; |
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|
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&pfc { |
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avb0_pins: avb { |
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mux { |
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groups = "avb0_link", "avb0_mdc", "avb0_mii"; |
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function = "avb0"; |
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}; |
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}; |
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|
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pwm0_pins: pwm0 { |
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groups = "pwm0_c"; |
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function = "pwm0"; |
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}; |
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|
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pwm1_pins: pwm1 { |
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groups = "pwm1_c"; |
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function = "pwm1"; |
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}; |
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|
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scif2_pins: scif2 { |
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groups = "scif2_data"; |
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function = "scif2"; |
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}; |
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usb0_pins: usb0 { |
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groups = "usb0"; |
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function = "usb0"; |
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}; |
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}; |
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&ehci0 { |
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status = "okay"; |
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}; |
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&ohci0 { |
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status = "okay"; |
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}; |
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&avb { |
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pinctrl-0 = <&avb0_pins>; |
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pinctrl-names = "default"; |
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renesas,no-ether-link; |
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phy-handle = <&phy0>; |
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status = "okay"; |
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phy0: ethernet-phy@0 { |
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rxc-skew-ps = <1500>; |
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reg = <0>; |
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interrupt-parent = <&gpio5>; |
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interrupts = <19 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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}; |
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&scif2 { |
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pinctrl-0 = <&scif2_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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&usb2_phy0 { |
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pinctrl-0 = <&usb0_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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&pwm0 { |
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pinctrl-0 = <&pwm0_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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&pwm1 { |
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pinctrl-0 = <&pwm1_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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&rwdt { |
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timeout-sec = <60>; |
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status = "okay"; |
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}; |
@ -0,0 +1,15 @@ |
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if TARGET_DRAAK |
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|
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config SYS_SOC |
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default "rmobile" |
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config SYS_BOARD |
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default "draak" |
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config SYS_VENDOR |
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default "renesas" |
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config SYS_CONFIG_NAME |
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default "draak" |
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endif |
@ -0,0 +1,6 @@ |
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DRAAK BOARD |
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M: Marek Vasut <marek.vasut+renesas@gmail.com> |
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S: Maintained |
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F: board/renesas/draak/ |
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F: include/configs/draak.h |
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F: configs/r8a77995_draak_defconfig |
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#
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# board/renesas/draak/Makefile
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#
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# Copyright (C) 2015 Renesas Electronics Corporation
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := draak.o
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/*
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* board/renesas/draak/draak.c |
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* This file is Draak board support. |
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* |
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* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <netdev.h> |
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#include <dm.h> |
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#include <dm/platform_data/serial_sh.h> |
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#include <asm/processor.h> |
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#include <asm/mach-types.h> |
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#include <asm/io.h> |
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#include <linux/errno.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/rmobile.h> |
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#include <asm/arch/rcar-mstp.h> |
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#include <asm/arch/sh_sdhi.h> |
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#include <i2c.h> |
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#include <mmc.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define CPGWPCR 0xE6150904 |
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#define CPGWPR 0xE615090C |
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#define CLK2MHZ(clk) (clk / 1000 / 1000) |
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void s_init(void) |
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{ |
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
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/* Watchdog init */ |
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writel(0xA5A5A500, &rwdt->rwtcsra); |
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writel(0xA5A5A500, &swdt->swtcsra); |
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writel(0xA5A50000, CPGWPCR); |
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writel(0xFFFFFFFF, CPGWPR); |
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} |
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#define GSX_MSTP112 BIT(12) /* 3DG */ |
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#define TMU0_MSTP125 BIT(25) /* secure */ |
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#define TMU1_MSTP124 BIT(24) /* non-secure */ |
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#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ |
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#define DVFS_MSTP926 BIT(26) |
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#define HSUSB_MSTP704 BIT(4) /* HSUSB */ |
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int board_early_init_f(void) |
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{ |
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/* TMU0,1 */ /* which use ? */ |
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); |
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#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) |
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/* DVFS for reset */ |
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mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); |
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#endif |
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return 0; |
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} |
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|
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/* SYSC */ |
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/* R/- 32 Power status register 2(3DG) */ |
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#define SYSC_PWRSR2 0xE6180100 |
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/* -/W 32 Power resume control register 2 (3DG) */ |
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#define SYSC_PWRONCR2 0xE618010C |
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/* HSUSB block registers */ |
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#define HSUSB_REG_LPSTS 0xE6590102 |
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#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) |
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#define HSUSB_REG_UGCTRL2 0xE6590184 |
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#define HSUSB_REG_UGCTRL2_USB0SEL 0x30 |
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#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 |
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int board_init(void) |
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{ |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; |
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/* USB1 pull-up */ |
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setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); |
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/* Configure the HSUSB block */ |
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); |
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/* Choice USB0SEL */ |
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clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, |
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HSUSB_REG_UGCTRL2_USB0SEL_EHCI); |
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/* low power status */ |
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setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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if (fdtdec_setup_memory_size() != 0) |
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return -EINVAL; |
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return 0; |
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} |
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int dram_init_banksize(void) |
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{ |
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fdtdec_setup_memory_banksize(); |
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return 0; |
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} |
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#define RST_BASE 0xE6160000 |
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#define RST_CA57RESCNT (RST_BASE + 0x40) |
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#define RST_CA53RESCNT (RST_BASE + 0x44) |
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#define RST_RSTOUTCR (RST_BASE + 0x58) |
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#define RST_CA57_CODE 0xA5A5000F |
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#define RST_CA53_CODE 0x5A5A000F |
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void reset_cpu(ulong addr) |
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{ |
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unsigned long midr, cputype; |
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asm volatile("mrs %0, midr_el1" : "=r" (midr)); |
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cputype = (midr >> 4) & 0xfff; |
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if (cputype == 0xd03) |
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writel(RST_CA53_CODE, RST_CA53RESCNT); |
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else if (cputype == 0xd07) |
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writel(RST_CA57_CODE, RST_CA57RESCNT); |
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else |
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hang(); |
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} |
@ -0,0 +1,61 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_RMOBILE=y |
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CONFIG_SYS_MALLOC_F_LEN=0x2000 |
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CONFIG_RCAR_GEN3=y |
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CONFIG_R8A77995=y |
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CONFIG_TARGET_DRAAK=y |
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CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak" |
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CONFIG_SMBIOS_PRODUCT_NAME="" |
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set |
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CONFIG_USE_BOOTARGS=y |
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CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" |
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CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb" |
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CONFIG_VERSION_VARIABLE=y |
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CONFIG_HUSH_PARSER=y |
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CONFIG_CMD_BOOTZ=y |
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CONFIG_CMD_GPIO=y |
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CONFIG_CMD_I2C=y |
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CONFIG_CMD_MMC=y |
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CONFIG_CMD_USB=y |
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CONFIG_CMD_DHCP=y |
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CONFIG_CMD_MII=y |
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CONFIG_CMD_PING=y |
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CONFIG_CMD_EXT2=y |
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CONFIG_CMD_EXT4=y |
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CONFIG_CMD_EXT4_WRITE=y |
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CONFIG_CMD_FAT=y |
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CONFIG_CMD_FS_GENERIC=y |
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CONFIG_OF_CONTROL=y |
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CONFIG_ENV_IS_IN_MMC=y |
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CONFIG_REGMAP=y |
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CONFIG_SYSCON=y |
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CONFIG_CLK=y |
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CONFIG_CLK_RENESAS=y |
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CONFIG_DM_GPIO=y |
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CONFIG_RCAR_GPIO=y |
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CONFIG_DM_I2C=y |
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CONFIG_SYS_I2C_RCAR_IIC=y |
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CONFIG_DM_MMC=y |
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CONFIG_MMC_UNIPHIER=y |
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CONFIG_MTD=y |
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CONFIG_MTD_NOR_FLASH=y |
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CONFIG_CFI_FLASH=y |
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CONFIG_RENESAS_RPC_HF=y |
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CONFIG_PHY_MICREL=y |
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CONFIG_PHY_MICREL_KSZ90X1=y |
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CONFIG_DM_ETH=y |
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CONFIG_RENESAS_RAVB=y |
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CONFIG_PINCTRL=y |
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CONFIG_PINCONF=y |
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CONFIG_PINCTRL_PFC=y |
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CONFIG_DM_REGULATOR=y |
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CONFIG_DM_REGULATOR_FIXED=y |
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CONFIG_DM_REGULATOR_GPIO=y |
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CONFIG_SCIF_CONSOLE=y |
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CONFIG_USB=y |
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CONFIG_DM_USB=y |
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CONFIG_USB_XHCI_HCD=y |
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CONFIG_USB_EHCI_HCD=y |
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CONFIG_USB_EHCI_GENERIC=y |
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CONFIG_USB_STORAGE=y |
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CONFIG_SMBIOS_MANUFACTURER="" |
@ -0,0 +1,47 @@ |
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/*
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* include/configs/draak.h |
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* This file is Draak board configuration. |
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* |
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* Copyright (C) 2015 Renesas Electronics Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __DRAAK_H |
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#define __DRAAK_H |
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#undef DEBUG |
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#include "rcar-gen3-common.h" |
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/* Ethernet RAVB */ |
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#define CONFIG_NET_MULTI |
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#define CONFIG_BITBANGMII |
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#define CONFIG_BITBANGMII_MULTI |
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/* Board Clock */ |
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/* XTAL_CLK : 33.33MHz */ |
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#define CONFIG_SYS_CLK_FREQ 33333333u |
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/* Generic Timer Definitions (use in assembler source) */ |
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#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ |
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/* Environment in eMMC, at the end of 2nd "boot sector" */ |
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#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) |
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#define CONFIG_SYS_MMC_ENV_DEV 1 |
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#define CONFIG_SYS_MMC_ENV_PART 2 |
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#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
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#define CONFIG_FLASH_CFI_DRIVER |
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#define CONFIG_FLASH_CFI_MTD |
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#define CONFIG_FLASH_SHOW_PROGRESS 45 |
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#define CONFIG_MTD_DEVICE |
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#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
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#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 |
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#define CONFIG_SYS_MAX_FLASH_SECT 256 |
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#define CONFIG_SYS_WRITE_SWAPPED_DATA |
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#define CONFIG_CMD_CACHE |
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#endif /* __DRAAK_H */ |
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