Tom Warren
13 years ago
committed by
Albert ARIBAUD
parent
c2b626c199
commit
74652cf684
@ -0,0 +1,329 @@ |
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/*
|
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* (C) Copyright 2010-2011 |
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* NVIDIA Corporation <www.nvidia.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include "ap20.h" |
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#include <asm/io.h> |
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#include <asm/arch/tegra2.h> |
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#include <asm/arch/clk_rst.h> |
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#include <asm/arch/pmc.h> |
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#include <asm/arch/pinmux.h> |
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#include <asm/arch/scu.h> |
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#include <common.h> |
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u32 s_first_boot = 1; |
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static void enable_cpu_clock(int enable) |
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{ |
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 reg, clk; |
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/*
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* NOTE: |
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* Regardless of whether the request is to enable or disable the CPU |
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* clock, every processor in the CPU complex except the master (CPU 0) |
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* will have it's clock stopped because the AVP only talks to the |
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* master. The AVP does not know (nor does it need to know) that there |
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* are multiple processors in the CPU complex. |
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*/ |
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if (enable) { |
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/* Wait until all clocks are stable */ |
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udelay(PLL_STABILIZATION_DELAY); |
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writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); |
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writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); |
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} |
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/* Fetch the register containing the main CPU complex clock enable */ |
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reg = readl(&clkrst->crc_clk_out_enb_l); |
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reg |= CLK_ENB_CPU; |
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/*
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* Read the register containing the individual CPU clock enables and |
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* always stop the clock to CPU 1. |
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*/ |
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clk = readl(&clkrst->crc_clk_cpu_cmplx); |
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clk |= CPU1_CLK_STP; |
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if (enable) { |
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/* Unstop the CPU clock */ |
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clk &= ~CPU0_CLK_STP; |
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} else { |
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/* Stop the CPU clock */ |
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clk |= CPU0_CLK_STP; |
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} |
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writel(clk, &clkrst->crc_clk_cpu_cmplx); |
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writel(reg, &clkrst->crc_clk_out_enb_l); |
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} |
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static int is_cpu_powered(void) |
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{ |
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
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return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; |
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} |
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static void remove_cpu_io_clamps(void) |
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{ |
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
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u32 reg; |
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/* Remove the clamps on the CPU I/O signals */ |
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reg = readl(&pmc->pmc_remove_clamping); |
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reg |= CPU_CLMP; |
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writel(reg, &pmc->pmc_remove_clamping); |
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/* Give I/O signals time to stabilize */ |
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udelay(IO_STABILIZATION_DELAY); |
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} |
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static void powerup_cpu(void) |
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{ |
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
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u32 reg; |
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int timeout = IO_STABILIZATION_DELAY; |
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if (!is_cpu_powered()) { |
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/* Toggle the CPU power state (OFF -> ON) */ |
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reg = readl(&pmc->pmc_pwrgate_toggle); |
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reg &= PARTID_CP; |
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reg |= START_CP; |
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writel(reg, &pmc->pmc_pwrgate_toggle); |
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|
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/* Wait for the power to come up */ |
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while (!is_cpu_powered()) { |
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if (timeout-- == 0) |
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printf("CPU failed to power up!\n"); |
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else |
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udelay(10); |
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} |
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/*
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* Remove the I/O clamps from CPU power partition. |
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* Recommended only on a Warm boot, if the CPU partition gets |
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* power gated. Shouldn't cause any harm when called after a |
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* cold boot according to HW, probably just redundant. |
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*/ |
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remove_cpu_io_clamps(); |
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} |
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} |
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static void enable_cpu_power_rail(void) |
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{ |
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
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u32 reg; |
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reg = readl(&pmc->pmc_cntrl); |
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reg |= CPUPWRREQ_OE; |
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writel(reg, &pmc->pmc_cntrl); |
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/*
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* The TI PMU65861C needs a 3.75ms delay between enabling |
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* the power rail and enabling the CPU clock. This delay |
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* between SM1EN and SM1 is for switching time + the ramp |
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* up of the voltage to the CPU (VDD_CPU from PMU). |
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*/ |
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udelay(3750); |
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} |
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static void reset_A9_cpu(int reset) |
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{ |
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 reg, cpu; |
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/*
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* NOTE: Regardless of whether the request is to hold the CPU in reset |
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* or take it out of reset, every processor in the CPU complex |
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* except the master (CPU 0) will be held in reset because the |
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* AVP only talks to the master. The AVP does not know that there |
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* are multiple processors in the CPU complex. |
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*/ |
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/* Hold CPU 1 in reset */ |
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cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1; |
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writel(cpu, &clkrst->crc_cpu_cmplx_set); |
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reg = readl(&clkrst->crc_rst_dev_l); |
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if (reset) { |
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/* Now place CPU0 into reset */ |
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cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0; |
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writel(cpu, &clkrst->crc_cpu_cmplx_set); |
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/* Enable master CPU reset */ |
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reg |= SWR_CPU_RST; |
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} else { |
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/* Take CPU0 out of reset */ |
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cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0; |
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writel(cpu, &clkrst->crc_cpu_cmplx_clr); |
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/* Disable master CPU reset */ |
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reg &= ~SWR_CPU_RST; |
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} |
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writel(reg, &clkrst->crc_rst_dev_l); |
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} |
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static void clock_enable_coresight(int enable) |
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{ |
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 rst, clk, src; |
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rst = readl(&clkrst->crc_rst_dev_u); |
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clk = readl(&clkrst->crc_clk_out_enb_u); |
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if (enable) { |
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rst &= ~SWR_CSITE_RST; |
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clk |= CLK_ENB_CSITE; |
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} else { |
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rst |= SWR_CSITE_RST; |
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clk &= ~CLK_ENB_CSITE; |
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} |
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writel(clk, &clkrst->crc_clk_out_enb_u); |
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writel(rst, &clkrst->crc_rst_dev_u); |
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if (enable) { |
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/*
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* Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by |
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* 1.5, giving an effective frequency of 144MHz. |
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* Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor |
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* (bits 7:0), so 00000001b == 1.5 (n+1 + .5) |
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*/ |
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src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); |
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writel(src, &clkrst->crc_clk_src_csite); |
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/* Unlock the CPU CoreSight interfaces */ |
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rst = 0xC5ACCE55; |
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writel(rst, CSITE_CPU_DBG0_LAR); |
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writel(rst, CSITE_CPU_DBG1_LAR); |
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} |
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} |
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void start_cpu(u32 reset_vector) |
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{ |
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/* Enable VDD_CPU */ |
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enable_cpu_power_rail(); |
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/* Hold the CPUs in reset */ |
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reset_A9_cpu(1); |
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/* Disable the CPU clock */ |
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enable_cpu_clock(0); |
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/* Enable CoreSight */ |
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clock_enable_coresight(1); |
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/*
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* Set the entry point for CPU execution from reset, |
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* if it's a non-zero value. |
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*/ |
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if (reset_vector) |
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writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); |
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/* Enable the CPU clock */ |
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enable_cpu_clock(1); |
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/* If the CPU doesn't already have power, power it up */ |
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powerup_cpu(); |
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/* Take the CPU out of reset */ |
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reset_A9_cpu(0); |
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} |
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void halt_avp(void) |
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{ |
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for (;;) { |
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writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
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| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)), |
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FLOW_CTLR_HALT_COP_EVENTS); |
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} |
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} |
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void enable_scu(void) |
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{ |
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struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; |
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u32 reg; |
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/* If SCU already setup/enabled, return */ |
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if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) |
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return; |
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/* Invalidate all ways for all processors */ |
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writel(0xFFFF, &scu->scu_inv_all); |
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/* Enable SCU - bit 0 */ |
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reg = readl(&scu->scu_ctrl); |
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reg |= SCU_CTRL_ENABLE; |
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writel(reg, &scu->scu_ctrl); |
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} |
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void init_pmc_scratch(void) |
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{ |
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struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
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int i; |
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/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ |
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for (i = 0; i < 23; i++) |
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writel(0, &pmc->pmc_scratch1+i); |
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/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ |
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writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20); |
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} |
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void cpu_start(void) |
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{ |
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; |
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/* enable JTAG */ |
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writel(0xC0, &pmt->pmt_cfg_ctl); |
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if (s_first_boot) { |
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/*
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* Need to set this before cold-booting, |
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* otherwise we'll end up in an infinite loop. |
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*/ |
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s_first_boot = 0; |
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cold_boot(); |
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} |
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} |
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void tegra2_start() |
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{ |
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if (s_first_boot) { |
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/* Init Debug UART Port (115200 8n1) */ |
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uart_init(); |
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/* Init PMC scratch memory */ |
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init_pmc_scratch(); |
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} |
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#ifdef CONFIG_ENABLE_CORTEXA9 |
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/* take the mpcore out of reset */ |
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cpu_start(); |
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/* configure cache */ |
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cache_configure(); |
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#endif |
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} |
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@ -0,0 +1,104 @@ |
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/*
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* (C) Copyright 2010-2011 |
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* NVIDIA Corporation <www.nvidia.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <asm/types.h> |
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/* Stabilization delays, in usec */ |
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#define PLL_STABILIZATION_DELAY (300) |
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#define IO_STABILIZATION_DELAY (1000) |
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#define NVBL_PLLP_KHZ (216000) |
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#define PLLX_ENABLED (1 << 30) |
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#define CCLK_BURST_POLICY 0x20008888 |
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#define SUPER_CCLK_DIVIDER 0x80000000 |
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/* Calculate clock fractional divider value from ref and target frequencies */ |
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#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) |
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/* Calculate clock frequency value from reference and clock divider value */ |
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#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) |
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/* AVP/CPU ID */ |
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#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ |
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#define PG_UP_TAG_0 0x0 |
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#define CORESIGHT_UNLOCK 0xC5ACCE55; |
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/* AP20-Specific Base Addresses */ |
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/* AP20 Base physical address of SDRAM. */ |
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#define AP20_BASE_PA_SDRAM 0x00000000 |
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/* AP20 Base physical address of internal SRAM. */ |
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#define AP20_BASE_PA_SRAM 0x40000000 |
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/* AP20 Size of internal SRAM (256KB). */ |
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#define AP20_BASE_PA_SRAM_SIZE 0x00040000 |
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/* AP20 Base physical address of flash. */ |
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#define AP20_BASE_PA_NOR_FLASH 0xD0000000 |
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/* AP20 Base physical address of boot information table. */ |
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#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM |
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/*
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* Super-temporary stacks for EXTREMELY early startup. The values chosen for |
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* these addresses must be valid on ALL SOCs because this value is used before |
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* we are able to differentiate between the SOC types. |
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* |
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* NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its |
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* stack is placed below the AVP stack. Once the CPU stack has been moved, |
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* the AVP is free to use the IRAM the CPU stack previously occupied if |
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* it should need to do so. |
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* |
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* NOTE: In multi-processor CPU complex configurations, each processor will have |
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* its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a |
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* limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a |
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* stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous |
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* CPU. |
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*/ |
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|
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/* Common AVP early boot stack limit */ |
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#define AVP_EARLY_BOOT_STACK_LIMIT \ |
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(AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2)) |
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/* Common AVP early boot stack size */ |
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#define AVP_EARLY_BOOT_STACK_SIZE 0x1000 |
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/* Common CPU early boot stack limit */ |
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#define CPU_EARLY_BOOT_STACK_LIMIT \ |
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(AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE) |
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/* Common CPU early boot stack size */ |
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#define CPU_EARLY_BOOT_STACK_SIZE 0x1000 |
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|
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#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) |
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#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) |
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#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) |
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#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) |
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#define FLOW_MODE_STOP 2 |
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#define HALT_COP_EVENT_JTAG (1 << 28) |
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#define HALT_COP_EVENT_IRQ_1 (1 << 11) |
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#define HALT_COP_EVENT_FIQ_1 (1 << 9) |
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|
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/* Prototypes */ |
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|
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void tegra2_start(void); |
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void uart_init(void); |
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void udelay(unsigned long); |
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void cold_boot(void); |
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void cache_configure(void); |
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@ -0,0 +1,43 @@ |
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/*
|
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* (C) Copyright 2010,2011 |
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* NVIDIA Corporation <www.nvidia.com> |
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* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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#ifndef _SCU_H_ |
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#define _SCU_H_ |
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|
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/* ARM Snoop Control Unit (SCU) registers */ |
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struct scu_ctlr { |
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uint scu_ctrl; /* SCU Control Register, offset 00 */ |
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uint scu_cfg; /* SCU Config Register, offset 04 */ |
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uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */ |
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uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */ |
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uint scu_reserved0[12]; /* reserved, offset 10-3C */ |
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uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */ |
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uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */ |
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uint scu_reserved1[2]; /* reserved, offset 48-4C */ |
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uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */ |
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uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ |
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}; |
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|
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#define SCU_CTRL_ENABLE (1 << 0) |
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|
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#endif /* SCU_H */ |
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@ -0,0 +1,29 @@ |
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/*
|
||||
* (C) Copyright 2010,2011 |
||||
* NVIDIA Corporation <www.nvidia.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
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|
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#ifndef _BOARD_H_ |
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#define _BOARD_H_ |
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|
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void tegra2_start(void); |
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|
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#endif /* BOARD_H */ |
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Reference in new issue