85xx: Add UEC3 and UEC4 support for MPC8569MDS

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

board/freescale/mpc8569mds/bcsr.c

@@ -41,6 +41,10 @@ void enable_8569mds_qe_mdio()
 			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
 			BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
 }
 
 void disable_8569mds_brd_eeprom_write_protect()

board/freescale/mpc8569mds/mpc8569mds.c

@@ -77,6 +77,36 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
 	{2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */
 
+	/* UCC_3_RGMII */
+	{2, 11, 2, 0, 1}, /* CLK12 */
+	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
+	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
+	{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2      */
+	{1,  0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3      */
+	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
+	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
+	{1,  5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2      */
+	{1,  6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3      */
+	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
+	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
+	{2,  9, 2, 0, 2}, /* ENET3_GRXCLK              */
+	{2, 25, 1, 0, 2}, /* ENET3_GTXCLK              */
+
+	/* UCC_4_RGMII */
+	{2, 16, 2, 0, 3}, /* CLK17 */
+	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
+	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
+	{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2      */
+	{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3      */
+	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
+	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
+	{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2      */
+	{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3      */
+	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
+	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
+	{2, 17, 2, 0, 2}, /* ENET4_GRXCLK              */
+	{2, 24, 1, 0, 2}, /* ENET4_GTXCLK              */
+
 	/* UART1 is muxed with QE PortF bit [9-12].*/
 	{5, 12, 2, 0, 3}, /* UART1_SIN */
 	{5, 9,  1, 0, 3}, /* UART1_SOUT */

include/configs/MPC8569MDS.h

@@ -312,6 +312,29 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
 #endif
 
+#define CONFIG_UEC_ETH3         /* GETH3 */
+#define CONFIG_HAS_ETH2
+
+#ifdef CONFIG_UEC_ETH3
+#define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
+#define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
+#define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR       2
+#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
+
+#define CONFIG_UEC_ETH4         /* GETH4 */
+#define CONFIG_HAS_ETH3
+
+#ifdef CONFIG_UEC_ETH4
+#define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
+#define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
+#define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR       3
+#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
 #endif /* CONFIG_QE */
 
 #if defined(CONFIG_PCI)