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@ -86,6 +86,20 @@ static void setup_iomux_enet(void) |
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gpio_set_value(IMX_GPIO_NR(1, 25), 1); |
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} |
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iomux_v3_cfg_t const usdhc2_pads[] = { |
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MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
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}; |
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iomux_v3_cfg_t const usdhc3_pads[] = { |
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MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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@ -100,28 +114,82 @@ iomux_v3_cfg_t const usdhc3_pads[] = { |
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MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
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}; |
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iomux_v3_cfg_t const usdhc4_pads[] = { |
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MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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}; |
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static void setup_iomux_uart(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
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} |
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#ifdef CONFIG_FSL_ESDHC |
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struct fsl_esdhc_cfg usdhc_cfg[1] = { |
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struct fsl_esdhc_cfg usdhc_cfg[3] = { |
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{USDHC2_BASE_ADDR}, |
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{USDHC3_BASE_ADDR}, |
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{USDHC4_BASE_ADDR}, |
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}; |
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) |
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#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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gpio_direction_input(IMX_GPIO_NR(2, 0)); |
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return !gpio_get_value(IMX_GPIO_NR(2, 0)); |
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
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switch (cfg->esdhc_base) { |
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case USDHC2_BASE_ADDR: |
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return !gpio_get_value(USDHC2_CD_GPIO); |
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case USDHC3_BASE_ADDR: |
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return !gpio_get_value(USDHC3_CD_GPIO); |
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default: |
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return 1; /* eMMC/uSDHC4 is always present */ |
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} |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
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int i; |
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
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switch (i) { |
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case 0: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
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gpio_direction_input(USDHC2_CD_GPIO); |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
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break; |
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case 1: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
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gpio_direction_input(USDHC3_CD_GPIO); |
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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break; |
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case 2: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
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usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
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break; |
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default: |
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printf("Warning: you configured more USDHC controllers" |
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"(%d) than supported by the board\n", i + 1); |
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return 0; |
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} |
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if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) |
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printf("Warning: failed to initialize mmc dev %d\n", i); |
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} |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
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return 0; |
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} |
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#endif |
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