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@ -8,12 +8,15 @@ |
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#include <config.h> |
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#include <common.h> |
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#include <dm.h> |
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#include <net.h> |
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#include <malloc.h> |
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#include <asm/io.h> |
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#include <phy.h> |
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#include <miiphy.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#if !defined(CONFIG_PHYLIB) |
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# error AXI_ETHERNET requires PHYLIB |
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#endif |
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@ -87,6 +90,7 @@ struct axidma_priv { |
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struct axidma_reg *dmarx; |
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int phyaddr; |
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struct axi_regs *iobase; |
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phy_interface_t interface; |
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struct phy_device *phydev; |
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struct mii_dev *bus; |
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}; |
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@ -218,11 +222,11 @@ static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, |
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} |
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/* Setting axi emac and phy to proper setting */ |
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static int setup_phy(struct eth_device *dev) |
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static int setup_phy(struct udevice *dev) |
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{ |
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u16 phyreg; |
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u32 i, speed, emmc_reg, ret; |
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struct axidma_priv *priv = dev->priv; |
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struct axidma_priv *priv = dev_get_priv(dev); |
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struct axi_regs *regs = priv->iobase; |
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struct phy_device *phydev; |
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@ -298,9 +302,9 @@ static int setup_phy(struct eth_device *dev) |
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} |
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/* STOP DMA transfers */ |
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static void axiemac_halt(struct eth_device *dev) |
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static void axiemac_halt(struct udevice *dev) |
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{ |
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struct axidma_priv *priv = dev->priv; |
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struct axidma_priv *priv = dev_get_priv(dev); |
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u32 temp; |
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/* Stop the hardware */ |
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@ -358,16 +362,18 @@ static int axi_ethernet_init(struct axidma_priv *priv) |
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return 0; |
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} |
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static int axiemac_setup_mac(struct eth_device *dev) |
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static int axiemac_setup_mac(struct udevice *dev) |
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{ |
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struct axi_regs *regs = (struct axi_regs *)dev->iobase; |
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struct eth_pdata *pdata = dev_get_platdata(dev); |
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struct axidma_priv *priv = dev_get_priv(dev); |
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struct axi_regs *regs = priv->iobase; |
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/* Set the MAC address */ |
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int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) | |
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(dev->enetaddr[1] << 8) | (dev->enetaddr[0])); |
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int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | |
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(pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); |
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out_be32(®s->uaw0, val); |
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val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ; |
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val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4]; |
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val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; |
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out_be32(®s->uaw1, val); |
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return 0; |
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@ -396,10 +402,10 @@ static void axi_dma_init(struct axidma_priv *priv) |
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printf("%s: Timeout\n", __func__); |
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} |
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static int axiemac_init(struct eth_device *dev, bd_t * bis) |
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static int axiemac_init(struct udevice *dev) |
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{ |
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struct axidma_priv *priv = dev->priv; |
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struct axi_regs *regs = (struct axi_regs *)dev->iobase; |
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struct axidma_priv *priv = dev_get_priv(dev); |
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struct axi_regs *regs = priv->iobase; |
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u32 temp; |
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debug("axiemac: Init started\n"); |
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@ -458,9 +464,9 @@ static int axiemac_init(struct eth_device *dev, bd_t * bis) |
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return 0; |
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} |
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static int axiemac_send(struct eth_device *dev, void *ptr, int len) |
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static int axiemac_send(struct udevice *dev, void *ptr, int len) |
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{ |
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struct axidma_priv *priv = dev->priv; |
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struct axidma_priv *priv = dev_get_priv(dev); |
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u32 timeout; |
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if (len > PKTSIZE_ALIGN) |
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@ -530,15 +536,15 @@ static int isrxready(struct axidma_priv *priv) |
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return 0; |
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} |
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static int axiemac_recv(struct eth_device *dev) |
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static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) |
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{ |
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u32 length; |
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struct axidma_priv *priv = dev->priv; |
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struct axidma_priv *priv = dev_get_priv(dev); |
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u32 temp; |
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/* Wait for an incoming packet */ |
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if (!isrxready(priv)) |
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return 0; |
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return -1; |
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debug("axiemac: RX data ready\n"); |
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@ -578,77 +584,125 @@ static int axiemac_recv(struct eth_device *dev) |
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debug("axiemac: RX completed, framelength = %d\n", length); |
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return length; |
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return 0; |
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} |
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static int axiemac_miiphy_read(const char *devname, uchar addr, |
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uchar reg, ushort *val) |
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static int axiemac_miiphy_read(struct mii_dev *bus, int addr, |
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int devad, int reg) |
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{ |
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struct eth_device *dev = eth_get_dev(); |
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u32 ret; |
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int ret; |
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u16 value; |
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ret = phyread(dev->priv, addr, reg, val); |
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debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); |
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return ret; |
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ret = phyread(bus->priv, addr, reg, &value); |
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debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, |
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value, ret); |
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return value; |
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} |
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static int axiemac_miiphy_write(const char *devname, uchar addr, |
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uchar reg, ushort val) |
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static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad, |
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int reg, u16 value) |
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{ |
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struct eth_device *dev = eth_get_dev(); |
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debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); |
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return phywrite(dev->priv, addr, reg, val); |
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debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); |
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return phywrite(bus->priv, addr, reg, value); |
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} |
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static int axiemac_bus_reset(struct mii_dev *bus) |
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static int axi_emac_probe(struct udevice *dev) |
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{ |
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debug("axiemac: Bus reset\n"); |
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struct axidma_priv *priv = dev_get_priv(dev); |
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int ret; |
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priv->bus = mdio_alloc(); |
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priv->bus->read = axiemac_miiphy_read; |
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priv->bus->write = axiemac_miiphy_write; |
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priv->bus->priv = priv; |
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strcpy(priv->bus->name, "axi_emac"); |
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ret = mdio_register(priv->bus); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, |
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unsigned long dma_addr) |
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static int axi_emac_remove(struct udevice *dev) |
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{ |
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struct eth_device *dev; |
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struct axidma_priv *priv; |
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struct axidma_priv *priv = dev_get_priv(dev); |
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dev = calloc(1, sizeof(struct eth_device)); |
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if (dev == NULL) |
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return -1; |
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free(priv->phydev); |
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mdio_unregister(priv->bus); |
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mdio_free(priv->bus); |
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dev->priv = calloc(1, sizeof(struct axidma_priv)); |
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if (dev->priv == NULL) { |
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free(dev); |
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return -1; |
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} |
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priv = dev->priv; |
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return 0; |
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} |
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sprintf(dev->name, "aximac.%lx", base_addr); |
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static const struct eth_ops axi_emac_ops = { |
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.start = axiemac_init, |
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.send = axiemac_send, |
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.recv = axiemac_recv, |
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.stop = axiemac_halt, |
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.write_hwaddr = axiemac_setup_mac, |
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}; |
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dev->iobase = base_addr; |
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priv->iobase = (struct axi_regs *)base_addr; |
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priv->dmatx = (struct axidma_reg *)dma_addr; |
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static int axi_emac_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct eth_pdata *pdata = dev_get_platdata(dev); |
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struct axidma_priv *priv = dev_get_priv(dev); |
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int offset = 0; |
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const char *phy_mode; |
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pdata->iobase = (phys_addr_t)dev_get_addr(dev); |
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priv->iobase = (struct axi_regs *)pdata->iobase; |
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offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, |
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"axistream-connected"); |
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if (offset <= 0) { |
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printf("%s: axistream is not found\n", __func__); |
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return -EINVAL; |
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} |
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priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob, |
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offset, "reg", 0); |
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if (!priv->dmatx) { |
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printf("%s: axi_dma register space not found\n", __func__); |
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return -EINVAL; |
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} |
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/* RX channel offset is 0x30 */ |
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priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30); |
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dev->init = axiemac_init; |
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dev->halt = axiemac_halt; |
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dev->send = axiemac_send; |
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dev->recv = axiemac_recv; |
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dev->write_hwaddr = axiemac_setup_mac; |
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#ifdef CONFIG_PHY_ADDR |
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priv->phyaddr = CONFIG_PHY_ADDR; |
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#else |
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priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30); |
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priv->phyaddr = -1; |
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#endif |
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eth_register(dev); |
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offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, |
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"phy-handle"); |
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if (offset > 0) |
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priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); |
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phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); |
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if (phy_mode) |
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pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
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if (pdata->phy_interface == -1) { |
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debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); |
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return -EINVAL; |
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} |
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priv->interface = pdata->phy_interface; |
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) |
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miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write); |
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priv->bus = miiphy_get_dev_by_name(dev->name); |
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priv->bus->reset = axiemac_bus_reset; |
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#endif |
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return 1; |
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printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, |
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priv->phyaddr, phy_string_for_interface(priv->interface)); |
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return 0; |
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} |
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static const struct udevice_id axi_emac_ids[] = { |
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{ .compatible = "xlnx,axi-ethernet-1.00.a" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(axi_emac) = { |
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.name = "axi_emac", |
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.id = UCLASS_ETH, |
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.of_match = axi_emac_ids, |
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.ofdata_to_platdata = axi_emac_ofdata_to_platdata, |
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.probe = axi_emac_probe, |
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.remove = axi_emac_remove, |
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.ops = &axi_emac_ops, |
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.priv_auto_alloc_size = sizeof(struct axidma_priv), |
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.platdata_auto_alloc_size = sizeof(struct eth_pdata), |
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}; |
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