@ -174,9 +174,9 @@
# endif
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
# if defined(CONFIG_P1010RDB_PA)
# if defined(CONFIG_TARGET_ P1010RDB_PA)
# define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
# elif defined(CONFIG_P1010RDB_PB)
# elif defined(CONFIG_TARGET_ P1010RDB_PB)
# define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
# endif
# define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
@ -378,7 +378,7 @@ extern unsigned long get_sdram_size(void);
| CSPR_V )
# define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
# if defined(CONFIG_P1010RDB_PA)
# if defined(CONFIG_TARGET_ P1010RDB_PA)
# define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
@ -388,7 +388,7 @@ extern unsigned long get_sdram_size(void);
| CSOR_NAND_PB ( 32 ) ) /* 32 Pages Per Block */
# define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
# elif defined(CONFIG_P1010RDB_PB)
# elif defined(CONFIG_TARGET_ P1010RDB_PB)
# define CONFIG_SYS_NAND_ONFI_DETECTION
# define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
@ -404,7 +404,7 @@ extern unsigned long get_sdram_size(void);
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_CMD_NAND
# if defined(CONFIG_P1010RDB_PA)
# if defined(CONFIG_TARGET_ P1010RDB_PA)
/* NAND Flash Timing Params */
# define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
FTIM0_NAND_TWP ( 0x0C ) | \
@ -419,7 +419,7 @@ extern unsigned long get_sdram_size(void);
FTIM2_NAND_TWHRE ( 0x0f )
# define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
# elif defined(CONFIG_P1010RDB_PB)
# elif defined(CONFIG_TARGET_ P1010RDB_PB)
/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
/* ONFI NAND Flash mode0 Timing Params */
# define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
@ -592,7 +592,7 @@ extern unsigned long get_sdram_size(void);
# define I2C_PCA9557_BUS_NUM 0
/* I2C EEPROM */
# if defined(CONFIG_P1010RDB_PB)
# if defined(CONFIG_TARGET_ P1010RDB_PB)
# define CONFIG_ID_EEPROM
# ifdef CONFIG_ID_EEPROM
# define CONFIG_SYS_I2C_EEPROM_NXID
@ -718,10 +718,10 @@ extern unsigned long get_sdram_size(void);
# define CONFIG_ENV_SIZE 0x2000
# define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
# else
# if defined(CONFIG_P1010RDB_PA)
# if defined(CONFIG_TARGET_ P1010RDB_PA)
# define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
# define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
# elif defined(CONFIG_P1010RDB_PB)
# elif defined(CONFIG_TARGET_ P1010RDB_PB)
# define CONFIG_ENV_SIZE (16 * 1024)
# define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
# endif
@ -842,7 +842,7 @@ extern unsigned long get_sdram_size(void);
" bootm $loadaddr $ramdiskaddr $fdtaddr \0 " \
CONFIG_BOOTMODE
# if defined(CONFIG_P1010RDB_PA)
# if defined(CONFIG_TARGET_ P1010RDB_PA)
# define CONFIG_BOOTMODE \
" boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0; " \
" mw.b ffb00011 0; mw.b ffb00009 0; reset \0 " \
@ -851,7 +851,7 @@ extern unsigned long get_sdram_size(void);
" boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0; " \
" mw.b ffb00011 0; mw.b ffb00017 1; reset \0 "
# elif defined(CONFIG_P1010RDB_PB)
# elif defined(CONFIG_TARGET_ P1010RDB_PB)
# define CONFIG_BOOTMODE \
" boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0; " \
" i2c mw 19 1 2; i2c mw 19 3 e1; reset \0 " \