Now that we have 3 boards for the MPC512x it turns out that they all use the very same fixed_sdram() code. This patch factors out this common code into cpu/mpc512x/fixed_sdram.c and adds a new header file, include/asm-ppc/mpc512x.h, with some macros, inline functions and prototype definitions specific to MPC512x systems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>master
Wolfgang Denk
16 years ago
parent
0549353a6b
commit
7629f1c06b
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/*
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* (C) Copyright 2007-2009 DENX Software Engineering |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/mpc512x.h> |
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/*
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* fixed sdram init: |
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* The board doesn't use memory modules that have serial presence |
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* detect or similar mechanism for discovery of the DRAM settings |
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*/ |
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long int fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; |
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u32 msize_log2 = __ilog2(msize); |
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u32 i; |
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/* Initialize IO Control */ |
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out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); |
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/* Initialize DDR Local Window */ |
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out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000); |
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out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1); |
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sync_law(&im->sysconf.ddrlaw.ar); |
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|
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/* Enable DDR */ |
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN); |
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|
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/* Initialize DDR Priority Manager */ |
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out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); |
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out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2); |
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out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG); |
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out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU); |
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out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML); |
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out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU); |
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out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML); |
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out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU); |
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out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML); |
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out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU); |
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out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML); |
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out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU); |
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out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML); |
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out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU); |
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out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL); |
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out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU); |
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out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL); |
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out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU); |
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out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL); |
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out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU); |
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out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL); |
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out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU); |
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out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL); |
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|
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/* Initialize MDDRC */ |
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG); |
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out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0); |
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out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1); |
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out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2); |
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/* Initialize DDR */ |
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for (i = 0; i < 10; i++) |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); |
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
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/* Start MDDRC */ |
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out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN); |
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN); |
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return msize; |
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} |
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@ -0,0 +1,57 @@ |
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/*
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* include/asm-ppc/mpc512x.h |
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* |
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* Prototypes, etc. for the Freescale MPC512x embedded cpu chips |
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* |
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* 2009 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __ASMPPC_MPC512X_H |
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#define __ASMPPC_MPC512X_H |
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/*
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* macros for manipulating CSx_START/STOP |
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*/ |
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#define CSAW_START(start) ((start) & 0xFFFF0000) |
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#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) |
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/*
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* Inlines |
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*/ |
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/*
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* According to MPC5121e RM, configuring local access windows should |
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* be followed by a dummy read of the config register that was |
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* modified last and an isync. |
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*/ |
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static inline void sync_law(volatile void *addr) |
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{ |
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in_be32(addr); |
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__asm__ __volatile__ ("isync"); |
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} |
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/*
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* Prototypes |
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*/ |
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extern long int fixed_sdram(void); |
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extern int mpc5121_diu_init(void); |
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extern void ide_set_reset(int idereset); |
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#endif /* __ASMPPC_MPC512X_H */ |
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