From 9b0ad1b1c7a15ff674978705c7c52264978dc5d8 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 28 Oct 2008 17:53:38 +0800 Subject: [PATCH 01/12] 85xx: remove the unused ddr_enable_ecc in the board file The DDR controller of 8548/8544/8568/8572/8536 processors have the ECC data init feature, and the new DDR code is using the feature, and we don't need the way with DMA to init memory any more. Signed-off-by: Dave Liu Acked-by: Andy Fleming --- board/atum8548/atum8548.c | 10 ---------- board/freescale/mpc8536ds/mpc8536ds.c | 10 ---------- board/freescale/mpc8544ds/mpc8544ds.c | 10 ---------- board/freescale/mpc8548cds/mpc8548cds.c | 11 ----------- board/freescale/mpc8568mds/mpc8568mds.c | 12 ------------ board/freescale/mpc8572ds/mpc8572ds.c | 10 ---------- board/sbc8548/sbc8548.c | 10 ---------- include/configs/MPC8536DS.h | 2 +- include/configs/MPC8544DS.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8568MDS.h | 2 +- include/configs/MPC8572DS.h | 1 + 12 files changed, 5 insertions(+), 77 deletions(-) diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 226ef57..6ef663e 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -37,10 +37,6 @@ #include #include -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - long int fixed_sdram(void); int board_early_init_f (void) @@ -117,12 +113,6 @@ initdram(int board_type) dram_size = fixed_sdram (); #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif puts(" DDR: "); return dram_size; } diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 6fed4ea..2538483 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -41,10 +41,6 @@ #include "../common/pixis.h" #include "../common/sgmii_riser.h" -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - phys_size_t fixed_sdram(void); int checkboard (void) @@ -73,12 +69,6 @@ initdram(int board_type) dram_size = fixed_sdram(); #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif puts(" DDR: "); return dram_size; } diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 545d869..14581ab 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -38,10 +38,6 @@ #include "../common/pixis.h" #include "../common/sgmii_riser.h" -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -77,12 +73,6 @@ initdram(int board_type) dram_size *= 0x100000; -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif puts(" DDR: "); return dram_size; } diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index af5ff42..8698605 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -38,10 +38,6 @@ #include "../common/eeprom.h" #include "../common/via.h" -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - DECLARE_GLOBAL_DATA_PTR; void local_bus_init(void); @@ -118,13 +114,6 @@ initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - /* * SDRAM Initialization */ diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 688d8c3..bc93be8 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -99,11 +99,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ }; - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - void local_bus_init(void); void sdram_init(void); @@ -170,13 +165,6 @@ initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - /* * SDRAM Initialization */ diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 3a78c98..242af86 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -38,10 +38,6 @@ #include "../common/pixis.h" #include "../common/sgmii_riser.h" -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - long int fixed_sdram(void); int checkboard (void) @@ -69,12 +65,6 @@ phys_size_t initdram(int board_type) dram_size = fixed_sdram(); #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif puts(" DDR: "); return dram_size; } diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 9548ac6..cfb9ce5 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -36,10 +36,6 @@ #include #include -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - DECLARE_GLOBAL_DATA_PTR; void local_bus_init(void); @@ -114,12 +110,6 @@ initdram(int board_type) dram_size = fixed_sdram (); #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif /* * SDRAM Initialization */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index fff888ab..7c94c81 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -99,7 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_DDR_SPD #undef CONFIG_DDR_DLL -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index cdbbea6..a2d12ae 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -97,7 +97,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 083afba..df26f10 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -100,7 +100,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_DDR_SPD #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index ab3e6d6..60e6041 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -92,7 +92,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index c3693b8..ed25c99 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -99,6 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_DDR_SPD #undef CONFIG_DDR_DLL +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 From e57f0fa1333cdf3ca36110aac2900712a5f82976 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 28 Oct 2008 17:53:45 +0800 Subject: [PATCH 02/12] 85xx: the DDR tlb is missed for the !CONFIG_SPD_EEPROM case we need TLB entry for DDR at !SPD case. Signed-off-by: Dave Liu Acked-by: Andy Fleming --- board/freescale/mpc8536ds/mpc8536ds.c | 6 ++---- board/freescale/mpc8572ds/mpc8572ds.c | 6 ++---- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 2538483..2b17612 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -61,13 +61,11 @@ initdram(int board_type) #ifdef CONFIG_SPD_EEPROM dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; #else dram_size = fixed_sdram(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; puts(" DDR: "); return dram_size; diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 242af86..a14db5a 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -57,13 +57,11 @@ phys_size_t initdram(int board_type) #ifdef CONFIG_SPD_EEPROM dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; #else dram_size = fixed_sdram(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; puts(" DDR: "); return dram_size; From a2cd50ed6ef0ac6b127b3d6db756979a8336718d Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 11 Nov 2008 10:17:10 -0600 Subject: [PATCH 03/12] 85xx: Add CPU 2 errata workaround to all 8548 boards All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser Acked-by: Andy Fleming --- board/freescale/mpc8548cds/mpc8548cds.c | 12 ------------ board/sbc8548/sbc8548.c | 7 ------- cpu/mpc85xx/cpu_init.c | 13 +++++++++++++ 3 files changed, 13 insertions(+), 19 deletions(-) diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 8698605..ba6bff5 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -52,7 +52,6 @@ int checkboard (void) uint pci_slot = get_pci_slot (); uint cpu_board_rev = get_cpu_board_revision (); - uint svr; printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", get_board_version (), pci_slot); @@ -65,17 +64,6 @@ int checkboard (void) */ local_bus_init (); - svr = get_svr(); - - /* - * Fix CPU2 errata: A core hang possible while executing a - * msync instruction and a snoopable transaction from an I/O - * master tagged to make quick forward progress is present. - * Fixed in Silicon Rev.2.1 - */ - if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1)) - ecm->eebpcr |= (1 << 16); - /* * Hack TSEC 3 and 4 IO voltages. */ diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index cfb9ce5..017f6b3 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -62,13 +62,6 @@ int checkboard (void) local_bus_init (); /* - * Fix CPU2 errata: A core hang possible while executing a - * msync instruction and a snoopable transaction from an I/O - * master tagged to make quick forward progress is present. - */ - ecm->eebpcr |= (1 << 16); - - /* * Hack TSEC 3 and 4 IO voltages. */ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 3a8aef2..5862bd6 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -174,6 +174,19 @@ void cpu_init_f (void) { volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void); +#ifdef CONFIG_MPC8548 + ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + uint svr = get_svr(); + + /* + * CPU2 errata workaround: A core hang possible while executing + * a msync instruction and a snoopable transaction from an I/O + * master tagged to make quick forward progress is present. + * Fixed in silicon rev 2.1. + */ + if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) + out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); +#endif disable_tlb(14); disable_tlb(15); From dd332e18d082de75eca3fc2c7c778f5d4571a096 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Thu, 13 Nov 2008 18:08:57 +0100 Subject: [PATCH 04/12] 85xx: socrates: fix DDR SDRAM tlb entry configuration since commit be0bd8234b9777ecd63c4c686f72af070d886517 tlb entry for socrates DDR SDRAM will be reconfigured by setup_ddr_tlbs() from initdram() causing an inconsistency with previously configured DDR SDRAM tlb entry from tlb_table: socrates>l2cam 7 9 IDX PID EPN SIZE V TS RPN U0-U3 WIMGE UUUSSS 7 : 00 00000000 256MB V 0 -> 0_00000000 0000 -I-G- ---RWX 8 : 00 00000000 256MB V 0 -> 0_00000000 0000 ----- ---RWX 9 : 00 10000000 256MB V 0 -> 0_10000000 0000 ----- ---RWX This patch makes the presence of the DDR SDRAM tlb entry in the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this inconsistency. Signed-off-by: Anatolij Gustschin Acked-by: Andy Fleming --- board/socrates/tlb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index b91b1ea..4591e46 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -100,6 +100,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), +#if !defined(CONFIG_SPD_EEPROM) /* * TLB 7+8: 512M DDR, cache disabled (needed for memory test) * 0x00000000 512M DDR System memory @@ -114,6 +115,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); From 7008d26a40a76f90cae5824c812cfed449fb97b8 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Wed, 29 Oct 2008 09:21:44 -0500 Subject: [PATCH 05/12] fsl ddr skip interleaving if not supported. Removed while(1) hang if memctl_intlv_ctl is set wrong. Remove embedded tabs from strings. Signed-off-by: Ed Swarthout Acked-by: Kumar Gala Acked-by: Andy Fleming --- cpu/mpc8xxx/ddr/main.c | 9 +++++++-- cpu/mpc8xxx/ddr/options.c | 20 ++++++++++---------- 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c index 21a16d9..f1ad132 100644 --- a/cpu/mpc8xxx/ddr/main.c +++ b/cpu/mpc8xxx/ddr/main.c @@ -475,9 +475,14 @@ phys_size_t fsl_ddr_sdram(void) */ memctl_interleaved = 1; } else { - printf("Error: memctl interleaving not " + printf("Warning: memctl interleaving not " "properly configured on all controllers\n"); - while (1); + memctl_interleaved = 0; + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + info.memctl_opts[i].memctl_interleaving = 0; + debug("Recomputing with memctl_interleaving off.\n"); + total_memory = fsl_ddr_compute(&info, + STEP_ASSIGN_ADDRESSES); } } diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 714e88d..af7f73a 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -197,10 +197,10 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, */ if ((p = getenv("memctl_intlv_ctl")) != NULL) { if (pdimm[0].n_ranks == 0) { - printf("There is no rank on CS0. Because only rank on \ - CS0 and ranks chip-select interleaved with CS0\ - are controller interleaved, force non memory \ - controller interleaving\n"); + printf("There is no rank on CS0. Because only rank on " + "CS0 and ranks chip-select interleaved with CS0" + " are controller interleaved, force non memory " + "controller interleaving\n"); popts->memctl_interleaving = 0; } else { popts->memctl_interleaving = 1; @@ -239,22 +239,22 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, case FSL_DDR_CS0_CS1: if (pdimm[0].n_ranks != 2) { popts->ba_intlv_ctl = 0; - printf("No enough bank(chip-select) for \ - CS0+CS1, force non-interleaving!\n"); + printf("Not enough bank(chip-select) for " + "CS0+CS1, force non-interleaving!\n"); } break; case FSL_DDR_CS2_CS3: if (pdimm[1].n_ranks !=2){ popts->ba_intlv_ctl = 0; - printf("No enough bank(CS) for CS2+CS3, \ - force non-interleaving!\n"); + printf("Not enough bank(CS) for CS2+CS3, " + "force non-interleaving!\n"); } break; case FSL_DDR_CS0_CS1_AND_CS2_CS3: if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) { popts->ba_intlv_ctl = 0; - printf("No enough bank(CS) for CS0+CS1 or \ - CS2+CS3, force non-interleaving!\n"); + printf("Not enough bank(CS) for CS0+CS1 or " + "CS2+CS3, force non-interleaving!\n"); } break; default: From 5a105a333dab6a23e92d763ce76d6f31d57f45df Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 20 Nov 2008 15:36:48 -0600 Subject: [PATCH 06/12] Removed unused CONFIG_L1_INIT_RAM symbol. Prevent further viral propogation of the unused symbol CONFIG_L1_INIT_RAM by just removing it. Signed-off-by: Jon Loeliger Acked-by: Andy Fleming --- include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC8536DS.h | 2 -- include/configs/MPC8540ADS.h | 1 - include/configs/MPC8540EVAL.h | 1 - include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 2 -- include/configs/MPC8548CDS.h | 1 - include/configs/MPC8555CDS.h | 1 - include/configs/MPC8560ADS.h | 1 - include/configs/MPC8568MDS.h | 1 - include/configs/MPC8572DS.h | 2 -- include/configs/MPC8610HPCD.h | 1 - include/configs/MPC8641HPCN.h | 1 - include/configs/MVBLM7.h | 1 - include/configs/PM854.h | 1 - include/configs/PM856.h | 1 - include/configs/SBC8540.h | 1 - include/configs/TQM834x.h | 1 - include/configs/TQM85xx.h | 1 - include/configs/sbc8349.h | 1 - include/configs/sbc8548.h | 1 - include/configs/sbc8560.h | 1 - include/configs/sbc8641d.h | 1 - include/configs/socrates.h | 1 - include/configs/stxgp3.h | 1 - include/configs/stxssa.h | 1 - 27 files changed, 30 deletions(-) diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index bbdc211..8e82aac 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -193,7 +193,6 @@ #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ #define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index f633f24..14cbc45 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -266,7 +266,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #undef CONFIG_SYS_RAMBOOT #endif -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 7c94c81..5a99d5f 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -231,8 +231,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 79a52d9..0b8fe6a 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -258,7 +258,6 @@ #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 46a141a..21cf965 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -161,7 +161,6 @@ #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 7ada8a2..eaa737b 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -281,7 +281,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BR3_PRELIM 0xf8000801 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index a2d12ae..b31c2bb 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -207,8 +207,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index df26f10..7a7e5a1 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -303,7 +303,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BR3_PRELIM 0xf8000801 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index f9419cc..40b40ed 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -279,7 +279,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BR3_PRELIM 0xf8000801 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index f67d489..2b5b2c1 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -254,7 +254,6 @@ #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 60e6041..8bdec65 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -265,7 +265,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BR5_PRELIM 0xf8010801 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index ed25c99..f17639a 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -249,8 +249,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); | PIXIS_VCFGEN1_TSEC3SER \ | PIXIS_VCFGEN1_TSEC4SER) -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index f2fe4a6..7d57c1c 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -206,7 +206,6 @@ #undef CONFIG_CLOCKS_IN_MHZ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #ifndef CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 69b4c44..cd98894 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -268,7 +268,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_CLOCKS_IN_MHZ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #ifndef CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index bc2d825..4ecf806 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -130,7 +130,6 @@ #define CONFIG_SYS_MONITOR_BASE TEXT_BASE #undef CONFIG_SYS_RAMBOOT -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ diff --git a/include/configs/PM854.h b/include/configs/PM854.h index c3a7f81..1cc80ad 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -161,7 +161,6 @@ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h index b3bcf23..698ad2d 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -164,7 +164,6 @@ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 48c9339..2853fba 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -186,7 +186,6 @@ #define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000) /* the size of CS5 needs to be >= 16M for TLB and LAW setups */ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 2961a1b..796030d 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -171,7 +171,6 @@ extern int tqm834x_num_flash_banks; #undef CONFIG_SYS_RAMBOOT #endif -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 2d4048a..300f490 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -234,7 +234,6 @@ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \ + 0x04010000) /* Initial RAM address */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 174149b..0603e3c 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -162,7 +162,6 @@ #undef CONFIG_SYS_RAMBOOT #endif -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index aefd30a..5ce4dac 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -280,7 +280,6 @@ | CONFIG_SYS_LBC_LSDMR_RFEN \ ) -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 4301275..e1d3a52 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -180,7 +180,6 @@ #define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000) /* the size of CS5 needs to be >= 16M for TLB and LAW setups */ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 45d8179..752a905 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -241,7 +241,6 @@ #undef CONFIG_CLOCKS_IN_MHZ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #ifndef CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index c67db8f..e89b5a3 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -167,7 +167,6 @@ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 2188e54..a0f2ed0 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -151,7 +151,6 @@ #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index b0bd050..f0990c6 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -164,7 +164,6 @@ #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ From 35db1c6d34b57ae15e99cf03c8e8f8a6148d74f3 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Fri, 21 Nov 2008 19:24:22 -0600 Subject: [PATCH 07/12] drivers/fsl_pci_init: Fix inbound window mapping bug The current code will cause the creation of a 4GB window starting at 0 if we have more than 4GB of RAM installed, which overlaps with PCI_MEM space and causes pci_bus_to_phys() to return erroneous information. Limit the size to 4GB - 1; which causes the code to create one 2GB and one 1GB window instead. Signed-off-by: Becky Bruce Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- drivers/pci/fsl_pci_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 7625ccc..e57acba 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -58,7 +58,7 @@ void pciauto_config_init(struct pci_controller *hose); int fsl_pci_setup_inbound_windows(struct pci_region *r) { struct pci_region *rgn_base = r; - u64 sz = min((u64)gd->ram_size, 1ull << 32); + u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1); phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; From 9427ccde0355a2ebf47454e8e1be59f5b9864e08 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 1 Dec 2008 13:47:12 -0600 Subject: [PATCH 08/12] 85xx: Add PORDEVSR_PCI1 define Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser Signed-off-by: Andy Fleming --- board/freescale/mpc8548cds/mpc8548cds.c | 2 +- board/sbc8548/sbc8548.c | 2 +- board/tqc/tqm85xx/tqm85xx.c | 2 +- cpu/mpc85xx/pci.c | 2 +- include/asm-ppc/immap_85xx.h | 3 +-- 5 files changed, 5 insertions(+), 6 deletions(-) diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index ba6bff5..c562fc9 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -332,7 +332,7 @@ pci_init_board(void) first_free_busno=hose->last_busno+1; printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); #ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & PORDEVSR_PCI)) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 017f6b3..8c073cb 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -412,7 +412,7 @@ pci_init_board(void) first_free_busno=hose->last_busno+1; printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); #ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & PORDEVSR_PCI)) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 3a828ed..73f1d01 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -610,7 +610,7 @@ static inline void init_pci1(void) first_free_busno = hose->last_busno + 1; #ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & PORDEVSR_PCI)) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { ushort reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index 112f18c..787c6eb 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -70,7 +70,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) */ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - if (!(gur->pordevsr & PORDEVSR_PCI)) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 75b451d..e5046be 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1569,6 +1569,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 +#define MPC85xx_PORDEVSR_PCI1 0x00800000 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 @@ -1647,8 +1648,6 @@ typedef struct ccsr_gur { char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; -#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ - #define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) #define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) #define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) From ea154a1781135d822eedee7567cc156089eae93c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 24 Nov 2008 10:25:14 -0600 Subject: [PATCH 09/12] FSL: Moved BR_PHYS_ADDR for localbus to common header The BR_PHYS_ADDR macro is useful on all machines that have local bus which is pretty much all 83xx/85xx/86xx chips. Additionally most 85xx & 86xx will need it if they want to support 36-bit physical addresses. Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- include/asm-ppc/fsl_lbc.h | 8 ++++++++ include/configs/MPC8641HPCN.h | 9 --------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index cac7bf6..51fc5c1 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -69,6 +69,14 @@ #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) #endif +/* Convert an address into the right format for the BR registers */ +#ifdef CONFIG_PHYS_64BIT +#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ + ((x & 0x300000000ULL) >> 19))) +#else +#define BR_PHYS_ADDR(x) (x & 0xffff8000) +#endif + /* OR - Option Registers */ #define OR0 0x5004 /* Register offset to immr */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index cd98894..5a83296 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -186,17 +186,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ | CONFIG_SYS_PHYS_ADDR_HIGH) - #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -/* Convert an address into the right format for the BR registers */ -#ifdef CONFIG_PHYS_64BIT -#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ - ((x & 0x300000000ULL) >> 19))) -#else -#define BR_PHYS_ADDR(x) (x & 0xffff8000) -#endif - #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | 0x00001001) /* port size 16bit */ #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ From aed461af81012a398a205e9be67ab37667491838 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 24 Nov 2008 10:29:25 -0600 Subject: [PATCH 10/12] 85xx: Fix relocation of CCSRBAR If the virtual address for CCSRBAR is the same after relocation but the physical address is changing we'd end up having two TLB entries with the same VA. Instead we new us the new CCSRBAR virt address + 4k as a temp virt address to access the old CCSRBAR to relocate it. Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- cpu/mpc85xx/cpu_init.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 5862bd6..2d86547 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -140,14 +140,15 @@ void cpu_init_early_f(void) #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) { u32 temp; + volatile u32 *ccsr_virt = + (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); - set_tlb(0, CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_DEFAULT, + set_tlb(0, (u32)ccsr_virt, CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 1, BOOKE_PAGESZ_4K, 0); - temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT); - out_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_PHYS >> 12); - + temp = in_be32(ccsr_virt); + out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); } #endif From 9df59533f77de2829b4b66e5b7620e04edaa391c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 24 Nov 2008 10:29:26 -0600 Subject: [PATCH 11/12] 85xx: init gd as early as possible Moved up the initialization of GD so C code like set_tlb() can use gd->flags to determine if we've relocated or not in the future. Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- cpu/mpc85xx/cpu_init.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 2d86547..0b7c609 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -132,6 +132,12 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 0, BOOKE_PAGESZ_4K, 0); @@ -153,12 +159,6 @@ void cpu_init_early_f(void) } #endif - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - init_laws(); invalidate_tlb(0); init_tlbs(); From dc889e865356497d3e495570118c2245ebce2631 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Fri, 28 Nov 2008 20:16:58 +0800 Subject: [PATCH 12/12] 85xx: fix the wrong DDR settings for MPC8572DS The default DDR freq is 400MHz or 800M data rate, the old settings is pure wrong for the default case. Signed-off-by: Dave Liu Acked-by: Andy Fleming --- include/configs/MPC8572DS.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index f17639a..9a66ca8 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -115,22 +115,22 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 -#define CONFIG_SYS_DDR_MODE_1 0x00480432 +#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x626b2634 +#define CONFIG_SYS_DDR_TIMING_2 0x062874cf +#define CONFIG_SYS_DDR_MODE_1 0x00440462 #define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x06180100 +#define CONFIG_SYS_DDR_INTERVAL 0x0c300100 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 -#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 +#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 +#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ -#define CONFIG_SYS_DDR_CONTROL2 0x04400010 +#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ +#define CONFIG_SYS_DDR_CONTROL2 0x24400000 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d #define CONFIG_SYS_DDR_ERR_DIS 0x00000000