@ -35,9 +35,9 @@ DECLARE_GLOBAL_DATA_PTR;
/* COMMAND1 */
# define SPI_CMD1_GO BIT(31)
# define SPI_CMD1_M_S BIT(30)
# define SPI_CMD1_MODE_MASK 0x3
# define SPI_CMD1_MODE_MASK GENMASK(1, 0)
# define SPI_CMD1_MODE_SHIFT 28
# define SPI_CMD1_CS_SEL_MASK 0x3
# define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0)
# define SPI_CMD1_CS_SEL_SHIFT 26
# define SPI_CMD1_CS_POL_INACTIVE3 BIT(25)
# define SPI_CMD1_CS_POL_INACTIVE2 BIT(24)
@ -45,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
# define SPI_CMD1_CS_POL_INACTIVE0 BIT(22)
# define SPI_CMD1_CS_SW_HW BIT(21)
# define SPI_CMD1_CS_SW_VAL BIT(20)
# define SPI_CMD1_IDLE_SDA_MASK 0x3
# define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0)
# define SPI_CMD1_IDLE_SDA_SHIFT 18
# define SPI_CMD1_BIDIR BIT(17)
# define SPI_CMD1_LSBI_FE BIT(16)
@ -55,14 +55,14 @@ DECLARE_GLOBAL_DATA_PTR;
# define SPI_CMD1_RX_EN BIT(12)
# define SPI_CMD1_TX_EN BIT(11)
# define SPI_CMD1_PACKED BIT(5)
# define SPI_CMD1_BIT_LEN_MASK 0x1F
# define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0)
# define SPI_CMD1_BIT_LEN_SHIFT 0
/* COMMAND2 */
# define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
# define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
# define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6)
# define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
# define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
# define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0)
/* TRANSFER STATUS */
# define SPI_XFER_STS_RDY BIT(30)