This patch add support of LS1088AQDS platform. The LS1088A QorIQTM Development System (QDS) is a high-performance computing, evaluation, and development platform that supports the LS1088A QorIQ Architecture processor. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>master
Ashish Kumar
7 years ago
committed by
York Sun
parent
e84a324ba7
commit
7769776a60
@ -0,0 +1,70 @@ |
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/* |
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* NXP ls1088a QDS board device tree source |
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* |
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* Copyright 2017 NXP |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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#include "fsl-ls1088a.dtsi" |
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/ { |
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model = "NXP Layerscape 1088a QDS Board"; |
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compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; |
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aliases { |
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spi0 = &qspi; |
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spi1 = &dspi; |
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}; |
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}; |
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&dspi { |
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bus-num = <0>; |
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status = "okay"; |
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dflash0: n25q128a { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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reg = <0>; |
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spi-max-frequency = <1000000>; /* input clock */ |
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}; |
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dflash1: sst25wf040b { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <3500000>; |
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reg = <1>; |
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}; |
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dflash2: en25s64 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <3500000>; |
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reg = <2>; |
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}; |
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}; |
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&qspi { |
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bus-num = <0>; |
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status = "okay"; |
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qflash0: s25fs512s@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <50000000>; |
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reg = <0>; |
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}; |
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qflash1: s25fs512s@1 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <50000000>; |
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reg = <1>; |
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}; |
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}; |
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@ -0,0 +1,650 @@ |
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/*
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* Copyright 2017 NXP |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/io.h> |
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#include <asm/arch/fsl_serdes.h> |
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#include <hwconfig.h> |
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#include <fsl_mdio.h> |
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#include <malloc.h> |
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#include <fm_eth.h> |
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#include <i2c.h> |
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#include <miiphy.h> |
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#include <fsl-mc/ldpaa_wriop.h> |
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#include "../common/qixis.h" |
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#include "ls1088a_qixis.h" |
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#define MC_BOOT_ENV_VAR "mcinitcmd" |
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#ifdef CONFIG_FSL_MC_ENET |
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#define SFP_TX 0 |
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/* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
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* Bank 1 -> Lanes A, B, C, D, |
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* Bank 2 -> Lanes A,B, C, D, |
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*/ |
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/* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
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* means that the mapping must be determined dynamically, or that the lane |
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* maps to something other than a board slot. |
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*/ |
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static u8 lane_to_slot_fsm1[] = { |
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0, 0, 0, 0, 0, 0, 0, 0 |
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}; |
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/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
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* housed. |
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*/ |
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static int xqsgii_riser_phy_addr[] = { |
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XQSGMII_CARD_PHY1_PORT0_ADDR, |
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XQSGMII_CARD_PHY2_PORT0_ADDR, |
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XQSGMII_CARD_PHY3_PORT0_ADDR, |
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XQSGMII_CARD_PHY4_PORT0_ADDR, |
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XQSGMII_CARD_PHY3_PORT2_ADDR, |
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XQSGMII_CARD_PHY1_PORT2_ADDR, |
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XQSGMII_CARD_PHY4_PORT2_ADDR, |
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XQSGMII_CARD_PHY2_PORT2_ADDR, |
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}; |
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static int sgmii_riser_phy_addr[] = { |
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SGMII_CARD_PORT1_PHY_ADDR, |
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SGMII_CARD_PORT2_PHY_ADDR, |
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SGMII_CARD_PORT3_PHY_ADDR, |
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SGMII_CARD_PORT4_PHY_ADDR, |
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}; |
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/* Slot2 does not have EMI connections */ |
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#define EMI_NONE 0xFF |
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#define EMI1_RGMII1 0 |
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#define EMI1_RGMII2 1 |
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#define EMI1_SLOT1 2 |
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static const char * const mdio_names[] = { |
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"LS1088A_QDS_MDIO0", |
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"LS1088A_QDS_MDIO1", |
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"LS1088A_QDS_MDIO2", |
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DEFAULT_WRIOP_MDIO2_NAME, |
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}; |
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struct ls1088a_qds_mdio { |
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u8 muxval; |
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struct mii_dev *realbus; |
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}; |
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static void sgmii_configure_repeater(int dpmac) |
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{ |
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struct mii_dev *bus; |
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uint8_t a = 0xf; |
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int i, j, ret; |
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unsigned short value; |
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const char *dev = "LS1088A_QDS_MDIO2"; |
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int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; |
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int i2c_phy_addr = 0; |
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int phy_addr = 0; |
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uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; |
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uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; |
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uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; |
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uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; |
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/* Set I2c to Slot 1 */ |
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i2c_write(0x77, 0, 0, &a, 1); |
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switch (dpmac) { |
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case 1: |
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i2c_phy_addr = i2c_addr[1]; |
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phy_addr = 4; |
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break; |
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case 2: |
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i2c_phy_addr = i2c_addr[0]; |
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phy_addr = 0; |
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break; |
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case 3: |
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i2c_phy_addr = i2c_addr[3]; |
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phy_addr = 0xc; |
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break; |
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case 7: |
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i2c_phy_addr = i2c_addr[2]; |
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phy_addr = 8; |
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break; |
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} |
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/* Check the PHY status */ |
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ret = miiphy_set_current_dev(dev); |
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if (ret > 0) |
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goto error; |
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bus = mdio_get_current_dev(); |
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debug("Reading from bus %s\n", bus->name); |
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ret = miiphy_write(dev, phy_addr, 0x1f, 3); |
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if (ret > 0) |
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goto error; |
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mdelay(10); |
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ret = miiphy_read(dev, phy_addr, 0x11, &value); |
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if (ret > 0) |
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goto error; |
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mdelay(10); |
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if ((value & 0xfff) == 0x401) { |
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miiphy_write(dev, phy_addr, 0x1f, 0); |
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printf("DPMAC %d:PHY is ..... Configured\n", dpmac); |
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return; |
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} |
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for (i = 0; i < 4; i++) { |
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for (j = 0; j < 4; j++) { |
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a = 0x18; |
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i2c_write(i2c_phy_addr, 6, 1, &a, 1); |
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a = 0x38; |
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i2c_write(i2c_phy_addr, 4, 1, &a, 1); |
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a = 0x4; |
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i2c_write(i2c_phy_addr, 8, 1, &a, 1); |
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i2c_write(i2c_phy_addr, 0xf, 1, |
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&ch_a_eq[i], 1); |
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i2c_write(i2c_phy_addr, 0x11, 1, |
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&ch_a_ctl2[j], 1); |
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i2c_write(i2c_phy_addr, 0x16, 1, |
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&ch_b_eq[i], 1); |
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i2c_write(i2c_phy_addr, 0x18, 1, |
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&ch_b_ctl2[j], 1); |
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a = 0x14; |
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i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); |
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a = 0xb5; |
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i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); |
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a = 0x20; |
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i2c_write(i2c_phy_addr, 4, 1, &a, 1); |
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mdelay(100); |
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ret = miiphy_read(dev, phy_addr, 0x11, &value); |
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if (ret > 0) |
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goto error; |
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mdelay(100); |
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ret = miiphy_read(dev, phy_addr, 0x11, &value); |
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if (ret > 0) |
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goto error; |
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if ((value & 0xfff) == 0x401) { |
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printf("DPMAC %d :PHY is configured ", |
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dpmac); |
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printf("after setting repeater 0x%x\n", |
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value); |
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i = 5; |
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j = 5; |
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} else { |
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printf("DPMAC %d :PHY is failed to ", |
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dpmac); |
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printf("configure the repeater 0x%x\n", value); |
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} |
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} |
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} |
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miiphy_write(dev, phy_addr, 0x1f, 0); |
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error: |
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if (ret) |
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printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac); |
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return; |
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} |
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static void qsgmii_configure_repeater(int dpmac) |
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{ |
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uint8_t a = 0xf; |
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int i, j; |
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int i2c_phy_addr = 0; |
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int phy_addr = 0; |
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int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; |
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uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; |
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uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; |
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uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; |
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uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; |
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const char *dev = mdio_names[EMI1_SLOT1]; |
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int ret = 0; |
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unsigned short value; |
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/* Set I2c to Slot 1 */ |
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i2c_write(0x77, 0, 0, &a, 1); |
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switch (dpmac) { |
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case 7: |
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case 8: |
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case 9: |
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case 10: |
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i2c_phy_addr = i2c_addr[2]; |
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phy_addr = 8; |
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break; |
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case 3: |
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case 4: |
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case 5: |
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case 6: |
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i2c_phy_addr = i2c_addr[3]; |
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phy_addr = 0xc; |
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break; |
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} |
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/* Check the PHY status */ |
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ret = miiphy_set_current_dev(dev); |
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ret = miiphy_write(dev, phy_addr, 0x1f, 3); |
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mdelay(10); |
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ret = miiphy_read(dev, phy_addr, 0x11, &value); |
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mdelay(10); |
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ret = miiphy_read(dev, phy_addr, 0x11, &value); |
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mdelay(10); |
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if ((value & 0xf) == 0xf) { |
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miiphy_write(dev, phy_addr, 0x1f, 0); |
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printf("DPMAC %d :PHY is ..... Configured\n", dpmac); |
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return; |
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} |
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for (i = 0; i < 4; i++) { |
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for (j = 0; j < 4; j++) { |
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a = 0x18; |
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i2c_write(i2c_phy_addr, 6, 1, &a, 1); |
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a = 0x38; |
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i2c_write(i2c_phy_addr, 4, 1, &a, 1); |
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a = 0x4; |
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i2c_write(i2c_phy_addr, 8, 1, &a, 1); |
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i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); |
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i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); |
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i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); |
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i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); |
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a = 0x14; |
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i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); |
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a = 0xb5; |
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i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); |
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a = 0x20; |
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i2c_write(i2c_phy_addr, 4, 1, &a, 1); |
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mdelay(100); |
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ret = miiphy_read(dev, phy_addr, 0x11, &value); |
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if (ret > 0) |
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goto error; |
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mdelay(1); |
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ret = miiphy_read(dev, phy_addr, 0x11, &value); |
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if (ret > 0) |
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goto error; |
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mdelay(10); |
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if ((value & 0xf) == 0xf) { |
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miiphy_write(dev, phy_addr, 0x1f, 0); |
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printf("DPMAC %d :PHY is ..... Configured\n", |
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dpmac); |
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return; |
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} |
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} |
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} |
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error: |
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printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac); |
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return; |
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} |
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static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval) |
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{ |
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return mdio_names[muxval]; |
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} |
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struct mii_dev *mii_dev_for_muxval(u8 muxval) |
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{ |
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struct mii_dev *bus; |
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const char *name = ls1088a_qds_mdio_name_for_muxval(muxval); |
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if (!name) { |
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printf("No bus for muxval %x\n", muxval); |
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return NULL; |
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} |
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bus = miiphy_get_dev_by_name(name); |
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if (!bus) { |
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printf("No bus by name %s\n", name); |
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return NULL; |
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} |
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return bus; |
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} |
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static void ls1088a_qds_enable_SFP_TX(u8 muxval) |
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{ |
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u8 brdcfg9; |
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brdcfg9 = QIXIS_READ(brdcfg[9]); |
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brdcfg9 &= ~BRDCFG9_SFPTX_MASK; |
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brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT); |
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QIXIS_WRITE(brdcfg[9], brdcfg9); |
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} |
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static void ls1088a_qds_mux_mdio(u8 muxval) |
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{ |
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u8 brdcfg4; |
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if (muxval <= 5) { |
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brdcfg4 = QIXIS_READ(brdcfg[4]); |
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brdcfg4 &= ~BRDCFG4_EMISEL_MASK; |
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brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); |
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QIXIS_WRITE(brdcfg[4], brdcfg4); |
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} |
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} |
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static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr, |
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int devad, int regnum) |
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{ |
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struct ls1088a_qds_mdio *priv = bus->priv; |
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ls1088a_qds_mux_mdio(priv->muxval); |
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return priv->realbus->read(priv->realbus, addr, devad, regnum); |
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} |
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static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, |
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int regnum, u16 value) |
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{ |
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struct ls1088a_qds_mdio *priv = bus->priv; |
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ls1088a_qds_mux_mdio(priv->muxval); |
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value); |
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} |
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static int ls1088a_qds_mdio_reset(struct mii_dev *bus) |
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{ |
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struct ls1088a_qds_mdio *priv = bus->priv; |
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return priv->realbus->reset(priv->realbus); |
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} |
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static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval) |
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{ |
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struct ls1088a_qds_mdio *pmdio; |
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struct mii_dev *bus = mdio_alloc(); |
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if (!bus) { |
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printf("Failed to allocate ls1088a_qds MDIO bus\n"); |
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return -1; |
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} |
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pmdio = malloc(sizeof(*pmdio)); |
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if (!pmdio) { |
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printf("Failed to allocate ls1088a_qds private data\n"); |
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free(bus); |
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return -1; |
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} |
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bus->read = ls1088a_qds_mdio_read; |
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bus->write = ls1088a_qds_mdio_write; |
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bus->reset = ls1088a_qds_mdio_reset; |
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sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval)); |
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pmdio->realbus = miiphy_get_dev_by_name(realbusname); |
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if (!pmdio->realbus) { |
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printf("No bus with name %s\n", realbusname); |
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free(bus); |
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free(pmdio); |
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return -1; |
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} |
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pmdio->muxval = muxval; |
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bus->priv = pmdio; |
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return mdio_register(bus); |
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} |
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/*
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* Initialize the dpmac_info array. |
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* |
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*/ |
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static void initialize_dpmac_to_slot(void) |
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{ |
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
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u32 serdes1_prtcl, cfg; |
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cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & |
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FSL_CHASSIS3_SRDS1_PRTCL_MASK; |
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cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; |
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serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); |
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switch (serdes1_prtcl) { |
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case 0x12: |
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printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", |
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serdes1_prtcl); |
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lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; |
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lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1; |
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lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1; |
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lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1; |
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break; |
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case 0x15: |
||||
case 0x1D: |
||||
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", |
||||
serdes1_prtcl); |
||||
lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; |
||||
lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1; |
||||
lane_to_slot_fsm1[2] = EMI_NONE; |
||||
lane_to_slot_fsm1[3] = EMI_NONE; |
||||
break; |
||||
case 0x1E: |
||||
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", |
||||
serdes1_prtcl); |
||||
lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; |
||||
lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1; |
||||
lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1; |
||||
lane_to_slot_fsm1[3] = EMI_NONE; |
||||
break; |
||||
case 0x3A: |
||||
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", |
||||
serdes1_prtcl); |
||||
lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; |
||||
lane_to_slot_fsm1[1] = EMI_NONE; |
||||
lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1; |
||||
lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1; |
||||
break; |
||||
|
||||
default: |
||||
printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", |
||||
__func__, serdes1_prtcl); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
void ls1088a_handle_phy_interface_sgmii(int dpmac_id) |
||||
{ |
||||
struct mii_dev *bus; |
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
||||
u32 serdes1_prtcl, cfg; |
||||
|
||||
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & |
||||
FSL_CHASSIS3_SRDS1_PRTCL_MASK; |
||||
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; |
||||
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); |
||||
|
||||
int *riser_phy_addr; |
||||
char *env_hwconfig = env_get("hwconfig"); |
||||
|
||||
if (hwconfig_f("xqsgmii", env_hwconfig)) |
||||
riser_phy_addr = &xqsgii_riser_phy_addr[0]; |
||||
else |
||||
riser_phy_addr = &sgmii_riser_phy_addr[0]; |
||||
|
||||
switch (serdes1_prtcl) { |
||||
case 0x12: |
||||
case 0x15: |
||||
case 0x1E: |
||||
case 0x3A: |
||||
switch (dpmac_id) { |
||||
case 1: |
||||
wriop_set_phy_address(dpmac_id, riser_phy_addr[1]); |
||||
break; |
||||
case 2: |
||||
wriop_set_phy_address(dpmac_id, riser_phy_addr[0]); |
||||
break; |
||||
case 3: |
||||
wriop_set_phy_address(dpmac_id, riser_phy_addr[3]); |
||||
break; |
||||
case 7: |
||||
wriop_set_phy_address(dpmac_id, riser_phy_addr[2]); |
||||
break; |
||||
default: |
||||
printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id); |
||||
break; |
||||
} |
||||
break; |
||||
default: |
||||
printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", |
||||
__func__, serdes1_prtcl); |
||||
return; |
||||
} |
||||
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; |
||||
bus = mii_dev_for_muxval(EMI1_SLOT1); |
||||
wriop_set_mdio(dpmac_id, bus); |
||||
} |
||||
|
||||
void ls1088a_handle_phy_interface_qsgmii(int dpmac_id) |
||||
{ |
||||
struct mii_dev *bus; |
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
||||
u32 serdes1_prtcl, cfg; |
||||
|
||||
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & |
||||
FSL_CHASSIS3_SRDS1_PRTCL_MASK; |
||||
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; |
||||
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); |
||||
|
||||
switch (serdes1_prtcl) { |
||||
case 0x1D: |
||||
case 0x1E: |
||||
switch (dpmac_id) { |
||||
case 3: |
||||
case 4: |
||||
case 5: |
||||
case 6: |
||||
wriop_set_phy_address(dpmac_id, dpmac_id + 9); |
||||
break; |
||||
case 7: |
||||
case 8: |
||||
case 9: |
||||
case 10: |
||||
wriop_set_phy_address(dpmac_id, dpmac_id + 1); |
||||
break; |
||||
} |
||||
|
||||
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; |
||||
bus = mii_dev_for_muxval(EMI1_SLOT1); |
||||
wriop_set_mdio(dpmac_id, bus); |
||||
break; |
||||
default: |
||||
printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", |
||||
serdes1_prtcl); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
void ls1088a_handle_phy_interface_xsgmii(int i) |
||||
{ |
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
||||
u32 serdes1_prtcl, cfg; |
||||
|
||||
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & |
||||
FSL_CHASSIS3_SRDS1_PRTCL_MASK; |
||||
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; |
||||
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); |
||||
|
||||
switch (serdes1_prtcl) { |
||||
case 0x15: |
||||
case 0x1D: |
||||
case 0x1E: |
||||
wriop_set_phy_address(i, i + 26); |
||||
ls1088a_qds_enable_SFP_TX(SFP_TX); |
||||
break; |
||||
default: |
||||
printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", |
||||
serdes1_prtcl); |
||||
break; |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
int error = 0, i; |
||||
char *mc_boot_env_var; |
||||
#ifdef CONFIG_FSL_MC_ENET |
||||
struct memac_mdio_info *memac_mdio0_info; |
||||
char *env_hwconfig = env_get("hwconfig"); |
||||
|
||||
initialize_dpmac_to_slot(); |
||||
|
||||
memac_mdio0_info = (struct memac_mdio_info *)malloc( |
||||
sizeof(struct memac_mdio_info)); |
||||
memac_mdio0_info->regs = |
||||
(struct memac_mdio_controller *) |
||||
CONFIG_SYS_FSL_WRIOP1_MDIO1; |
||||
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME; |
||||
|
||||
/* Register the real MDIO1 bus */ |
||||
fm_memac_mdio_init(bis, memac_mdio0_info); |
||||
|
||||
/* Register the muxing front-ends to the MDIO buses */ |
||||
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1); |
||||
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2); |
||||
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1); |
||||
|
||||
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { |
||||
switch (wriop_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_QSGMII: |
||||
ls1088a_handle_phy_interface_qsgmii(i); |
||||
break; |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
ls1088a_handle_phy_interface_sgmii(i); |
||||
break; |
||||
case PHY_INTERFACE_MODE_XGMII: |
||||
ls1088a_handle_phy_interface_xsgmii(i); |
||||
break; |
||||
default: |
||||
break; |
||||
|
||||
if (i == 16) |
||||
i = NUM_WRIOP_PORTS; |
||||
} |
||||
} |
||||
|
||||
mc_boot_env_var = env_get(MC_BOOT_ENV_VAR); |
||||
if (mc_boot_env_var) |
||||
run_command_list(mc_boot_env_var, -1, 0); |
||||
error = cpu_eth_init(bis); |
||||
|
||||
if (hwconfig_f("xqsgmii", env_hwconfig)) { |
||||
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { |
||||
switch (wriop_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_QSGMII: |
||||
qsgmii_configure_repeater(i); |
||||
break; |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
sgmii_configure_repeater(i); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
|
||||
if (i == 16) |
||||
i = NUM_WRIOP_PORTS; |
||||
} |
||||
} |
||||
#endif |
||||
error = pci_eth_init(bis); |
||||
return error; |
||||
} |
||||
@ -0,0 +1,29 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1088AQDS=y |
||||
# CONFIG_SYS_MALLOC_F is not set |
||||
CONFIG_DM_SPI=y |
||||
CONFIG_DM_SPI_FLASH=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_OF_BOARD_SETUP=y |
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_I2C=y |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_DM=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_FSL_DSPI=y |
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y |
||||
# CONFIG_DISPLAY_BOARDINFO is not set |
||||
CONFIG_FSL_LS_PPA=y |
||||
@ -0,0 +1,414 @@ |
||||
/*
|
||||
* Copyright 2017 NXP |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __LS1088A_QDS_H |
||||
#define __LS1088A_QDS_H |
||||
|
||||
#include "ls1088a_common.h" |
||||
|
||||
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE |
||||
|
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
unsigned long get_board_sys_clk(void); |
||||
unsigned long get_board_ddr_clk(void); |
||||
#endif |
||||
|
||||
|
||||
#if defined(CONFIG_QSPI_BOOT) |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
||||
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 |
||||
#define CONFIG_ENV_SIZE 0x20000 |
||||
#endif |
||||
|
||||
#if defined(CONFIG_QSPI_BOOT) |
||||
#define CONFIG_QIXIS_I2C_ACCESS |
||||
#define SYS_NO_FLASH |
||||
|
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_SYS_CLK_FREQ 100000000 |
||||
#define CONFIG_DDR_CLK_FREQ 100000000 |
||||
#else |
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
||||
#endif |
||||
|
||||
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) |
||||
#define COUNTER_FREQUENCY 25000000 /* 25MHz */ |
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
||||
|
||||
#define CONFIG_DDR_SPD |
||||
#define CONFIG_DDR_ECC |
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
||||
#define SPD_EEPROM_ADDRESS 0x51 |
||||
#define CONFIG_SYS_SPD_BUS_NUM 0 |
||||
|
||||
|
||||
/*
|
||||
* IFC Definitions |
||||
*/ |
||||
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
||||
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) |
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
||||
#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) |
||||
|
||||
#define CONFIG_SYS_NOR0_CSPR \ |
||||
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR0_CSPR_EARLY \ |
||||
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR1_CSPR \ |
||||
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR1_CSPR_EARLY \ |
||||
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) |
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
||||
FTIM0_NOR_TEADC(0x5) | \
|
||||
FTIM0_NOR_TEAHC(0x5)) |
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
||||
FTIM1_NOR_TRAD_NOR(0x1a) |\
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x13)) |
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
||||
FTIM2_NOR_TCH(0x4) | \
|
||||
FTIM2_NOR_TWPH(0x0E) | \
|
||||
FTIM2_NOR_TWP(0x1c)) |
||||
#define CONFIG_SYS_NOR_FTIM3 0x04000000 |
||||
#define CONFIG_SYS_IFC_CCR 0x01000000 |
||||
|
||||
#ifndef SYS_NO_FLASH |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
#define CONFIG_SYS_FLASH_QUIET_TEST |
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ |
||||
CONFIG_SYS_FLASH_BASE + 0x40000000} |
||||
#endif |
||||
#endif |
||||
|
||||
#define CONFIG_NAND_FSL_IFC |
||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 256 |
||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2 |
||||
|
||||
#define CONFIG_SYS_NAND_CSPR_EXT (0x0) |
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V) |
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) |
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
|
||||
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
||||
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
|
||||
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION |
||||
|
||||
/* ONFI NAND Flash mode0 Timing Params */ |
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x07) | \
|
||||
FTIM0_NAND_TWH(0x0a)) |
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0x0e) | \
|
||||
FTIM1_NAND_TRP(0x18)) |
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
||||
FTIM2_NAND_TREH(0x0a) | \
|
||||
FTIM2_NAND_TWHRE(0x1e)) |
||||
#define CONFIG_SYS_NAND_FTIM3 0x0 |
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
#define CONFIG_CMD_NAND |
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
||||
|
||||
#define CONFIG_FSL_QIXIS |
||||
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 |
||||
#define QIXIS_LBMAP_SWITCH 6 |
||||
#define QIXIS_QMAP_MASK 0xe0 |
||||
#define QIXIS_QMAP_SHIFT 5 |
||||
#define QIXIS_LBMAP_MASK 0x0f |
||||
#define QIXIS_LBMAP_SHIFT 0 |
||||
#define QIXIS_LBMAP_DFLTBANK 0x0e |
||||
#define QIXIS_LBMAP_ALTBANK 0x2e |
||||
#define QIXIS_LBMAP_SD 0x00 |
||||
#define QIXIS_LBMAP_SD_QSPI 0x0e |
||||
#define QIXIS_LBMAP_QSPI 0x0e |
||||
#define QIXIS_RCW_SRC_SD 0x40 |
||||
#define QIXIS_RCW_SRC_QSPI 0x62 |
||||
#define QIXIS_RST_CTL_RESET 0x41 |
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 |
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |
||||
#define QIXIS_RST_FORCE_MEM 0x01 |
||||
#define QIXIS_STAT_PRES1 0xb |
||||
#define QIXIS_SDID_MASK 0x07 |
||||
#define QIXIS_ESDHC_NO_ADAPTER 0x7 |
||||
|
||||
#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) |
||||
#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ |
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V) |
||||
#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ |
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V) |
||||
|
||||
#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) |
||||
#if defined(CONFIG_QSPI_BOOT) |
||||
#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) |
||||
#else |
||||
#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) |
||||
#endif |
||||
/* QIXIS Timing parameters*/ |
||||
#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
||||
FTIM0_GPCM_TEADC(0x0e) | \
|
||||
FTIM0_GPCM_TEAHC(0x0e)) |
||||
#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
||||
FTIM1_GPCM_TRAD(0x3f)) |
||||
#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
||||
FTIM2_GPCM_TCH(0xf) | \
|
||||
FTIM2_GPCM_TWP(0x3E)) |
||||
#define SYS_FPGA_CS_FTIM3 0x0 |
||||
|
||||
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR |
||||
#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL |
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK |
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR |
||||
#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 |
||||
#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 |
||||
#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 |
||||
#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 |
||||
#else |
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY |
||||
#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR |
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY |
||||
#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR |
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY |
||||
#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR |
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK |
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR |
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 |
||||
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 |
||||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 |
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 |
||||
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR |
||||
#define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL |
||||
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK |
||||
#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR |
||||
#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0 |
||||
#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1 |
||||
#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2 |
||||
#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 |
||||
|
||||
/*
|
||||
* I2C bus multiplexer |
||||
*/ |
||||
#define I2C_MUX_PCA_ADDR_PRI 0x77 |
||||
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ |
||||
#define I2C_RETIMER_ADDR 0x18 |
||||
#define I2C_RETIMER_ADDR2 0x19 |
||||
#define I2C_MUX_CH_DEFAULT 0x8 |
||||
#define I2C_MUX_CH5 0xD |
||||
|
||||
/*
|
||||
* RTC configuration |
||||
*/ |
||||
#define RTC |
||||
#define CONFIG_RTC_PCF8563 1 |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ |
||||
#define CONFIG_CMD_DATE |
||||
|
||||
/* EEPROM */ |
||||
#define CONFIG_ID_EEPROM |
||||
#define CONFIG_SYS_I2C_EEPROM_NXID |
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
||||
|
||||
/* QSPI device */ |
||||
#if defined(CONFIG_QSPI_BOOT) |
||||
#define CONFIG_FSL_QSPI |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
#define FSL_QSPI_FLASH_SIZE (1 << 26) |
||||
#define FSL_QSPI_FLASH_NUM 2 |
||||
|
||||
#endif |
||||
|
||||
#ifdef CONFIG_FSL_DSPI |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
#define CONFIG_SPI_FLASH_SST |
||||
#define CONFIG_SPI_FLASH_EON |
||||
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
||||
#define CONFIG_SF_DEFAULT_BUS 1 |
||||
#define CONFIG_SF_DEFAULT_CS 0 |
||||
#endif |
||||
#endif |
||||
|
||||
#define CONFIG_CMD_MEMINFO |
||||
#define CONFIG_CMD_MEMTEST |
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x9fffffff |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
|
||||
#define CONFIG_FSL_MEMAC |
||||
|
||||
/* MMC */ |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
||||
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ |
||||
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) |
||||
|
||||
/* Initial environment variables */ |
||||
#if defined(CONFIG_QSPI_BOOT) |
||||
#undef CONFIG_EXTRA_ENV_SETTINGS |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||
"loadaddr=0x90100000\0" \
|
||||
"kernel_addr=0x100000\0" \
|
||||
"ramdisk_addr=0x800000\0" \
|
||||
"ramdisk_size=0x2000000\0" \
|
||||
"fdt_high=0xa0000000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"kernel_start=0x1000000\0" \
|
||||
"kernel_load=0xa0000000\0" \
|
||||
"kernel_size=0x2800000\0" \
|
||||
"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
|
||||
"sf read 0x80100000 0xE00000 0x100000;" \
|
||||
"fsl_mc start mc 0x80000000 0x80100000\0" \
|
||||
"mcmemsize=0x70000000 \0" |
||||
#else /* NOR BOOT */ |
||||
#undef CONFIG_EXTRA_ENV_SETTINGS |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||
"loadaddr=0x90100000\0" \
|
||||
"kernel_addr=0x100000\0" \
|
||||
"ramdisk_addr=0x800000\0" \
|
||||
"ramdisk_size=0x2000000\0" \
|
||||
"fdt_high=0xa0000000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"kernel_start=0x1000000\0" \
|
||||
"kernel_load=0xa0000000\0" \
|
||||
"kernel_size=0x2800000\0" \
|
||||
"mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
|
||||
"mcmemsize=0x70000000 \0" |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET |
||||
#define CONFIG_FSL_MEMAC |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHYLIB_10G |
||||
#define CONFIG_PHY_VITESSE |
||||
#define CONFIG_PHY_REALTEK |
||||
#define CONFIG_PHY_TERANETICS |
||||
#define RGMII_PHY1_ADDR 0x1 |
||||
#define RGMII_PHY2_ADDR 0x2 |
||||
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C |
||||
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d |
||||
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E |
||||
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F |
||||
|
||||
#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 |
||||
#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 |
||||
#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 |
||||
#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 |
||||
#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 |
||||
#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 |
||||
#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 |
||||
#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 |
||||
#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 |
||||
#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 |
||||
#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa |
||||
#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb |
||||
#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc |
||||
#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd |
||||
#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe |
||||
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf |
||||
|
||||
#define CONFIG_MII /* MII PHY management */ |
||||
#define CONFIG_ETHPRIME "DPMAC1@xgmii" |
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
||||
|
||||
#endif |
||||
|
||||
#undef CONFIG_CMDLINE_EDITING |
||||
#include <config_distro_defaults.h> |
||||
#define BOOT_TARGET_DEVICES(func) \ |
||||
func(USB, usb, 0) \
|
||||
func(MMC, mmc, 0) \
|
||||
func(SCSI, scsi, 0) \
|
||||
func(DHCP, dhcp, na) |
||||
#include <config_distro_bootcmd.h> |
||||
|
||||
#include <asm/fsl_secure_boot.h> |
||||
|
||||
#endif /* __LS1088A_QDS_H */ |
||||
Loading…
Reference in new issue