Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2master
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2012 Altera Corporation <www.altera.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(SOC).o
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SOBJS := lowlevel_init.o
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COBJS-y := misc.o timer.o
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COBJS-$(CONFIG_SPL_BUILD) += spl.o
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COBJS := $(COBJS-y)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
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all: $(obj).depend $(LIB) |
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$(LIB): $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,16 @@ |
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#
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# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed "as is" WITHOUT ANY WARRANTY of any
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# kind, whether express or implied; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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ifndef CONFIG_SPL_BUILD |
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ALL-y += $(obj)u-boot.img
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endif |
@ -0,0 +1,77 @@ |
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/* |
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* |
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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#include <config.h> |
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#include <version.h> |
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/* Save the parameter pass in by previous boot loader */ |
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.global save_boot_params
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save_boot_params: |
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/* save the parameter here */ |
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/* |
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* Setup stack for exception, which is located |
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* at the end of on-chip RAM. We don't expect exception prior to |
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* relocation and if that happens, we won't worry -- it will overide |
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* global data region as the code will goto reset. After relocation, |
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* this region won't be used by other part of program. |
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* Hence it is safe. |
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*/ |
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ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) |
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ldr r1, =IRQ_STACK_START_IN |
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str r0, [r1] |
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bx lr |
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/* Set up the platform, once the cpu has been initialized */ |
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.globl lowlevel_init
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lowlevel_init: |
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/* Remap */ |
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#ifdef CONFIG_SPL_BUILD |
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/* |
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* SPL : configure the remap (L3 NIC-301 GPV) |
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* so the on-chip RAM at lower memory instead ROM. |
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*/ |
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ldr r0, =SOCFPGA_L3REGS_ADDRESS |
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mov r1, #0x19 |
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str r1, [r0] |
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#else |
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/* |
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* U-Boot : configure the remap (L3 NIC-301 GPV) |
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* so the SDRAM at lower memory instead on-chip RAM. |
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*/ |
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ldr r0, =SOCFPGA_L3REGS_ADDRESS |
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mov r1, #0x2 |
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str r1, [r0] |
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/* Private components security */ |
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/* |
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* U-Boot : configure private timer, global timer and cpu |
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* component access as non secure for kernel stage (as required |
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* by kernel) |
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*/ |
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mrc p15,4,r0,c15,c0,0 |
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add r1, r0, #0x54 |
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ldr r2, [r1] |
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orr r2, r2, #0xff |
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orr r2, r2, #0xf00 |
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str r2, [r1] |
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#endif /* #ifdef CONFIG_SPL_BUILD */ |
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mov pc, lr |
@ -0,0 +1,54 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/reset_manager.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static const struct socfpga_reset_manager *reset_manager_base = |
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(void *)SOCFPGA_RSTMGR_ADDRESS; |
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/*
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* Write the reset manager register to cause reset |
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*/ |
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void reset_cpu(ulong addr) |
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{ |
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/* request a warm reset */ |
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writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); |
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/*
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* infinite loop here as watchdog will trigger and reset |
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* the processor |
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*/ |
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while (1) |
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; |
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} |
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/*
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* Release peripherals from reset based on handoff |
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*/ |
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void reset_deassert_peripherals_handoff(void) |
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{ |
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writel(0, &reset_manager_base->per_mod_reset); |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); |
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return 0; |
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} |
@ -0,0 +1,48 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/u-boot.h> |
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#include <asm/utils.h> |
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#include <version.h> |
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#include <image.h> |
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#include <malloc.h> |
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#include <asm/arch/reset_manager.h> |
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#include <spl.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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u32 spl_boot_device(void) |
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{ |
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return BOOT_DEVICE_RAM; |
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} |
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/*
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* Board initialization after bss clearance |
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*/ |
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void spl_board_init(void) |
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{ |
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/* init timer for enabling delay function */ |
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timer_init(); |
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/* de-assert reset for peripherals and bridges based on handoff */ |
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reset_deassert_peripherals_handoff(); |
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/* enable console uart printing */ |
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preloader_console_init(); |
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} |
@ -0,0 +1,104 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/timer.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; |
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/*
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* Timer initialization |
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*/ |
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int timer_init(void) |
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{ |
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writel(TIMER_LOAD_VAL, &timer_base->load_val); |
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writel(TIMER_LOAD_VAL, &timer_base->curr_val); |
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writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl); |
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return 0; |
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} |
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static u32 read_timer(void) |
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{ |
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return readl(&timer_base->curr_val); |
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} |
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/*
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* Delay x useconds |
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*/ |
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void __udelay(unsigned long usec) |
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{ |
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unsigned long now, last; |
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/*
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* get the tmo value based on timer clock speed |
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* tmo = delay required / period of timer clock |
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*/ |
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long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000; |
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last = read_timer(); |
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while (tmo > 0) { |
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now = read_timer(); |
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if (last >= now) |
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/* normal mode (non roll) */ |
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tmo -= last - now; |
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else |
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/* we have overflow of the count down timer */ |
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tmo -= TIMER_LOAD_VAL - last + now; |
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last = now; |
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} |
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} |
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/*
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* Get the timer value |
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*/ |
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ulong get_timer(ulong base) |
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{ |
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return get_timer_masked() - base; |
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} |
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/*
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* Timer : get the time difference |
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* Unit of tick is based on the CONFIG_SYS_HZ |
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*/ |
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ulong get_timer_masked(void) |
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{ |
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/* current tick value */ |
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ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); |
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if (gd->lastinc >= now) { |
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/* normal mode (non roll) */ |
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/* move stamp forward with absolute diff ticks */ |
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gd->tbl += gd->lastinc - now; |
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} else { |
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/* we have overflow of the count down timer */ |
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gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now; |
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} |
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gd->lastinc = now; |
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return gd->tbl; |
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} |
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/*
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* Reset the timer |
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*/ |
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void reset_timer(void) |
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{ |
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/* capture current decrementer value time */ |
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gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); |
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/* start "advancing" time stamp from 0 */ |
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gd->tbl = 0; |
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} |
@ -0,0 +1,60 @@ |
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/* |
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) } |
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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. = 0x00000000; |
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. = ALIGN(4); |
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.text : |
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{ |
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arch/arm/cpu/armv7/start.o (.text) |
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*(.text*) |
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} >.sdram |
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. = ALIGN(4); |
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.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram |
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. = ALIGN(4); |
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.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram |
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. = ALIGN(4); |
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__image_copy_end = .; |
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_end = .; |
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.bss : { |
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. = ALIGN(4); |
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__bss_start = .; |
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*(.bss*) |
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. = ALIGN(4); |
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__bss_end__ = .; |
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} >.sdram |
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. = ALIGN(8); |
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__malloc_start = .; |
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. = . + CONFIG_SPL_MALLOC_SIZE; |
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__malloc_end = .; |
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. = . + CONFIG_SPL_STACK_SIZE; |
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. = ALIGN(8); |
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__stack_start = .; |
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} |
@ -0,0 +1,37 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef _RESET_MANAGER_H_ |
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#define _RESET_MANAGER_H_ |
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void reset_cpu(ulong addr); |
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void reset_deassert_peripherals_handoff(void); |
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struct socfpga_reset_manager { |
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u32 padding1; |
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u32 ctrl; |
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u32 padding2; |
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u32 padding3; |
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u32 mpu_mod_reset; |
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u32 per_mod_reset; |
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u32 per2_mod_reset; |
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u32 brg_mod_reset; |
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}; |
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#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 |
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#endif /* _RESET_MANAGER_H_ */ |
@ -0,0 +1,27 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef _SOCFPGA_BASE_ADDRS_H_ |
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#define _SOCFPGA_BASE_ADDRS_H_ |
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#define SOCFPGA_L3REGS_ADDRESS 0xff800000 |
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#define SOCFPGA_UART0_ADDRESS 0xffc02000 |
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#define SOCFPGA_UART1_ADDRESS 0xffc03000 |
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#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 |
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#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 |
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#endif /* _SOCFPGA_BASE_ADDRS_H_ */ |
@ -0,0 +1,26 @@ |
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/*
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* Copyright (C) 2012 Pavel Machek <pavel@denx.de> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
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*/ |
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|
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#ifndef _SOCFPGA_SPL_H_ |
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#define _SOCFPGA_SPL_H_ |
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|
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/* Symbols from linker script */ |
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extern char __malloc_start, __malloc_end, __stack_start; |
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|
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#define BOOT_DEVICE_RAM 1 |
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#endif |
@ -0,0 +1,29 @@ |
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/*
|
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
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*/ |
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|
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#ifndef _SOCFPGA_TIMER_H_ |
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#define _SOCFPGA_TIMER_H_ |
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|
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struct socfpga_timer { |
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u32 load_val; |
||||
u32 curr_val; |
||||
u32 ctrl; |
||||
u32 eoi; |
||||
u32 int_stat; |
||||
}; |
||||
|
||||
#endif |
@ -0,0 +1,50 @@ |
||||
#
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := socfpga_cyclone5.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
clean: |
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,80 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/reset_manager.h> |
||||
#include <asm/io.h> |
||||
|
||||
#include <netdev.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*
|
||||
* Print CPU information |
||||
*/ |
||||
int print_cpuinfo(void) |
||||
{ |
||||
puts("CPU : Altera SOCFPGA Platform\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Print Board information |
||||
*/ |
||||
int checkboard(void) |
||||
{ |
||||
puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Initialization function which happen at early stage of c code |
||||
*/ |
||||
int board_early_init_f(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
int board_init(void) |
||||
{ |
||||
icache_enable(); |
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) |
||||
int overwrite_console(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* DesignWare Ethernet initialization |
||||
*/ |
||||
/* We know all the init functions have been run now */ |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return 0; |
||||
} |
@ -0,0 +1,236 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/arch/socfpga_base_addrs.h> |
||||
|
||||
/*
|
||||
* High level configuration |
||||
*/ |
||||
|
||||
#define CONFIG_ARMV7 |
||||
#define CONFIG_L2_OFF |
||||
#define CONFIG_SYS_DCACHE_OFF |
||||
#undef CONFIG_USE_IRQ |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_SINGLE_BOOTLOADER |
||||
#define CONFIG_SOCFPGA |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x08000040 |
||||
#define V_NS16550_CLK 1000000 |
||||
#define CONFIG_BAUDRATE 57600 |
||||
#define CONFIG_SYS_HZ 1000 |
||||
#define CONFIG_TIMER_CLOCK_KHZ 2400 |
||||
#define CONFIG_SYS_LOAD_ADDR 0x7fc0 |
||||
|
||||
/* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_CBSIZE 256 |
||||
/* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
|
||||
/*
|
||||
* Display CPU and Board Info |
||||
*/ |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
/*
|
||||
* Enable early stage initialization at C environment |
||||
*/ |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
|
||||
/* flat device tree */ |
||||
#define CONFIG_OF_LIBFDT |
||||
/* skip updating the FDT blob */ |
||||
#define CONFIG_FDT_BLOB_SKIP_UPDATE |
||||
/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ |
||||
#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) |
||||
|
||||
#define CONFIG_SPL_RAM_DEVICE |
||||
#define CONFIG_SPL_STACK (&__stack_start) |
||||
#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) |
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) |
||||
|
||||
/*
|
||||
* Memory allocation (MALLOC) |
||||
*/ |
||||
/* Room required on the stack for the environment data */ |
||||
#define CONFIG_ENV_SIZE 1024 |
||||
/* Size of DRAM reserved for malloc() use */ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
||||
|
||||
/* SP location before relocation, must use scratch RAM */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 |
||||
/* Reserving 0x100 space at back of scratch RAM for debug info */ |
||||
#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) |
||||
/* Stack pointer prior relocation, must situated at on-chip RAM */ |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE) |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#include <config_cmd_default.h> |
||||
/* FAT file system support */ |
||||
#define CONFIG_CMD_FAT |
||||
|
||||
|
||||
/*
|
||||
* Misc |
||||
*/ |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
#undef CONFIG_PARTITIONS |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment setup |
||||
*/ |
||||
|
||||
/* Delay before automatically booting the default image */ |
||||
#define CONFIG_BOOTDELAY 3 |
||||
/* Enable auto completion of commands using TAB */ |
||||
#define CONFIG_AUTO_COMPLETE |
||||
/* use "hush" command parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_CMD_RUN |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run ramboot" |
||||
|
||||
/*
|
||||
* arguments passed to the bootm command. The value of |
||||
* CONFIG_BOOTARGS goes into the environment value "bootargs". |
||||
* Do note the value will overide also the chosen node in FDT blob. |
||||
*/ |
||||
#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"verify=n\0" \
|
||||
"loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" \
|
||||
"bootimage=uImage\0" \
|
||||
"fdt_addr=100\0" \
|
||||
"fsloadcmd=ext2load\0" \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" \
|
||||
"qspiroot=/dev/mtdblock0\0" \
|
||||
"qspirootfstype=jffs2\0" \
|
||||
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
|
||||
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" |
||||
|
||||
/* using environment setting for stdin, stdout, stderr */ |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
/* Enable the call to overwrite_console() */ |
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
||||
/* Enable overwrite of previous console environment settings */ |
||||
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
||||
|
||||
/* max number of command args */ |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
|
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
/*
|
||||
* SDRAM Memory Map |
||||
*/ |
||||
/* We have 1 bank of DRAM */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
/* SDRAM Bank #1 */ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
/* SDRAM memory size */ |
||||
#define PHYS_SDRAM_1_SIZE 0x80000000 |
||||
|
||||
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 |
||||
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define UART0_BASE SOCFPGA_UART0_ADDRESS |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4 |
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550_COM1 UART0_BASE |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
/*
|
||||
* FLASH |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/*
|
||||
* L4 OSC1 Timer 0 |
||||
*/ |
||||
/* This timer use eosc1 where the clock frequency is fixed
|
||||
* throughout any condition */ |
||||
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS |
||||
|
||||
/* reload value when timer count to zero */ |
||||
#define TIMER_LOAD_VAL 0xFFFFFFFF |
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
|
||||
/*
|
||||
* SPL "Second Program Loader" aka Initial Software |
||||
*/ |
||||
|
||||
/* Enable building of SPL globally */ |
||||
#define CONFIG_SPL |
||||
#define CONFIG_SPL_FRAMEWORK |
||||
|
||||
/* TEXT_BASE for linking the SPL binary */ |
||||
#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 |
||||
|
||||
/* Stack size for SPL */ |
||||
#define CONFIG_SPL_STACK_SIZE (4 * 1024) |
||||
|
||||
/* MALLOC size for SPL */ |
||||
#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) |
||||
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
#define CONFIG_SPL_BOARD_INIT |
||||
|
||||
#define CHUNKSZ_CRC32 (1 * 1024) |
||||
|
||||
#define CONFIG_CRC32_VERIFY |
||||
|
||||
/* Linker script for SPL */ |
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" |
||||
|
||||
/* Support for common/libcommon.o in SPL binary */ |
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
/* Support for lib/libgeneric.o in SPL binary */ |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue