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ARM: rmobile: Convert R8A7791 Porter board to DM and DT

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Convert the R8A7791 Porter board to DM and DT. This implies mostly
enabling the necessary configuration options and plucking out the
ad-hoc configuration from the board file. Moreover, the pre-reloc
malloc size was increased to allow the clock driver to start up
early without running out of malloc space and the early stack was
moved further up in the DRAM to avoid rewriting U-Boot itself.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
master
Marek Vasut 7 years ago committed by Marek Vasut
parent bb834b6247
commit 789edf694c
5 changed files with 31 additions and 141 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 2
      board/renesas/porter/Makefile
  2. 123
      board/renesas/porter/porter.c
  3. 24
      configs/porter_defconfig
  4. 21
      include/configs/porter.h
  5. 2
      include/configs/rcar-gen2-common.h

2
board/renesas/porter/Makefile
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@ -7,4 +7,4 @@
# SPDX-License-Identifier: GPL-2.0
#
obj-y := porter.o qos.o ../rcar-common/common.o
obj-y := porter.o qos.o

123
board/renesas/porter/porter.c
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@ -47,11 +47,7 @@ void s_init(void)
qos_init();
}
#define TMU0_MSTP125 (1 << 25)
#define SDHI0_MSTP314 (1 << 14)
#define SDHI2_MSTP311 (1 << 11)
#define SCIF0_MSTP721 (1 << 21)
#define ETHER_MSTP813 (1 << 13)
#define TMU0_MSTP125 BIT(25)
#define SD2CKCR 0xE615026C
#define SD_97500KHZ 0x7
@ -60,15 +56,6 @@ int board_early_init_f(void)
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
/* SCIF0 */
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
/* SDHI */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP311);
/*
* SD0 clock is set to 97.5MHz by default.
* Set SD2 to the 97.5MHz as well.
@ -78,112 +65,25 @@ int board_early_init_f(void)
return 0;
}
/* LSI pin pull-up control */
#define PUPR5 0xe6060114
#define PUPR5_ETH 0x3FFC0000
#define PUPR5_ETH_MAGIC (1 << 27)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
/* Init PFC controller */
r8a7791_pinmux_init();
/* Ether Enable */
gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
gpio_request(GPIO_FN_ETH_RX_ER, NULL);
gpio_request(GPIO_FN_ETH_RXD0, NULL);
gpio_request(GPIO_FN_ETH_RXD1, NULL);
gpio_request(GPIO_FN_ETH_LINK, NULL);
gpio_request(GPIO_FN_ETH_REFCLK, NULL);
gpio_request(GPIO_FN_ETH_MDIO, NULL);
gpio_request(GPIO_FN_ETH_TXD1, NULL);
gpio_request(GPIO_FN_ETH_TX_EN, NULL);
gpio_request(GPIO_FN_ETH_TXD0, NULL);
gpio_request(GPIO_FN_ETH_MDC, NULL);
gpio_request(GPIO_FN_IRQ0, NULL);
mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
gpio_direction_output(GPIO_GP_5_22, 0);
mdelay(20);
gpio_set_value(GPIO_GP_5_22, 1);
udelay(1);
return 0;
}
#define CXR24 0xEE7003C0 /* MAC address high register */
#define CXR25 0xEE7003C8 /* MAC address low register */
int board_eth_init(bd_t *bis)
int dram_init(void)
{
#ifdef CONFIG_SH_ETHER
int ret = -ENODEV;
u32 val;
unsigned char enetaddr[6];
ret = sh_eth_initialize(bis);
if (!eth_env_get_enetaddr("ethaddr", enetaddr))
return ret;
/* Set Mac address */
val = enetaddr[0] << 24 | enetaddr[1] << 16 |
enetaddr[2] << 8 | enetaddr[3];
writel(val, CXR24);
val = enetaddr[4] << 8 | enetaddr[5];
writel(val, CXR25);
if (fdtdec_setup_memory_size() != 0)
return -EINVAL;
return ret;
#else
return 0;
#endif
}
int board_mmc_init(bd_t *bis)
int dram_init_banksize(void)
{
int ret = -ENODEV;
#ifdef CONFIG_SH_SDHI
gpio_request(GPIO_FN_SD0_DATA0, NULL);
gpio_request(GPIO_FN_SD0_DATA1, NULL);
gpio_request(GPIO_FN_SD0_DATA2, NULL);
gpio_request(GPIO_FN_SD0_DATA3, NULL);
gpio_request(GPIO_FN_SD0_CLK, NULL);
gpio_request(GPIO_FN_SD0_CMD, NULL);
gpio_request(GPIO_FN_SD0_CD, NULL);
gpio_request(GPIO_FN_SD2_DATA0, NULL);
gpio_request(GPIO_FN_SD2_DATA1, NULL);
gpio_request(GPIO_FN_SD2_DATA2, NULL);
gpio_request(GPIO_FN_SD2_DATA3, NULL);
gpio_request(GPIO_FN_SD2_CLK, NULL);
gpio_request(GPIO_FN_SD2_CMD, NULL);
gpio_request(GPIO_FN_SD2_CD, NULL);
/* SDHI 0 */
gpio_request(GPIO_GP_2_12, NULL);
gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
SH_SDHI_QUIRK_16BIT_BUF);
if (ret)
return ret;
/* SDHI 2 */
gpio_request(GPIO_GP_2_26, NULL);
gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
#endif
return ret;
}
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
fdtdec_setup_memory_banksize();
return 0;
}
@ -215,14 +115,3 @@ void reset_cpu(ulong addr)
val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}
static const struct sh_serial_platdata serial_platdata = {
.base = SCIF0_BASE,
.type = PORT_SCIF,
.clk = CONFIG_P_CLK_FREQ,
};
U_BOOT_DEVICE(porter_serials) = {
.name = "serial_sh",
.platdata = &serial_platdata,
};

24
configs/porter_defconfig
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@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7791=y
CONFIG_TARGET_PORTER=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7791-porter-u-boot"
@ -9,8 +9,10 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
@ -24,14 +26,30 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
CONFIG_NETDEVICES=y
CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
CONFIG_BAUDRATE=38400
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_RCAR_GEN2=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y

21
include/configs/porter.h
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@ -23,7 +23,7 @@
#endif
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
#define CONFIG_SYS_INIT_SP_ADDR 0x7023FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
#endif
@ -57,8 +57,6 @@
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
#define CONFIG_SYS_TMU_CLK_DIV 4
@ -76,21 +74,4 @@
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
/* USB */
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* SD */
#define CONFIG_SH_SDHI_FREQ 97500000
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA 0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA 0x00200000
#endif /* __PORTER_H */

2
include/configs/rcar-gen2-common.h
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@ -21,7 +21,9 @@
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_TMU_TIMER
#ifndef CONFIG_PINCTRL_PFC
#define CONFIG_SH_GPIO_PFC
#endif
/* console */

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