ARM: tegra: pinmux: account for different drivegroup base registers

Tegra210 starts its drive group registers at a different offset from the
APB MISC register block that other SoCs. Update the code to handle this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

arch/arm/include/asm/arch-tegra114/pinmux.h

@@ -313,6 +313,7 @@ enum pmux_func {
 	PMUX_FUNC_COUNT,
 };
 
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING
 #define TEGRA_PMX_SOC_HAS_DRVGRPS
 #define TEGRA_PMX_GRPS_HAVE_LPMD

arch/arm/include/asm/arch-tegra124/pinmux.h

@@ -335,6 +335,7 @@ enum pmux_func {
 	PMUX_FUNC_COUNT,
 };
 
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING
 #define TEGRA_PMX_SOC_HAS_DRVGRPS
 #define TEGRA_PMX_GRPS_HAVE_LPMD

arch/arm/include/asm/arch-tegra20/pinmux.h

@@ -233,6 +233,7 @@ enum pmux_func {
 	PMUX_FUNC_COUNT,
 };
 
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
 #include <asm/arch-tegra/pinmux.h>
 
 #endif /* _TEGRA20_PINMUX_H_ */

arch/arm/include/asm/arch-tegra30/pinmux.h

@@ -391,6 +391,7 @@ enum pmux_func {
 	PMUX_FUNC_COUNT,
 };
 
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
 #define TEGRA_PMX_SOC_HAS_DRVGRPS
 #define TEGRA_PMX_GRPS_HAVE_LPMD
 #define TEGRA_PMX_GRPS_HAVE_SCHMT

arch/arm/mach-tegra/pinmux-common.c

@@ -99,7 +99,7 @@
 
 #endif /* CONFIG_TEGRA20 */
 
-#define DRV_REG(group)	_R(0x868 + ((group) * 4))
+#define DRV_REG(group)	_R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
 
 /*
  * We could force arch-tegraNN/pinmux.h to define all of these. However,