_ Add gpio compatible and aliases for stm32f429 _ Add FMC sdram node with associated new bindings value to manage second bank (ie bank 1). _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl, pwrcfg and gpio nodes. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>master
Patrice Chotard
7 years ago
committed by
Tom Rini
parent
46b1e54b18
commit
791651e390
@ -0,0 +1,204 @@ |
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/* |
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
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* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <dt-bindings/memory/stm32-sdram.h> |
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/{ |
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clocks { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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aliases { |
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/* Aliases for gpios so as to use sequence */ |
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gpio0 = &gpioa; |
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gpio1 = &gpiob; |
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gpio2 = &gpioc; |
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gpio3 = &gpiod; |
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gpio4 = &gpioe; |
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gpio5 = &gpiof; |
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gpio6 = &gpiog; |
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gpio7 = &gpioh; |
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gpio8 = &gpioi; |
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gpio9 = &gpioj; |
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gpio10 = &gpiok; |
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}; |
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|
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soc { |
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u-boot,dm-pre-reloc; |
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pin-controller { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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fmc: fmc@A0000000 { |
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compatible = "st,stm32-fmc"; |
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reg = <0xA0000000 0x1000>; |
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clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; |
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pinctrl-0 = <&fmc_pins>; |
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pinctrl-names = "default"; |
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u-boot,dm-pre-reloc; |
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|
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/* |
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* Memory configuration from sdram datasheet |
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* IS42S16400J |
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*/ |
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bank1: bank@1 { |
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st,sdram-control = /bits/ 8 <NO_COL_8 |
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NO_ROW_12 |
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MWIDTH_16 |
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BANKS_4 |
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CAS_3 |
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SDCLK_2 |
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RD_BURST_EN |
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RD_PIPE_DL_0>; |
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st,sdram-timing = /bits/ 8 <TMRD_3 |
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TXSR_7 |
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TRAS_4 |
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TRC_6 |
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TWR_2 |
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TRP_2 TRCD_2>; |
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st,sdram-refcount = < 1386 >; |
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}; |
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}; |
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}; |
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}; |
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|
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&clk_hse { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&clk_lse { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&clk_i2s_ckin { |
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u-boot,dm-pre-reloc; |
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}; |
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&pwrcfg { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&rcc { |
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u-boot,dm-pre-reloc; |
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}; |
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&gpioa { |
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compatible = "st,stm32-gpio"; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&gpiob { |
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compatible = "st,stm32-gpio"; |
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u-boot,dm-pre-reloc; |
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}; |
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&gpioc { |
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compatible = "st,stm32-gpio"; |
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u-boot,dm-pre-reloc; |
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}; |
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&gpiod { |
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compatible = "st,stm32-gpio"; |
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u-boot,dm-pre-reloc; |
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}; |
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&gpioe { |
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compatible = "st,stm32-gpio"; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&gpiof { |
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compatible = "st,stm32-gpio"; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&gpiog { |
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compatible = "st,stm32-gpio"; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&gpioh { |
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compatible = "st,stm32-gpio"; |
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u-boot,dm-pre-reloc; |
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}; |
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&gpioi { |
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compatible = "st,stm32-gpio"; |
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u-boot,dm-pre-reloc; |
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}; |
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&gpioj { |
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compatible = "st,stm32-gpio"; |
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u-boot,dm-pre-reloc; |
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}; |
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&gpiok { |
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compatible = "st,stm32-gpio"; |
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u-boot,dm-pre-reloc; |
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}; |
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&pinctrl { |
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usart1_pins_a: usart1@0 { |
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u-boot,dm-pre-reloc; |
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pins1 { |
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u-boot,dm-pre-reloc; |
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}; |
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pins2 { |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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fmc_pins: fmc@0 { |
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u-boot,dm-pre-reloc; |
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pins |
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{ |
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pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */ |
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<STM32_PINMUX('D', 9, AF12)>, /* D14 */ |
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<STM32_PINMUX('D', 8, AF12)>, /* D13 */ |
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<STM32_PINMUX('E',15, AF12)>, /* D12 */ |
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<STM32_PINMUX('E',14, AF12)>, /* D11 */ |
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<STM32_PINMUX('E',13, AF12)>, /* D10 */ |
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<STM32_PINMUX('E',12, AF12)>, /* D09 */ |
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<STM32_PINMUX('E',11, AF12)>, /* D08 */ |
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<STM32_PINMUX('E',10, AF12)>, /* D07 */ |
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<STM32_PINMUX('E', 9, AF12)>, /* D06 */ |
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<STM32_PINMUX('E', 8, AF12)>, /* D05 */ |
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<STM32_PINMUX('E', 7, AF12)>, /* D04 */ |
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<STM32_PINMUX('D', 1, AF12)>, /* D03 */ |
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<STM32_PINMUX('D', 0, AF12)>, /* D02 */ |
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<STM32_PINMUX('D',15, AF12)>, /* D01 */ |
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<STM32_PINMUX('D',14, AF12)>, /* D00 */ |
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<STM32_PINMUX('E', 0, AF12)>, /* NBL0 */ |
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<STM32_PINMUX('E', 1, AF12)>, /* NBL1 */ |
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<STM32_PINMUX('G', 5, AF12)>, /* BA1 */ |
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<STM32_PINMUX('G', 4, AF12)>, /* BA0 */ |
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<STM32_PINMUX('G', 1, AF12)>, /* A11 */ |
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<STM32_PINMUX('G', 0, AF12)>, /* A10 */ |
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<STM32_PINMUX('F',15, AF12)>, /* A09 */ |
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<STM32_PINMUX('F',14, AF12)>, /* A08 */ |
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<STM32_PINMUX('F',13, AF12)>, /* A07 */ |
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<STM32_PINMUX('F',12, AF12)>, /* A06 */ |
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<STM32_PINMUX('F', 5, AF12)>, /* A05 */ |
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<STM32_PINMUX('F', 4, AF12)>, /* A04 */ |
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<STM32_PINMUX('F', 3, AF12)>, /* A03 */ |
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<STM32_PINMUX('F', 2, AF12)>, /* A02 */ |
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<STM32_PINMUX('F', 1, AF12)>, /* A01 */ |
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<STM32_PINMUX('F', 0, AF12)>, /* A00 */ |
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<STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */ |
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<STM32_PINMUX('C', 0, AF12)>, /* SDNWE */ |
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<STM32_PINMUX('F',11, AF12)>, /* SDNRAS */ |
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<STM32_PINMUX('G',15, AF12)>, /* SDNCAS */ |
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<STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */ |
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<STM32_PINMUX('G', 8, AF12)>; /* SDCLK */ |
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slew-rate = <2>; |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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}; |
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