Tom Rini
8 years ago
commit
793fd86f72
@ -0,0 +1,22 @@ |
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/* |
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
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* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/dts-v1/; |
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|
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#include "dfi-bt700.dtsi" |
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|
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#include "serial.dtsi" |
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|
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/ { |
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model = "DFI-BT700"; |
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compatible = "dfi,bt700", "intel,baytrail"; |
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|
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aliases { |
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serial0 = &serial; |
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spi0 = &spi; |
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}; |
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}; |
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@ -0,0 +1,308 @@ |
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/* |
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
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* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <dt-bindings/gpio/x86-gpio.h> |
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#include <dt-bindings/interrupt-router/intel-irq.h> |
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|
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#include "skeleton.dtsi" |
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#include "rtc.dtsi" |
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#include "tsc_timer.dtsi" |
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|
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/ { |
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config { |
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silent_console = <0>; |
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}; |
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|
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pch_pinctrl { |
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compatible = "intel,x86-pinctrl"; |
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reg = <0 0>; |
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|
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/* Add UART1 PAD configuration (SIO HS-UART) */ |
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uart1_txd@0 { |
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pad-offset = <0x10>; |
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mode-func = <1>; |
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}; |
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|
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uart1_rxd@0 { |
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pad-offset = <0x20>; |
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mode-func = <1>; |
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}; |
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|
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/* |
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* As of today, the latest version FSP (gold4) for BayTrail |
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* misses the PAD configuration of the SD controller's Card |
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* Detect signal. The default PAD value for the CD pin sets |
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* the pin to work in GPIO mode, which causes card detect |
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* status cannot be reflected by the Present State register |
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* in the SD controller (bit 16 & bit 18 are always zero). |
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* |
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* Configure this pin to function 1 (SD controller). |
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*/ |
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sdmmc3_cd@0 { |
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pad-offset = <0x3a0>; |
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mode-func = <1>; |
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}; |
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}; |
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|
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chosen { |
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stdout-path = "/serial"; |
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}; |
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|
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "intel,baytrail-cpu"; |
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reg = <0>; |
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intel,apic-id = <0>; |
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}; |
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|
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cpu@1 { |
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device_type = "cpu"; |
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compatible = "intel,baytrail-cpu"; |
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reg = <1>; |
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intel,apic-id = <2>; |
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}; |
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|
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cpu@2 { |
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device_type = "cpu"; |
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compatible = "intel,baytrail-cpu"; |
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reg = <2>; |
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intel,apic-id = <4>; |
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}; |
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|
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cpu@3 { |
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device_type = "cpu"; |
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compatible = "intel,baytrail-cpu"; |
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reg = <3>; |
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intel,apic-id = <6>; |
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}; |
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}; |
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|
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pci { |
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compatible = "intel,pci-baytrail", "pci-x86"; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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u-boot,dm-pre-reloc; |
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 |
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0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 |
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0x01000000 0x0 0x2000 0x2000 0 0xe000>; |
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|
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pciuart0: uart@1e,3 { |
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compatible = "pci8086,0f0a.00", |
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"pci8086,0f0a", |
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"pciclass,070002", |
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"pciclass,0700", |
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"ns16550"; |
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u-boot,dm-pre-reloc; |
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reg = <0x0200f310 0x0 0x0 0x0 0x0>; |
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reg-shift = <2>; |
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clock-frequency = <58982400>; |
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current-speed = <115200>; |
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}; |
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|
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pch@1f,0 { |
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reg = <0x0000f800 0 0 0 0>; |
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compatible = "pci8086,0f1c", "intel,pch9"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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|
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irq-router { |
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compatible = "intel,irq-router"; |
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intel,pirq-config = "ibase"; |
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intel,ibase-offset = <0x50>; |
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intel,actl-addr = <0>; |
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intel,pirq-link = <8 8>; |
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intel,pirq-mask = <0xdee0>; |
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intel,pirq-routing = < |
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/* BayTrail PCI devices */ |
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PCI_BDF(0, 2, 0) INTA PIRQA |
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PCI_BDF(0, 3, 0) INTA PIRQA |
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PCI_BDF(0, 16, 0) INTA PIRQA |
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PCI_BDF(0, 17, 0) INTA PIRQA |
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PCI_BDF(0, 18, 0) INTA PIRQA |
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PCI_BDF(0, 19, 0) INTA PIRQA |
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PCI_BDF(0, 20, 0) INTA PIRQA |
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PCI_BDF(0, 21, 0) INTA PIRQA |
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PCI_BDF(0, 22, 0) INTA PIRQA |
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PCI_BDF(0, 23, 0) INTA PIRQA |
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PCI_BDF(0, 24, 0) INTA PIRQA |
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PCI_BDF(0, 24, 1) INTC PIRQC |
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PCI_BDF(0, 24, 2) INTD PIRQD |
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PCI_BDF(0, 24, 3) INTB PIRQB |
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PCI_BDF(0, 24, 4) INTA PIRQA |
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PCI_BDF(0, 24, 5) INTC PIRQC |
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PCI_BDF(0, 24, 6) INTD PIRQD |
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PCI_BDF(0, 24, 7) INTB PIRQB |
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PCI_BDF(0, 26, 0) INTA PIRQA |
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PCI_BDF(0, 27, 0) INTA PIRQA |
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PCI_BDF(0, 28, 0) INTA PIRQA |
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PCI_BDF(0, 28, 1) INTB PIRQB |
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PCI_BDF(0, 28, 2) INTC PIRQC |
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PCI_BDF(0, 28, 3) INTD PIRQD |
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PCI_BDF(0, 29, 0) INTA PIRQA |
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PCI_BDF(0, 30, 0) INTA PIRQA |
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PCI_BDF(0, 30, 1) INTD PIRQD |
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PCI_BDF(0, 30, 2) INTB PIRQB |
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PCI_BDF(0, 30, 3) INTC PIRQC |
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PCI_BDF(0, 30, 4) INTD PIRQD |
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PCI_BDF(0, 30, 5) INTB PIRQB |
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PCI_BDF(0, 31, 3) INTB PIRQB |
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|
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/* |
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* PCIe root ports downstream |
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* interrupts |
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*/ |
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PCI_BDF(1, 0, 0) INTA PIRQA |
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PCI_BDF(1, 0, 0) INTB PIRQB |
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PCI_BDF(1, 0, 0) INTC PIRQC |
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PCI_BDF(1, 0, 0) INTD PIRQD |
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PCI_BDF(2, 0, 0) INTA PIRQB |
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PCI_BDF(2, 0, 0) INTB PIRQC |
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PCI_BDF(2, 0, 0) INTC PIRQD |
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PCI_BDF(2, 0, 0) INTD PIRQA |
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PCI_BDF(3, 0, 0) INTA PIRQC |
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PCI_BDF(3, 0, 0) INTB PIRQD |
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PCI_BDF(3, 0, 0) INTC PIRQA |
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PCI_BDF(3, 0, 0) INTD PIRQB |
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PCI_BDF(4, 0, 0) INTA PIRQD |
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PCI_BDF(4, 0, 0) INTB PIRQA |
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PCI_BDF(4, 0, 0) INTC PIRQB |
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PCI_BDF(4, 0, 0) INTD PIRQC |
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>; |
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}; |
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spi: spi { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "intel,ich9-spi"; |
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spi-flash@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0>; |
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compatible = "stmicro,n25q064a", |
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"spi-flash"; |
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memory-map = <0xff800000 0x00800000>; |
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rw-mrc-cache { |
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label = "rw-mrc-cache"; |
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reg = <0x006f0000 0x00010000>; |
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}; |
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}; |
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}; |
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|
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gpioa { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0 0x20>; |
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bank-name = "A"; |
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}; |
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gpiob { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0x20 0x20>; |
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bank-name = "B"; |
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}; |
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gpioc { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0x40 0x20>; |
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bank-name = "C"; |
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}; |
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gpiod { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0x60 0x20>; |
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bank-name = "D"; |
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}; |
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gpioe { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0x80 0x20>; |
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bank-name = "E"; |
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}; |
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gpiof { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0xA0 0x20>; |
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bank-name = "F"; |
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}; |
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}; |
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}; |
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fsp { |
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compatible = "intel,baytrail-fsp"; |
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fsp,mrc-init-tseg-size = <0>; |
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fsp,mrc-init-mmio-size = <0x800>; |
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fsp,mrc-init-spd-addr1 = <0xa0>; |
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fsp,mrc-init-spd-addr2 = <0xa2>; |
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fsp,emmc-boot-mode = <1>; |
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fsp,enable-sdio; |
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fsp,enable-sdcard; |
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fsp,enable-hsuart0; |
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fsp,enable-hsuart1; |
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fsp,enable-spi; |
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fsp,enable-sata; |
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fsp,sata-mode = <1>; |
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fsp,enable-lpe; |
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fsp,lpss-sio-enable-pci-mode; |
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fsp,enable-dma0; |
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fsp,enable-dma1; |
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fsp,enable-i2c0; |
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fsp,enable-i2c1; |
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fsp,enable-i2c2; |
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fsp,enable-i2c3; |
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fsp,enable-i2c4; |
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fsp,enable-i2c5; |
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fsp,enable-i2c6; |
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fsp,enable-pwm0; |
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fsp,enable-pwm1; |
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fsp,igd-dvmt50-pre-alloc = <2>; |
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fsp,aperture-size = <2>; |
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fsp,gtt-size = <2>; |
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fsp,scc-enable-pci-mode; |
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fsp,os-selection = <4>; |
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fsp,emmc45-ddr50-enabled; |
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fsp,emmc45-retune-timer-value = <8>; |
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fsp,enable-igd; |
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fsp,enable-memory-down; |
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fsp,memory-down-params { |
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compatible = "intel,baytrail-fsp-mdp"; |
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fsp,dram-speed = <2>; /* 2=1333MHz */ |
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fsp,dram-type = <1>; /* 1=DDR3L */ |
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fsp,dimm-0-enable; |
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fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ |
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fsp,dimm-density = <3>; /* 3=8Gbit */ |
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fsp,dimm-bus-width = <3>; /* 3=64bits */ |
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fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */ |
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|
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/* These following values might need a re-visit */ |
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fsp,dimm-tcl = <8>; |
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fsp,dimm-trpt-rcd = <8>; |
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fsp,dimm-twr = <8>; |
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fsp,dimm-twtr = <4>; |
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fsp,dimm-trrd = <6>; |
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fsp,dimm-trtp = <4>; |
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fsp,dimm-tfaw = <22>; |
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}; |
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}; |
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|
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microcode { |
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update@0 { |
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#include "microcode/m0130673325.dtsi" |
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}; |
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update@1 { |
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#include "microcode/m0130679907.dtsi" |
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}; |
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}; |
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}; |
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@ -0,0 +1,21 @@ |
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/* |
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
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* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/dts-v1/; |
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|
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#include "dfi-bt700.dtsi" |
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|
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/ { |
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model = "theadorable-x86-DFI-BT700"; |
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compatible = "anonymous,theadorable-x86-dfi-bt700", "dfi,bt700", |
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"intel,baytrail"; |
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|
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aliases { |
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serial0 = &pciuart0; |
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spi0 = &spi; |
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}; |
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}; |
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@ -0,0 +1,29 @@ |
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# |
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# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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|
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if VENDOR_DFI |
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|
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choice |
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prompt "Mainboard model" |
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optional |
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|
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config TARGET_DFI_BT700 |
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bool "DFI BT700 BayTrail" |
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help |
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This is the DFI Q7X-151 baseboard equipped with the |
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DFI BayTrail Bt700 SoM. It contains an Atom E3845 with |
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Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2, |
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USB 3, SATA, serial console and DisplayPort video out. |
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It requires some binary blobs - see README.x86 for details. |
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|
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Note that PCIE_ECAM_BASE is set up by the FSP so the value used |
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by U-Boot matches that value. |
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|
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endchoice |
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|
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source "board/dfi/dfi-bt700/Kconfig" |
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|
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endif |
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@ -0,0 +1,28 @@ |
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if TARGET_DFI_BT700 |
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|
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config SYS_BOARD |
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default "dfi-bt700" |
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|
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config SYS_VENDOR |
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default "dfi" |
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|
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config SYS_SOC |
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default "baytrail" |
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|
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config SYS_CONFIG_NAME |
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default "dfi-bt700" |
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|
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config SYS_TEXT_BASE |
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default 0xfff00000 if !EFI_STUB |
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default 0x01110000 if EFI_STUB |
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|
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config BOARD_SPECIFIC_OPTIONS # dummy |
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def_bool y |
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select X86_RESET_VECTOR if !EFI_STUB |
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select INTEL_BAYTRAIL |
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select BOARD_ROMSIZE_KB_8192 |
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|
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config PCIE_ECAM_BASE |
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default 0xe0000000 |
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|
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endif |
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@ -0,0 +1,10 @@ |
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congatec DFI-BT700 |
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M: Stefan Roese <sr@denx.de> |
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S: Maintained |
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F: board/dfi/dfi-bt700 |
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F: include/configs/dfi-bt700.h |
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F: configs/dfi-bt700-q7x-151_defconfig |
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F: configs/theadorable-x86-dfi-bt700_defconfig |
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F: arch/x86/dts/dfi-bt700.dtsi |
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F: arch/x86/dts/dfi-bt700-q7x-151.dts |
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F: arch/x86/dts/theadorable-x86-dfi-bt700.dts |
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@ -0,0 +1,8 @@ |
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#
|
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# Copyright (C) 2015, Google, Inc
|
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#
|
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# SPDX-License-Identifier: GPL-2.0+
|
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#
|
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|
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obj-y += dfi-bt700.o start.o
|
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obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
|
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@ -0,0 +1,13 @@ |
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/* |
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/* Power Button */ |
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Device (PWRB) |
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{ |
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Name(_HID, EISAID("PNP0C0C")) |
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} |
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|
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/* TODO: Need add Nuvoton SuperIO chipset NCT6102D ASL codes */ |
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@ -0,0 +1,30 @@ |
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/*
|
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* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <nuvoton_nct6102d.h> |
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#include <asm/gpio.h> |
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#include <asm/ibmpc.h> |
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#include <asm/pnp_def.h> |
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|
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int board_early_init_f(void) |
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{ |
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#ifdef CONFIG_INTERNAL_UART |
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/* Disable the legacy UART which is enabled per default */ |
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nct6102d_uarta_disable(); |
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#else |
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/*
|
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* The FSP enables the BayTrail internal legacy UART (again). |
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* Disable it again, so that the Nuvoton one can be used. |
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*/ |
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setup_internal_uart(0); |
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#endif |
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|
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/* Disable the watchdog which is enabled per default */ |
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nct6102d_wdt_disable(); |
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|
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return 0; |
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} |
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@ -0,0 +1,14 @@ |
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/* |
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) |
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{ |
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/* platform specific */ |
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#include <asm/arch/acpi/platform.asl> |
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|
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/* board specific */ |
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#include "acpi/mainboard.asl" |
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} |
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@ -0,0 +1,9 @@ |
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/* |
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* Copyright (C) 2015, Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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.globl early_board_init
|
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early_board_init: |
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jmp early_board_init_ret |
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@ -0,0 +1,63 @@ |
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CONFIG_X86=y |
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CONFIG_DM_I2C=y |
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CONFIG_VENDOR_DFI=y |
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CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151" |
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CONFIG_TARGET_DFI_BT700=y |
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CONFIG_HAVE_INTEL_ME=y |
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CONFIG_ENABLE_MRC_CACHE=y |
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CONFIG_SMP=y |
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CONFIG_HAVE_VGA_BIOS=y |
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CONFIG_GENERATE_PIRQ_TABLE=y |
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CONFIG_GENERATE_MP_TABLE=y |
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CONFIG_GENERATE_ACPI_TABLE=y |
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CONFIG_SEABIOS=y |
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CONFIG_FIT=y |
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CONFIG_FIT_SIGNATURE=y |
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CONFIG_BOOTSTAGE=y |
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CONFIG_BOOTSTAGE_REPORT=y |
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CONFIG_HUSH_PARSER=y |
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CONFIG_CMD_CPU=y |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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CONFIG_CMD_MMC=y |
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CONFIG_CMD_SF=y |
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CONFIG_CMD_SPI=y |
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CONFIG_CMD_USB=y |
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CONFIG_CMD_GPIO=y |
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# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_CMD_DHCP=y |
||||
# CONFIG_CMD_NFS is not set |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_BOOTSTAGE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_REGMAP=y |
||||
CONFIG_SYSCON=y |
||||
CONFIG_CPU=y |
||||
CONFIG_NUVOTON_NCT6102D=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_GIGADEVICE=y |
||||
CONFIG_SPI_FLASH_MACRONIX=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_SPI_FLASH_WINBOND=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_E1000=y |
||||
CONFIG_DM_PCI=y |
||||
CONFIG_DM_RTC=y |
||||
CONFIG_DEBUG_UART=y |
||||
CONFIG_DEBUG_UART_BASE=0x3f8 |
||||
CONFIG_DEBUG_UART_CLOCK=1843200 |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_ICH_SPI=y |
||||
CONFIG_TIMER=y |
||||
CONFIG_USB=y |
||||
CONFIG_DM_USB=y |
||||
CONFIG_VIDEO_VESA=y |
||||
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y |
||||
CONFIG_FRAMEBUFFER_VESA_MODE_114=y |
||||
CONFIG_USE_PRIVATE_LIBGCC=y |
||||
@ -0,0 +1,60 @@ |
||||
CONFIG_X86=y |
||||
CONFIG_DM_I2C=y |
||||
CONFIG_VENDOR_DFI=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="theadorable-x86-dfi-bt700" |
||||
CONFIG_TARGET_DFI_BT700=y |
||||
CONFIG_HAVE_INTEL_ME=y |
||||
CONFIG_ENABLE_MRC_CACHE=y |
||||
CONFIG_SMP=y |
||||
CONFIG_HAVE_VGA_BIOS=y |
||||
CONFIG_GENERATE_PIRQ_TABLE=y |
||||
CONFIG_GENERATE_MP_TABLE=y |
||||
CONFIG_GENERATE_ACPI_TABLE=y |
||||
CONFIG_SEABIOS=y |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_SIGNATURE=y |
||||
CONFIG_BOOTSTAGE=y |
||||
CONFIG_BOOTSTAGE_REPORT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_CPU=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_SPI=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_GPIO=y |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_CMD_DHCP=y |
||||
# CONFIG_CMD_NFS is not set |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_BOOTSTAGE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_REGMAP=y |
||||
CONFIG_SYSCON=y |
||||
CONFIG_CPU=y |
||||
CONFIG_NUVOTON_NCT6102D=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_GIGADEVICE=y |
||||
CONFIG_SPI_FLASH_MACRONIX=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_SPI_FLASH_WINBOND=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_E1000=y |
||||
CONFIG_DM_PCI=y |
||||
CONFIG_DM_RTC=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_ICH_SPI=y |
||||
CONFIG_TIMER=y |
||||
CONFIG_USB=y |
||||
CONFIG_DM_USB=y |
||||
CONFIG_VIDEO_VESA=y |
||||
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y |
||||
CONFIG_FRAMEBUFFER_VESA_MODE_114=y |
||||
CONFIG_USE_PRIVATE_LIBGCC=y |
||||
@ -0,0 +1,56 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <nuvoton_nct6102d.h> |
||||
#include <asm/io.h> |
||||
#include <asm/pnp_def.h> |
||||
|
||||
static void superio_outb(int reg, int val) |
||||
{ |
||||
outb(reg, NCT_EFER); |
||||
outb(val, NCT_EFDR); |
||||
} |
||||
|
||||
static inline int superio_inb(int reg) |
||||
{ |
||||
outb(reg, NCT_EFER); |
||||
return inb(NCT_EFDR); |
||||
} |
||||
|
||||
static int superio_enter(void) |
||||
{ |
||||
outb(NCT_ENTRY_KEY, NCT_EFER); /* Enter extended function mode */ |
||||
outb(NCT_ENTRY_KEY, NCT_EFER); /* Again according to manual */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void superio_select(int ld) |
||||
{ |
||||
superio_outb(NCT_LD_SELECT_REG, ld); |
||||
} |
||||
|
||||
static void superio_exit(void) |
||||
{ |
||||
outb(NCT_EXIT_KEY, NCT_EFER); /* Leave extended function mode */ |
||||
} |
||||
|
||||
/*
|
||||
* The Nuvoton NCT6102D starts per default after reset with both, |
||||
* the internal watchdog and the internal legacy UART enabled. This |
||||
* code provides a function to disable the watchdog. |
||||
*/ |
||||
int nct6102d_wdt_disable(void) |
||||
{ |
||||
superio_enter(); |
||||
/* Select logical device for WDT */ |
||||
superio_select(NCT6102D_LD_WDT); |
||||
superio_outb(NCT6102D_WDT_TIMEOUT, 0x00); |
||||
superio_exit(); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,74 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <configs/x86-common.h> |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (1 << 20) |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
|
||||
#ifndef CONFIG_INTERNAL_UART |
||||
/* Use BayTrail internal HS UART which is memory-mapped */ |
||||
#undef CONFIG_SYS_NS16550_PORT_MAPPED |
||||
#endif |
||||
|
||||
#define CONFIG_PCI_PNP |
||||
|
||||
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ |
||||
"stdout=serial\0" \
|
||||
"stderr=serial\0" |
||||
|
||||
#define CONFIG_SCSI_DEV_LIST \ |
||||
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
|
||||
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT} |
||||
|
||||
#define CONFIG_MMC |
||||
#define CONFIG_SDHCI |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_MMC_SDMA |
||||
|
||||
#undef CONFIG_USB_MAX_CONTROLLER_COUNT |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
||||
|
||||
#define CONFIG_USB_HOST_ETHER |
||||
#define CONFIG_USB_ETHER_ASIX |
||||
#define CONFIG_USB_ETHER_SMSC95XX |
||||
#define CONFIG_USB_ETHER_MCS7830 |
||||
#define CONFIG_USB_ETHER_RTL8152 |
||||
|
||||
#define VIDEO_IO_OFFSET 0 |
||||
#define CONFIG_X86EMU_RAW_IO |
||||
#define CONFIG_CMD_BMP |
||||
|
||||
#define CONFIG_ENV_SECT_SIZE 0x1000 |
||||
#define CONFIG_ENV_OFFSET 0x006ef000 |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#undef CONFIG_BOOTCOMMAND |
||||
|
||||
#define CONFIG_BOOTARGS \ |
||||
"root=/dev/sda1 ro quiet" |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"load scsi 0:1 03000000 /boot/vmlinuz-${kernel-ver}-generic;" \
|
||||
"load scsi 0:1 04000000 /boot/initrd.img-${kernel-ver}-generic;" \
|
||||
"run boot" |
||||
|
||||
#undef CONFIG_EXTRA_ENV_SETTINGS |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"kernel-ver=4.4.0-24\0" \
|
||||
"boot=zboot 03000000 0 04000000 ${filesize}\0" \
|
||||
"upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;" \
|
||||
"sf probe;sf update 100000 0 800000;saveenv\0" |
||||
|
||||
#define CONFIG_PREBOOT |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,34 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _NUVOTON_NCT6102D_H_ |
||||
#define _NUVOTON_NCT6102D_H_ |
||||
|
||||
/* I/O address of Nuvoton Super IO chip */ |
||||
#define NCT6102D_IO_PORT 0x4e |
||||
|
||||
/* Extended Function Enable Registers */ |
||||
#define NCT_EFER (NCT6102D_IO_PORT + 0) |
||||
/* Extended Function Index Register (same as EFER) */ |
||||
#define NCT_EFIR (NCT6102D_IO_PORT + 0) |
||||
/* Extended Function Data Register */ |
||||
#define NCT_EFDR (NCT_EFIR + 1) |
||||
|
||||
#define NCT_LD_SELECT_REG 0x07 |
||||
|
||||
/* Logical device number */ |
||||
#define NCT6102D_LD_UARTA 0x02 |
||||
#define NCT6102D_LD_WDT 0x08 |
||||
|
||||
#define NCT6102D_UARTA_ENABLE 0x30 |
||||
#define NCT6102D_WDT_TIMEOUT 0xf1 |
||||
|
||||
#define NCT_ENTRY_KEY 0x87 |
||||
#define NCT_EXIT_KEY 0xaa |
||||
|
||||
int nct6102d_wdt_disable(void); |
||||
|
||||
#endif /* _NUVOTON_NCT6102D_H_ */ |
||||
Loading…
Reference in new issue