* Patch by Keith Outwater, 28 Apr 2003: - Miscellaneous corrections and additions to GEN860T board specific code. - Added GEN860_SC variant to GEN860T. - Miscellaneous corrections to GEN860T documentation. - Correct duplicate entry in U-Boot CREDITS file. - Add GEN860T_SC entry in MAINTAINERS file. - Update CREDITS file with GEN860T_SC info. * Update Smiths Aerospace addresses in MAINTAINERS file * Fix error handling in hush's version of "run" commandmaster
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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$(LIB): .depend $(OBJS) |
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$(AR) crv $@ $^
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,366 @@ |
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/*
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <ioports.h> |
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#include <mpc8260.h> |
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/*
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* I/O Port configuration table |
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* |
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* if conf is 1, then that port pin will be configured at boot time |
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* according to the five values podr/pdir/ppar/psor/pdat for that entry |
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*/ |
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const iop_conf_t iop_conf_tab[4][32] = { |
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/* Port A configuration */ |
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{ /* conf ppar psor pdir podr pdat */ |
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/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ |
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/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ |
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/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ |
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/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ |
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/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ |
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/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ |
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/* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ |
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/* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ |
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/* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ |
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/* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ |
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/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ |
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/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ |
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/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ |
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/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ |
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/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ |
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/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ |
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/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ |
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/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ |
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/* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ |
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/* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ |
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/* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ |
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/* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ |
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#if 1 |
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/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ |
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/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ |
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#else |
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/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ |
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/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ |
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#endif |
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/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ |
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/* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ |
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/* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ |
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/* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ |
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/* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ |
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/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ |
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/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ |
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/* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ |
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}, |
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/* Port B configuration */ |
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{ /* conf ppar psor pdir podr pdat */ |
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
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/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ |
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/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ |
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/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ |
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/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ |
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/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ |
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/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ |
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/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ |
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/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ |
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/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ |
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/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ |
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/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ |
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/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ |
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/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ |
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/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ |
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ |
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ |
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ |
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ |
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}, |
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/* Port C */ |
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{ /* conf ppar psor pdir podr pdat */ |
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/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ |
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/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ |
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/* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ |
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/* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ |
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/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ |
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/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ |
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/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ |
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/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ |
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/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ |
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/* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ |
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/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ |
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/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ |
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ |
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ |
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/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ |
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/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ |
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#if 0 |
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/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ |
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#else |
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/* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* PC15 */ |
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#endif |
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/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ |
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/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ |
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/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ |
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/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ |
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/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ |
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/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ |
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/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ |
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/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ |
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/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ |
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/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ |
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/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ |
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/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ |
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/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ |
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/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ |
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/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ |
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}, |
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/* Port D */ |
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{ /* conf ppar psor pdir podr pdat */ |
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ |
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ |
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/* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ |
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/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ |
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/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ |
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/* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ |
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/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ |
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/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ |
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/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ |
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/* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ |
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/* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ |
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/* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ |
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/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ |
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/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ |
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/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ |
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/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ |
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#if defined(CONFIG_SOFT_I2C) |
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/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ |
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/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ |
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#else |
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#if defined(CONFIG_HARD_I2C) |
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ |
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#else /* normal I/O port pins */ |
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ |
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#endif |
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#endif |
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
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/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
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/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
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/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ |
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/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ |
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/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ |
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#if 0 |
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/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ |
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#else |
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/* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* PD4 */ |
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#endif |
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ |
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ |
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ |
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ |
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} |
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}; |
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/* ------------------------------------------------------------------------- */ |
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/* Check Board Identity:
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*/ |
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int checkboard (void) |
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{ |
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printf ("Board: ATC\n"); |
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return 0; |
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} |
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/* ------------------------------------------------------------------------- */ |
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/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
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* |
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* This routine performs standard 8260 initialization sequence |
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* and calculates the available memory size. It may be called |
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* several times to try different SDRAM configurations on both |
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* 60x and local buses. |
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*/ |
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static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, |
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ulong orx, volatile uchar * base) |
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{ |
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volatile uchar c = 0xff; |
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ulong cnt, val; |
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volatile ulong *addr; |
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volatile uint *sdmr_ptr; |
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volatile uint *orx_ptr; |
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int i; |
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ulong save[32]; /* to make test non-destructive */ |
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ulong maxsize; |
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/* We must be able to test a location outsize the maximum legal size
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* to find out THAT we are outside; but this address still has to be |
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* mapped by the controller. That means, that the initial mapping has |
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* to be (at least) twice as large as the maximum expected size. |
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*/ |
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maxsize = (1 + (~orx | 0x7fff)) / 2; |
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/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
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* we are configuring CS1 if base != 0 |
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*/ |
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sdmr_ptr = &memctl->memc_psdmr; |
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orx_ptr = &memctl->memc_or2; |
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*orx_ptr = orx; |
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/*
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* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): |
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* |
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* "At system reset, initialization software must set up the |
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* programmable parameters in the memory controller banks registers |
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* (ORx, BRx, P/LSDMR). After all memory parameters are configured, |
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* system software should execute the following initialization sequence |
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* for each SDRAM device. |
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* |
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* 1. Issue a PRECHARGE-ALL-BANKS command |
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* 2. Issue eight CBR REFRESH commands |
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* 3. Issue a MODE-SET command to initialize the mode register |
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* |
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* The initial commands are executed by setting P/LSDMR[OP] and |
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* accessing the SDRAM with a single-byte transaction." |
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* |
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* The appropriate BRx/ORx registers have already been set when we |
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* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. |
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*/ |
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*sdmr_ptr = sdmr | PSDMR_OP_PREA; |
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*base = c; |
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*sdmr_ptr = sdmr | PSDMR_OP_CBRR; |
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for (i = 0; i < 8; i++) |
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*base = c; |
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*sdmr_ptr = sdmr | PSDMR_OP_MRW; |
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*(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ |
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*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; |
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*base = c; |
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/*
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* Check memory range for valid RAM. A simple memory test determines |
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* the actually available RAM size between addresses `base' and |
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* `base + maxsize'. Some (not all) hardware errors are detected: |
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* - short between address lines |
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* - short between data lines |
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*/ |
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i = 0; |
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for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { |
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addr = (volatile ulong *) base + cnt; /* pointer arith! */ |
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save[i++] = *addr; |
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*addr = ~cnt; |
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} |
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addr = (volatile ulong *) base; |
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save[i] = *addr; |
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*addr = 0; |
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if ((val = *addr) != 0) { |
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*addr = save[i]; |
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return (0); |
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} |
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for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { |
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addr = (volatile ulong *) base + cnt; /* pointer arith! */ |
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val = *addr; |
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*addr = save[--i]; |
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if (val != ~cnt) { |
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/* Write the actual size to ORx
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*/ |
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*orx_ptr = orx | ~(cnt * sizeof (long) - 1); |
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return (cnt * sizeof (long)); |
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} |
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} |
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return (maxsize); |
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} |
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long int initdram (int board_type) |
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{ |
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volatile immap_t *immap = (immap_t *) CFG_IMMR; |
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volatile memctl8260_t *memctl = &immap->im_memctl; |
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#ifndef CFG_RAMBOOT |
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ulong size8, size9; |
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#endif |
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long psize; |
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|
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psize = 8 * 1024 * 1024; |
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|
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memctl->memc_mptpr = CFG_MPTPR; |
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memctl->memc_psrt = CFG_PSRT; |
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|
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#ifndef CFG_RAMBOOT |
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/* 60x SDRAM setup:
|
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*/ |
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size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, |
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(uchar *) CFG_SDRAM_BASE); |
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size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, |
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(uchar *) CFG_SDRAM_BASE); |
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|
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if (size8 < size9) { |
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psize = size9; |
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printf ("(60x:9COL) "); |
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} else { |
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psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, |
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(uchar *) CFG_SDRAM_BASE); |
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printf ("(60x:8COL) "); |
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} |
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#endif /* CFG_RAMBOOT */ |
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icache_enable (); |
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|
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return (psize); |
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} |
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|
||||
#if (CONFIG_COMMANDS & CFG_CMD_DOC) |
||||
extern void doc_probe (ulong physadr); |
||||
void doc_init (void) |
||||
{ |
||||
doc_probe (CFG_DOC_BASE); |
||||
} |
||||
#endif |
@ -0,0 +1,43 @@ |
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# ATC boards
|
||||
#
|
||||
|
||||
# This should be equal to the CFG_FLASH_BASE define in config_atc.h
|
||||
# for the "final" configuration, with U-Boot in flash, or the address
|
||||
# in RAM where U-Boot is loaded at for debugging.
|
||||
#
|
||||
|
||||
ifeq ($(CONFIG_BOOT_ROM),y) |
||||
TEXT_BASE := 0xFF800000
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
|
||||
else |
||||
TEXT_BASE := 0xFF000000
|
||||
endif |
||||
|
||||
# RAM version
|
||||
#TEXT_BASE := 0x100000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
|
@ -0,0 +1,665 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
|
||||
* has nothing to do with the flash chip being 8-bit or 16-bit. |
||||
*/ |
||||
#ifdef CONFIG_FLASH_16BIT |
||||
typedef unsigned short FLASH_PORT_WIDTH; |
||||
typedef volatile unsigned short FLASH_PORT_WIDTHV; |
||||
#define FLASH_ID_MASK 0xFFFF |
||||
#else |
||||
typedef unsigned long FLASH_PORT_WIDTH; |
||||
typedef volatile unsigned long FLASH_PORT_WIDTHV; |
||||
#define FLASH_ID_MASK 0xFFFFFFFF |
||||
#endif |
||||
|
||||
#define FPW FLASH_PORT_WIDTH |
||||
#define FPWV FLASH_PORT_WIDTHV |
||||
|
||||
#define ORMASK(size) ((-size) & OR_AM_MSK) |
||||
|
||||
#define FLASH_CYCLE1 0x0555 |
||||
#define FLASH_CYCLE2 0x02aa |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static ulong flash_get_size(FPWV *addr, flash_info_t *info); |
||||
static void flash_reset(flash_info_t *info); |
||||
static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); |
||||
static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); |
||||
static void flash_get_offsets(ulong base, flash_info_t *info); |
||||
static flash_info_t *flash_get_info(ulong base); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* flash_init() |
||||
* |
||||
* sets up flash_info and returns size of FLASH (bytes) |
||||
*/ |
||||
unsigned long flash_init (void) |
||||
{ |
||||
unsigned long size = 0; |
||||
int i; |
||||
|
||||
/* Init: no FLASHes known */ |
||||
for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { |
||||
#if 0 |
||||
ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; |
||||
#else |
||||
ulong flashbase = CFG_FLASH_BASE; |
||||
#endif |
||||
|
||||
memset(&flash_info[i], 0, sizeof(flash_info_t)); |
||||
|
||||
flash_info[i].size =
|
||||
flash_get_size((FPW *)flashbase, &flash_info[i]); |
||||
|
||||
if (flash_info[i].flash_id == FLASH_UNKNOWN) { |
||||
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", |
||||
i, flash_info[i].size); |
||||
} |
||||
|
||||
size += flash_info[i].size; |
||||
} |
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
||||
/* monitor protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, |
||||
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, |
||||
flash_get_info(CFG_MONITOR_BASE)); |
||||
#endif |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
/* ENV protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR+CFG_ENV_SIZE-1, |
||||
flash_get_info(CFG_ENV_ADDR)); |
||||
#endif |
||||
|
||||
|
||||
return size ? size : 1; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_reset(flash_info_t *info) |
||||
{ |
||||
FPWV *base = (FPWV *)(info->start[0]); |
||||
|
||||
/* Put FLASH back in read mode */ |
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) |
||||
*base = (FPW)0x00FF00FF; /* Intel Read Mode */ |
||||
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) |
||||
*base = (FPW)0x00F000F0; /* AMD Read Mode */ |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_get_offsets (ulong base, flash_info_t *info) |
||||
{ |
||||
int i; |
||||
|
||||
/* set up sector start address table */ |
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL |
||||
&& (info->flash_id & FLASH_BTYPE)) { |
||||
int bootsect_size; /* number of bytes/boot sector */ |
||||
int sect_size; /* number of bytes/regular sector */ |
||||
|
||||
bootsect_size = 0x00002000 * (sizeof(FPW)/2); |
||||
sect_size = 0x00010000 * (sizeof(FPW)/2); |
||||
|
||||
/* set sector offsets for bottom boot block type */ |
||||
for (i = 0; i < 8; ++i) { |
||||
info->start[i] = base + (i * bootsect_size); |
||||
} |
||||
for (i = 8; i < info->sector_count; i++) { |
||||
info->start[i] = base + ((i - 7) * sect_size); |
||||
} |
||||
} |
||||
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD |
||||
&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { |
||||
|
||||
int sect_size; /* number of bytes/sector */ |
||||
|
||||
sect_size = 0x00010000 * (sizeof(FPW)/2); |
||||
|
||||
/* set up sector start address table (uniform sector type) */ |
||||
for( i = 0; i < info->sector_count; i++ ) |
||||
info->start[i] = base + (i * sect_size); |
||||
} |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
static flash_info_t *flash_get_info(ulong base) |
||||
{ |
||||
int i; |
||||
flash_info_t * info; |
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { |
||||
info = & flash_info[i]; |
||||
if (info->start[0] <= base && base < info->start[0] + info->size) |
||||
break; |
||||
} |
||||
|
||||
return i == CFG_MAX_FLASH_BANKS ? 0 : info; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
void flash_print_info (flash_info_t *info) |
||||
{ |
||||
int i; |
||||
uchar *boottype; |
||||
uchar *bootletter; |
||||
uchar *fmt; |
||||
uchar botbootletter[] = "B"; |
||||
uchar topbootletter[] = "T"; |
||||
uchar botboottype[] = "bottom boot sector"; |
||||
uchar topboottype[] = "top boot sector"; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_AMD: printf ("AMD "); break; |
||||
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; |
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
||||
case FLASH_MAN_SST: printf ("SST "); break; |
||||
case FLASH_MAN_STM: printf ("STM "); break; |
||||
case FLASH_MAN_INTEL: printf ("INTEL "); break; |
||||
default: printf ("Unknown Vendor "); break; |
||||
} |
||||
|
||||
/* check for top or bottom boot, if it applies */ |
||||
if (info->flash_id & FLASH_BTYPE) { |
||||
boottype = botboottype; |
||||
bootletter = botbootletter; |
||||
} |
||||
else { |
||||
boottype = topboottype; |
||||
bootletter = topbootletter; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_AM640U: |
||||
fmt = "29LV641D (64 Mbit, uniform sectors)\n"; |
||||
break; |
||||
case FLASH_28F800C3B: |
||||
case FLASH_28F800C3T: |
||||
fmt = "28F800C3%s (8 Mbit, %s)\n"; |
||||
break; |
||||
case FLASH_INTEL800B: |
||||
case FLASH_INTEL800T: |
||||
fmt = "28F800B3%s (8 Mbit, %s)\n"; |
||||
break; |
||||
case FLASH_28F160C3B: |
||||
case FLASH_28F160C3T: |
||||
fmt = "28F160C3%s (16 Mbit, %s)\n"; |
||||
break; |
||||
case FLASH_INTEL160B: |
||||
case FLASH_INTEL160T: |
||||
fmt = "28F160B3%s (16 Mbit, %s)\n"; |
||||
break; |
||||
case FLASH_28F320C3B: |
||||
case FLASH_28F320C3T: |
||||
fmt = "28F320C3%s (32 Mbit, %s)\n"; |
||||
break; |
||||
case FLASH_INTEL320B: |
||||
case FLASH_INTEL320T: |
||||
fmt = "28F320B3%s (32 Mbit, %s)\n"; |
||||
break; |
||||
case FLASH_28F640C3B: |
||||
case FLASH_28F640C3T: |
||||
fmt = "28F640C3%s (64 Mbit, %s)\n"; |
||||
break; |
||||
case FLASH_INTEL640B: |
||||
case FLASH_INTEL640T: |
||||
fmt = "28F640B3%s (64 Mbit, %s)\n"; |
||||
break; |
||||
default: |
||||
fmt = "Unknown Chip Type\n"; |
||||
break; |
||||
} |
||||
|
||||
printf (fmt, bootletter, boottype); |
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size >> 20, |
||||
info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
|
||||
for (i=0; i<info->sector_count; ++i) { |
||||
if ((i % 5) == 0) { |
||||
printf ("\n "); |
||||
} |
||||
|
||||
printf (" %08lX%s", info->start[i], |
||||
info->protect[i] ? " (RO)" : " "); |
||||
} |
||||
|
||||
printf ("\n"); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
|
||||
ulong flash_get_size (FPWV *addr, flash_info_t *info) |
||||
{ |
||||
/* Write auto select command: read Manufacturer ID */ |
||||
|
||||
/* Write auto select command sequence and test FLASH answer */ |
||||
addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ |
||||
addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ |
||||
addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ |
||||
|
||||
/* The manufacturer codes are only 1 byte, so just use 1 byte.
|
||||
* This works for any bus width and any FLASH device width. |
||||
*/ |
||||
udelay(1000000);//psl
|
||||
//psl switch (addr[1] & 0xff) {
|
||||
switch (addr[0] & 0xff) {//psl
|
||||
|
||||
case (uchar)AMD_MANUFACT: |
||||
info->flash_id = FLASH_MAN_AMD; |
||||
break; |
||||
|
||||
case (uchar)INTEL_MANUFACT: |
||||
info->flash_id = FLASH_MAN_INTEL; |
||||
break; |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
break; |
||||
} |
||||
|
||||
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ |
||||
//psl if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) {
|
||||
if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { |
||||
|
||||
case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ |
||||
info->flash_id += FLASH_AM640U; |
||||
info->sector_count = 128; |
||||
info->size = 0x00800000 * (sizeof(FPW)/2); |
||||
break; /* => 8 or 16 MB */ |
||||
|
||||
case (FPW)INTEL_ID_28F800C3B: |
||||
info->flash_id += FLASH_28F800C3B; |
||||
info->sector_count = 23; |
||||
info->size = 0x00100000 * (sizeof(FPW)/2); |
||||
break; /* => 1 or 2 MB */ |
||||
|
||||
case (FPW)INTEL_ID_28F800B3B: |
||||
info->flash_id += FLASH_INTEL800B; |
||||
info->sector_count = 23; |
||||
info->size = 0x00100000 * (sizeof(FPW)/2); |
||||
break; /* => 1 or 2 MB */ |
||||
|
||||
case (FPW)INTEL_ID_28F160C3B: |
||||
info->flash_id += FLASH_28F160C3B; |
||||
info->sector_count = 39; |
||||
info->size = 0x00200000 * (sizeof(FPW)/2); |
||||
break; /* => 2 or 4 MB */ |
||||
|
||||
case (FPW)INTEL_ID_28F160B3B: |
||||
info->flash_id += FLASH_INTEL160B; |
||||
info->sector_count = 39; |
||||
info->size = 0x00200000 * (sizeof(FPW)/2); |
||||
break; /* => 2 or 4 MB */ |
||||
|
||||
case (FPW)INTEL_ID_28F320C3B: |
||||
info->flash_id += FLASH_28F320C3B; |
||||
info->sector_count = 71; |
||||
info->size = 0x00400000 * (sizeof(FPW)/2); |
||||
break; /* => 4 or 8 MB */ |
||||
|
||||
case (FPW)INTEL_ID_28F320B3B: |
||||
info->flash_id += FLASH_INTEL320B; |
||||
info->sector_count = 71; |
||||
info->size = 0x00400000 * (sizeof(FPW)/2); |
||||
break; /* => 4 or 8 MB */ |
||||
|
||||
case (FPW)INTEL_ID_28F640C3B: |
||||
info->flash_id += FLASH_28F640C3B; |
||||
info->sector_count = 135; |
||||
info->size = 0x00800000 * (sizeof(FPW)/2); |
||||
break; /* => 8 or 16 MB */ |
||||
|
||||
case (FPW)INTEL_ID_28F640B3B: |
||||
info->flash_id += FLASH_INTEL640B; |
||||
info->sector_count = 135; |
||||
info->size = 0x00800000 * (sizeof(FPW)/2); |
||||
break; /* => 8 or 16 MB */ |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
return (0); /* => no or unknown flash */ |
||||
} |
||||
|
||||
flash_get_offsets((ulong)addr, info); |
||||
|
||||
/* Put FLASH back in read mode */ |
||||
flash_reset(info); |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
||||
{ |
||||
FPWV *addr; |
||||
int flag, prot, sect; |
||||
int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; |
||||
ulong start, now, last; |
||||
int rcode = 0; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_INTEL800B: |
||||
case FLASH_INTEL160B: |
||||
case FLASH_INTEL320B: |
||||
case FLASH_INTEL640B: |
||||
case FLASH_28F800C3B: |
||||
case FLASH_28F160C3B: |
||||
case FLASH_28F320C3B: |
||||
case FLASH_28F640C3B: |
||||
case FLASH_AM640U: |
||||
break; |
||||
case FLASH_UNKNOWN: |
||||
default: |
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
||||
info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect=s_first; sect<=s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
last = get_timer(0); |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last && rcode == 0; sect++) { |
||||
|
||||
if (info->protect[sect] != 0) /* protected, skip it */ |
||||
continue; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr = (FPWV *)(info->start[sect]); |
||||
if (intel) { |
||||
*addr = (FPW)0x00500050; /* clear status register */ |
||||
*addr = (FPW)0x00200020; /* erase setup */ |
||||
*addr = (FPW)0x00D000D0; /* erase confirm */ |
||||
} |
||||
else { |
||||
/* must be AMD style if not Intel */ |
||||
FPWV *base; /* first address in bank */ |
||||
|
||||
base = (FPWV *)(info->start[0]); |
||||
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ |
||||
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ |
||||
base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ |
||||
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ |
||||
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ |
||||
*addr = (FPW)0x00300030; /* erase sector */ |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
start = get_timer(0); |
||||
|
||||
/* wait at least 50us for AMD, 80us for Intel.
|
||||
* Let's wait 1 ms. |
||||
*/ |
||||
udelay (1000); |
||||
|
||||
while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { |
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
|
||||
if (intel) { |
||||
/* suspend erase */ |
||||
*addr = (FPW)0x00B000B0; |
||||
} |
||||
|
||||
flash_reset(info); /* reset to read mode */ |
||||
rcode = 1; /* failed */ |
||||
break; |
||||
} |
||||
|
||||
/* show that we're waiting */ |
||||
if ((get_timer(last)) > CFG_HZ) {/* every second */ |
||||
putc ('.'); |
||||
last = get_timer(0); |
||||
} |
||||
} |
||||
|
||||
/* show that we're waiting */ |
||||
if ((get_timer(last)) > CFG_HZ) { /* every second */ |
||||
putc ('.'); |
||||
last = get_timer(0); |
||||
} |
||||
|
||||
flash_reset(info); /* reset to read mode */ |
||||
} |
||||
|
||||
printf (" done\n"); |
||||
return rcode; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ |
||||
int bytes; /* number of bytes to program in current word */ |
||||
int left; /* number of bytes left to program */ |
||||
int i, res; |
||||
|
||||
for (left = cnt, res = 0; |
||||
left > 0 && res == 0; |
||||
addr += sizeof(data), left -= sizeof(data) - bytes) { |
||||
|
||||
bytes = addr & (sizeof(data) - 1); |
||||
addr &= ~(sizeof(data) - 1); |
||||
|
||||
/* combine source and destination data so can program
|
||||
* an entire word of 16 or 32 bits |
||||
*/ |
||||
for (i = 0; i < sizeof(data); i++) { |
||||
data <<= 8; |
||||
if (i < bytes || i - bytes >= left ) |
||||
data += *((uchar *)addr + i); |
||||
else |
||||
data += *src++; |
||||
} |
||||
|
||||
/* write one word to the flash */ |
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_AMD: |
||||
res = write_word_amd(info, (FPWV *)addr, data); |
||||
break; |
||||
case FLASH_MAN_INTEL: |
||||
res = write_word_intel(info, (FPWV *)addr, data); |
||||
break; |
||||
default: |
||||
/* unknown flash type, error! */ |
||||
printf ("missing or unknown FLASH type\n"); |
||||
res = 1; /* not really a timeout, but gives error */ |
||||
break; |
||||
} |
||||
} |
||||
|
||||
return (res); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for AMD FLASH |
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank |
||||
* (not an individual chip) is. |
||||
* |
||||
* returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) |
||||
{ |
||||
ulong start; |
||||
int flag; |
||||
int res = 0; /* result, assume success */ |
||||
FPWV *base; /* first address in flash bank */ |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*dest & data) != data) { |
||||
return (2); |
||||
} |
||||
|
||||
|
||||
base = (FPWV *)(info->start[0]); |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ |
||||
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ |
||||
base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ |
||||
|
||||
*dest = data; /* start programming the data */ |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
start = get_timer (0); |
||||
|
||||
/* data polling for D7 */ |
||||
while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
*dest = (FPW)0x00F000F0; /* reset bank */ |
||||
res = 1; |
||||
} |
||||
} |
||||
|
||||
return (res); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for Intel FLASH |
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank |
||||
* (not an individual chip) is. |
||||
* |
||||
* returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) |
||||
{ |
||||
ulong start; |
||||
int flag; |
||||
int res = 0; /* result, assume success */ |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*dest & data) != data) { |
||||
return (2); |
||||
} |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
*dest = (FPW)0x00500050; /* clear status register */ |
||||
*dest = (FPW)0x00FF00FF; /* make sure in read mode */ |
||||
*dest = (FPW)0x00400040; /* program setup */ |
||||
|
||||
*dest = data; /* start programming the data */ |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
start = get_timer (0); |
||||
|
||||
while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
*dest = (FPW)0x00B000B0; /* Suspend program */ |
||||
res = 1; |
||||
} |
||||
} |
||||
|
||||
if (res == 0 && (*dest & (FPW)0x00100010)) |
||||
res = 1; /* write failed, time out error is close enough */ |
||||
|
||||
*dest = (FPW)0x00500050; /* clear status register */ |
||||
*dest = (FPW)0x00FF00FF; /* make sure in read mode */ |
||||
|
||||
return (res); |
||||
} |
@ -0,0 +1,118 @@ |
||||
/* |
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc8260/start.o (.text) |
||||
*(.text) |
||||
common/environment.o(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
|
@ -0,0 +1,132 @@ |
||||
/* |
||||
* Linker command file for the GEN860T board when the environment is |
||||
* stored in flash memory. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
SECTIONS |
||||
{ |
||||
/* |
||||
* Read-only sections, merged into text segment: |
||||
*/ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc8xx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* |
||||
* Read-write section, merged into data segment: |
||||
*/ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data: |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
|
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
|
||||
.ppcenv: |
||||
{ |
||||
. = env_offset; |
||||
common/environment.o |
||||
} |
||||
} |
@ -0,0 +1,435 @@ |
||||
/*
|
||||
* Copyright (c) 2001 Navin Boppuri / Prashant Patel |
||||
* <nboppuri@trinetcommunication.com>, |
||||
* <pmpatel@trinetcommunication.com> |
||||
* Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de> |
||||
* Copyright (c) 2001-2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* MPC8260 CPM SPI interface. |
||||
* |
||||
* Parts of this code are probably not portable and/or specific to |
||||
* the board which I used for the tests. Please send fixes/complaints |
||||
* to wd@denx.de |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/cpm_8260.h> |
||||
#include <linux/ctype.h> |
||||
#include <malloc.h> |
||||
#include <post.h> |
||||
#include <net.h> |
||||
|
||||
#if defined(CONFIG_SPI) |
||||
|
||||
/* Warning:
|
||||
* You cannot enable DEBUG for early system initalization, i. e. when |
||||
* this driver is used to read environment parameters like "baudrate" |
||||
* from EEPROM which are used to initialize the serial port which is |
||||
* needed to print the debug messages... |
||||
*/ |
||||
#undef DEBUG |
||||
|
||||
#define SPI_EEPROM_WREN 0x06 |
||||
#define SPI_EEPROM_RDSR 0x05 |
||||
#define SPI_EEPROM_READ 0x03 |
||||
#define SPI_EEPROM_WRITE 0x02 |
||||
|
||||
/* ---------------------------------------------------------------
|
||||
* Offset for initial SPI buffers in DPRAM: |
||||
* We need a 520 byte scratch DPRAM area to use at an early stage. |
||||
* It is used between the two initialization calls (spi_init_f() |
||||
* and spi_init_r()). |
||||
* The value 0x2000 makes it far enough from the start of the data |
||||
* area (as well as from the stack pointer). |
||||
* --------------------------------------------------------------- */ |
||||
#ifndef CFG_SPI_INIT_OFFSET |
||||
#define CFG_SPI_INIT_OFFSET 0x2000 |
||||
#endif |
||||
|
||||
#define CPM_SPI_BASE 0x100 |
||||
|
||||
#ifdef DEBUG |
||||
|
||||
#define DPRINT(a) printf a; |
||||
/* -----------------------------------------------
|
||||
* Helper functions to peek into tx and rx buffers |
||||
* ----------------------------------------------- */ |
||||
static const char * const hex_digit = "0123456789ABCDEF"; |
||||
|
||||
static char quickhex (int i) |
||||
{ |
||||
return hex_digit[i]; |
||||
} |
||||
|
||||
static void memdump (void *pv, int num) |
||||
{ |
||||
int i; |
||||
unsigned char *pc = (unsigned char *) pv; |
||||
|
||||
for (i = 0; i < num; i++) |
||||
printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); |
||||
printf ("\t"); |
||||
for (i = 0; i < num; i++) |
||||
printf ("%c", isprint (pc[i]) ? pc[i] : '.'); |
||||
printf ("\n"); |
||||
} |
||||
#else /* !DEBUG */ |
||||
|
||||
#define DPRINT(a) |
||||
|
||||
#endif /* DEBUG */ |
||||
|
||||
/* -------------------
|
||||
* Function prototypes |
||||
* ------------------- */ |
||||
void spi_init (void); |
||||
|
||||
ssize_t spi_read (uchar *, int, uchar *, int); |
||||
ssize_t spi_write (uchar *, int, uchar *, int); |
||||
ssize_t spi_xfer (size_t); |
||||
|
||||
/* -------------------
|
||||
* Variables |
||||
* ------------------- */ |
||||
|
||||
#define MAX_BUFFER 0x104 |
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Initially we place the RX and TX buffers at a fixed location in DPRAM! |
||||
* ---------------------------------------------------------------------- */ |
||||
static uchar *rxbuf = |
||||
(uchar *)&((immap_t *)CFG_IMMR)->im_dprambase |
||||
[CFG_SPI_INIT_OFFSET]; |
||||
static uchar *txbuf = |
||||
(uchar *)&((immap_t *)CFG_IMMR)->im_dprambase |
||||
[CFG_SPI_INIT_OFFSET+MAX_BUFFER]; |
||||
|
||||
/* **************************************************************************
|
||||
* |
||||
* Function: spi_init_f |
||||
* |
||||
* Description: Init SPI-Controller (ROM part) |
||||
* |
||||
* return: --- |
||||
* |
||||
* *********************************************************************** */ |
||||
void spi_init_f (void) |
||||
{ |
||||
unsigned int dpaddr; |
||||
|
||||
volatile spi_t *spi; |
||||
volatile immap_t *immr; |
||||
volatile cpm8260_t *cp; |
||||
volatile cbd_t *tbdf, *rbdf; |
||||
|
||||
immr = (immap_t *) CFG_IMMR; |
||||
cp = (cpm8260_t *) &immr->im_cpm; |
||||
|
||||
*(ushort *)(&immr->im_dprambase[PROFF_SPI_BASE]) = PROFF_SPI; |
||||
spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; |
||||
|
||||
/* 1 */ |
||||
/* ------------------------------------------------
|
||||
* Initialize Port D SPI pins |
||||
* (we are only in Master Mode !) |
||||
* ------------------------------------------------ */ |
||||
|
||||
/* --------------------------------------------
|
||||
* GPIO or per. Function |
||||
* PPARD[16] = 1 [0x00008000] (SPIMISO) |
||||
* PPARD[17] = 1 [0x00004000] (SPIMOSI) |
||||
* PPARD[18] = 1 [0x00002000] (SPICLK) |
||||
* PPARD[12] = 0 [0x00080000] -> GPIO: (CS for ATC EEPROM) |
||||
* -------------------------------------------- */ |
||||
immr->im_ioport.iop_ppard |= 0x0000E000; /* set bits */ |
||||
immr->im_ioport.iop_ppard &= ~0x00080000; /* reset bit */ |
||||
|
||||
/* ----------------------------------------------
|
||||
* In/Out or per. Function 0/1 |
||||
* PDIRD[16] = 0 [0x00008000] -> PERI1: SPIMISO |
||||
* PDIRD[17] = 0 [0x00004000] -> PERI1: SPIMOSI |
||||
* PDIRD[18] = 0 [0x00002000] -> PERI1: SPICLK |
||||
* PDIRD[12] = 1 [0x00080000] -> GPIO OUT: CS for ATC EEPROM |
||||
* ---------------------------------------------- */ |
||||
immr->im_ioport.iop_pdird &= ~0x0000E000; |
||||
immr->im_ioport.iop_pdird |= 0x00080000; |
||||
|
||||
/* ----------------------------------------------
|
||||
* special option reg. |
||||
* PSORD[16] = 1 [0x00008000] -> SPIMISO |
||||
* PSORD[17] = 1 [0x00004000] -> SPIMOSI |
||||
* PSORD[18] = 1 [0x00002000] -> SPICLK |
||||
* ---------------------------------------------- */ |
||||
immr->im_ioport.iop_psord |= 0x0000E000; |
||||
|
||||
/* Initialize the parameter ram.
|
||||
* We need to make sure many things are initialized to zero |
||||
*/ |
||||
spi->spi_rstate = 0; |
||||
spi->spi_rdp = 0; |
||||
spi->spi_rbptr = 0; |
||||
spi->spi_rbc = 0; |
||||
spi->spi_rxtmp = 0; |
||||
spi->spi_tstate = 0; |
||||
spi->spi_tdp = 0; |
||||
spi->spi_tbptr = 0; |
||||
spi->spi_tbc = 0; |
||||
spi->spi_txtmp = 0; |
||||
|
||||
/* Allocate space for one transmit and one receive buffer
|
||||
* descriptor in the DP ram |
||||
*/ |
||||
#ifdef CFG_ALLOC_DPRAM |
||||
dpaddr = m8260_cpm_dpalloc (sizeof(cbd_t)*2, 8); |
||||
#else |
||||
dpaddr = CPM_SPI_BASE; |
||||
#endif |
||||
|
||||
/* 3 */ |
||||
/* Set up the SPI parameters in the parameter ram */ |
||||
spi->spi_rbase = dpaddr; |
||||
spi->spi_tbase = dpaddr + sizeof (cbd_t); |
||||
|
||||
/***********IMPORTANT******************/ |
||||
|
||||
/*
|
||||
* Setting transmit and receive buffer descriptor pointers |
||||
* initially to rbase and tbase. Only the microcode patches |
||||
* documentation talks about initializing this pointer. This |
||||
* is missing from the sample I2C driver. If you dont |
||||
* initialize these pointers, the kernel hangs. |
||||
*/ |
||||
spi->spi_rbptr = spi->spi_rbase; |
||||
spi->spi_tbptr = spi->spi_tbase; |
||||
|
||||
/* 4 */ |
||||
/* Init SPI Tx + Rx Parameters */ |
||||
while (cp->cp_cpcr & CPM_CR_FLG) |
||||
; |
||||
cp->cp_cpcr = mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, |
||||
0, CPM_CR_INIT_TRX) | CPM_CR_FLG; |
||||
while (cp->cp_cpcr & CPM_CR_FLG) |
||||
; |
||||
|
||||
/* 6 */ |
||||
/* Set to big endian. */ |
||||
spi->spi_tfcr = CPMFCR_EB; |
||||
spi->spi_rfcr = CPMFCR_EB; |
||||
|
||||
/* 7 */ |
||||
/* Set maximum receive size. */ |
||||
spi->spi_mrblr = MAX_BUFFER; |
||||
|
||||
/* 8 + 9 */ |
||||
/* tx and rx buffer descriptors */ |
||||
tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; |
||||
rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; |
||||
|
||||
tbdf->cbd_sc &= ~BD_SC_READY; |
||||
rbdf->cbd_sc &= ~BD_SC_EMPTY; |
||||
|
||||
/* Set the bd's rx and tx buffer address pointers */ |
||||
rbdf->cbd_bufaddr = (ulong) rxbuf; |
||||
tbdf->cbd_bufaddr = (ulong) txbuf; |
||||
|
||||
/* 10 + 11 */ |
||||
immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ |
||||
immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ |
||||
|
||||
|
||||
return; |
||||
} |
||||
|
||||
/* **************************************************************************
|
||||
* |
||||
* Function: spi_init_r |
||||
* |
||||
* Description: Init SPI-Controller (RAM part) - |
||||
* The malloc engine is ready and we can move our buffers to |
||||
* normal RAM |
||||
* |
||||
* return: --- |
||||
* |
||||
* *********************************************************************** */ |
||||
void spi_init_r (void) |
||||
{ |
||||
volatile spi_t *spi; |
||||
volatile immap_t *immr; |
||||
volatile cpm8260_t *cp; |
||||
volatile cbd_t *tbdf, *rbdf; |
||||
|
||||
immr = (immap_t *) CFG_IMMR; |
||||
cp = (cpm8260_t *) &immr->im_cpm; |
||||
|
||||
spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; |
||||
|
||||
/* tx and rx buffer descriptors */ |
||||
tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; |
||||
rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; |
||||
|
||||
/* Allocate memory for RX and TX buffers */ |
||||
rxbuf = (uchar *) malloc (MAX_BUFFER); |
||||
txbuf = (uchar *) malloc (MAX_BUFFER); |
||||
|
||||
rbdf->cbd_bufaddr = (ulong) rxbuf; |
||||
tbdf->cbd_bufaddr = (ulong) txbuf; |
||||
|
||||
return; |
||||
} |
||||
|
||||
/****************************************************************************
|
||||
* Function: spi_write |
||||
**************************************************************************** */ |
||||
ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) |
||||
{ |
||||
int i; |
||||
|
||||
memset(rxbuf, 0, MAX_BUFFER); |
||||
memset(txbuf, 0, MAX_BUFFER); |
||||
*txbuf = SPI_EEPROM_WREN; /* write enable */ |
||||
spi_xfer(1); |
||||
memcpy(txbuf, addr, alen); |
||||
*txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ |
||||
memcpy(alen + txbuf, buffer, len); |
||||
spi_xfer(alen + len); |
||||
/* ignore received data */ |
||||
for (i = 0; i < 1000; i++) { |
||||
*txbuf = SPI_EEPROM_RDSR; /* read status */ |
||||
txbuf[1] = 0; |
||||
spi_xfer(2); |
||||
if (!(rxbuf[1] & 1)) { |
||||
break; |
||||
} |
||||
udelay(1000); |
||||
} |
||||
if (i >= 1000) { |
||||
printf ("*** spi_write: Time out while writing!\n"); |
||||
} |
||||
|
||||
return len; |
||||
} |
||||
|
||||
/****************************************************************************
|
||||
* Function: spi_read |
||||
**************************************************************************** */ |
||||
ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) |
||||
{ |
||||
memset(rxbuf, 0, MAX_BUFFER); |
||||
memset(txbuf, 0, MAX_BUFFER); |
||||
memcpy(txbuf, addr, alen); |
||||
*txbuf = SPI_EEPROM_READ; /* READ memory array */ |
||||
|
||||
/*
|
||||
* There is a bug in 860T (?) that cuts the last byte of input |
||||
* if we're reading into DPRAM. The solution we choose here is |
||||
* to always read len+1 bytes (we have one extra byte at the |
||||
* end of the buffer). |
||||
*/ |
||||
spi_xfer(alen + len + 1); |
||||
memcpy(buffer, alen + rxbuf, len); |
||||
|
||||
return len; |
||||
} |
||||
|
||||
/****************************************************************************
|
||||
* Function: spi_xfer |
||||
**************************************************************************** */ |
||||
ssize_t spi_xfer (size_t count) |
||||
{ |
||||
volatile immap_t *immr; |
||||
volatile cpm8260_t *cp; |
||||
volatile spi_t *spi; |
||||
cbd_t *tbdf, *rbdf; |
||||
int tm; |
||||
|
||||
DPRINT (("*** spi_xfer entered ***\n")); |
||||
|
||||
immr = (immap_t *) CFG_IMMR; |
||||
cp = (cpm8260_t *) &immr->im_cpm; |
||||
|
||||
spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; |
||||
|
||||
tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; |
||||
rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; |
||||
|
||||
/* Board-specific: Set CS for device (ATC EEPROM) */ |
||||
immr->im_ioport.iop_pdatd &= ~0x00080000; |
||||
|
||||
/* Setting tx bd status and data length */ |
||||
tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP; |
||||
tbdf->cbd_datlen = count; |
||||
|
||||
DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", |
||||
tbdf->cbd_datlen)); |
||||
|
||||
/* Setting rx bd status and data length */ |
||||
rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; |
||||
rbdf->cbd_datlen = 0; /* rx length has no significance */ |
||||
|
||||
immr->im_spi.spi_spmode = SPMODE_REV | |
||||
SPMODE_MSTR | |
||||
SPMODE_EN | |
||||
SPMODE_LEN(8) | /* 8 Bits per char */ |
||||
SPMODE_PM(0x8) ; /* medium speed */ |
||||
immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ |
||||
immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ |
||||
|
||||
/* start spi transfer */ |
||||
DPRINT (("*** spi_xfer: Performing transfer ...\n")); |
||||
immr->im_spi.spi_spcom |= SPI_STR; /* Start transmit */ |
||||
|
||||
/* --------------------------------
|
||||
* Wait for SPI transmit to get out |
||||
* or time out (1 second = 1000 ms) |
||||
* -------------------------------- */ |
||||
for (tm=0; tm<1000; ++tm) { |
||||
if (immr->im_spi.spi_spie & SPI_TXB) { /* Tx Buffer Empty */ |
||||
DPRINT (("*** spi_xfer: Tx buffer empty\n")); |
||||
break; |
||||
} |
||||
if ((tbdf->cbd_sc & BD_SC_READY) == 0) { |
||||
DPRINT (("*** spi_xfer: Tx BD done\n")); |
||||
break; |
||||
} |
||||
udelay (1000); |
||||
} |
||||
if (tm >= 1000) { |
||||
printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); |
||||
} |
||||
DPRINT (("*** spi_xfer: ... transfer ended\n")); |
||||
|
||||
#ifdef DEBUG |
||||
printf ("\nspi_xfer: txbuf after xfer\n"); |
||||
memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */ |
||||
printf ("spi_xfer: rxbuf after xfer\n"); |
||||
memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */ |
||||
printf ("\n"); |
||||
#endif |
||||
|
||||
/* Clear CS for device */ |
||||
immr->im_ioport.iop_pdatd |= 0x00080000; |
||||
|
||||
return count; |
||||
} |
||||
#endif /* CONFIG_SPI */ |
@ -0,0 +1,442 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
||||
#define CONFIG_ATC 1 /* ...on a ATC board */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
* |
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must |
||||
* defined elsewhere (for example, on the cogent platform, there are serial |
||||
* ports on the motherboard which are used for the serial console - see |
||||
* cogent/cma101/serial.[ch]). |
||||
*/ |
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */ |
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on something else*/ |
||||
#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
* |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_ON_FCC |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_ETHER_ON_FCC2 |
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK13 |
||||
* - Tx-CLK is CLK14 |
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
||||
* - Enable Full Duplex in FSMR |
||||
*/ |
||||
# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
||||
# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
||||
|
||||
#define CONFIG_ETHER_ON_FCC3 |
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK15 |
||||
* - Tx-CLK is CLK16 |
||||
* - RAM for BD/Buffers is on the local Bus (see 28-13) |
||||
* - Enable Half Duplex in FSMR |
||||
*/ |
||||
# define CFG_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) |
||||
# define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) |
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
||||
#define CONFIG_8260_CLKIN 64000000 /* in Hz */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */ |
||||
|
||||
#define CONFIG_PREBOOT \ |
||||
"echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp;" \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
|
||||
"bootm" |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configuration options |
||||
*/ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ |
||||
|
||||
#define CFG_ALLOC_DPRAM |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_SPI |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Flash configuration |
||||
*/ |
||||
|
||||
#define CFG_BOOTROM_BASE 0xFF800000 |
||||
#define CFG_BOOTROM_SIZE 0x00080000 |
||||
#define CFG_FLASH_BASE 0xFF000000 |
||||
#define CFG_FLASH_SIZE 0x00800000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
#define CONFIG_FLASH_16BIT |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words |
||||
* |
||||
* if you change bits in the HRCW, you must also change the CFG_* |
||||
* defines for the various registers affected by the HRCW e.g. changing |
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR. |
||||
*/ |
||||
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ |
||||
HRCW_BPS10 | HRCW_DPPC10 |\
|
||||
HRCW_APPC10) |
||||
|
||||
/* no slaves so just fill with zeros */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xF0000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
* |
||||
* 60x SDRAM is mapped at CFG_SDRAM_BASE. |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
# define CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#if 1 |
||||
/* environment is in Flash */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) |
||||
# define CFG_ENV_SIZE 0x10000 |
||||
# define CFG_ENV_SECT_SIZE 0x10000 |
||||
#else |
||||
#define CFG_ENV_IS_IN_EEPROM 1 |
||||
#define CFG_ENV_OFFSET 0 |
||||
#define CFG_ENV_SIZE 2048 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ |
||||
#endif |
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11 |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control - initially enable both caches and |
||||
* invalidate contents, then the final state leaves only the instruction |
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches, |
||||
* but Soft reset does not. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ |
||||
HID0_DCI|HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID2 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5 |
||||
*----------------------------------------------------------------------- |
||||
* turn on Checkstop Reset Enable |
||||
*/ |
||||
#define CFG_RMR RMR_CSRE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define BCR_APD01 0x10000000 |
||||
#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC10|SIUMCR_APPC10|\ |
||||
SIUMCR_CS10PC00|SIUMCR_BCTLC10) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40 |
||||
*----------------------------------------------------------------------- |
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
||||
* and enable Time Counter |
||||
*/ |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
||||
* Periodic timer |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8 |
||||
*----------------------------------------------------------------------- |
||||
* Ensure DFBRG is Divide by 16 |
||||
*/ |
||||
#define CFG_SCCR SCCR_DFBRG01 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0 |
||||
|
||||
#define CFG_MIN_AM_MASK 0xC0000000 |
||||
/*-----------------------------------------------------------------------
|
||||
* MPTPR - Memory Refresh Timer Prescaler Register 10-18 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_MPTPR 0x1F00 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PSRT - Refresh Timer Register 10-16 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_PSRT 0x0f |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PSRT - SDRAM Mode Register 10-10 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/ |
||||
#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A10 |\
|
||||
ORxS_NUMR_11) |
||||
|
||||
#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ |
||||
PSDMR_BSMA_A16_A18 |\
|
||||
PSDMR_SDA10_PBI0_A10 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_1W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_1C |\
|
||||
PSDMR_CL_2) |
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/ |
||||
#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A7 |\
|
||||
ORxS_NUMR_13) |
||||
|
||||
#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ |
||||
PSDMR_BSMA_A13_A15 |\
|
||||
PSDMR_SDA10_PBI0_A9 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_1W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_1C |\
|
||||
PSDMR_CL_2) |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* Bank Bus Machine PortSz Device |
||||
* ---- --- ------- ------ ------ |
||||
* 0 60x GPCM 8 bit Boot ROM |
||||
* 1 60x GPCM 64 bit FLASH |
||||
* 2 60x SDRAM 64 bit SDRAM |
||||
* |
||||
*/ |
||||
|
||||
#define CFG_MRS_OFFS 0x00000000 |
||||
|
||||
/* Bank 0 - FLASH
|
||||
*/ |
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_16 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxU_EHTR_8IDLE) |
||||
|
||||
|
||||
/* Bank 2 - 60x bus SDRAM
|
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR2_PRELIM CFG_OR2_8COL |
||||
|
||||
#define CFG_PSDMR CFG_PSDMR_8COL |
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
#endif /* __CONFIG_H */ |
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Reference in new issue