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ppc4xx: remove DU440 board

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Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
master
Matthias Fuchs 10 years ago committed by Tom Rini
parent bc114076dc
commit 7ac9d47a22
11 changed files with 1 additions and 1440 deletions
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  1. 4
      arch/powerpc/cpu/ppc4xx/Kconfig
  2. 12
      board/esd/du440/Kconfig
  3. 6
      board/esd/du440/MAINTAINERS
  4. 9
      board/esd/du440/Makefile
  5. 16
      board/esd/du440/config.mk
  6. 882
      board/esd/du440/du440.c
  7. 27
      board/esd/du440/du440.h
  8. 66
      board/esd/du440/init.S
  9. 3
      configs/DU440_defconfig
  10. 1
      doc/README.scrapyard
  11. 415
      include/configs/DU440.h

4
arch/powerpc/cpu/ppc4xx/Kconfig
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@ -125,9 +125,6 @@ config TARGET_CPCI405AB
config TARGET_CPCI405DT
bool "Support CPCI405DT"
config TARGET_DU440
bool "Support DU440"
config TARGET_HH405
bool "Support HH405"
@ -238,7 +235,6 @@ source "board/csb472/Kconfig"
source "board/dave/PPChameleonEVB/Kconfig"
source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig"
source "board/esd/du440/Kconfig"
source "board/esd/hh405/Kconfig"
source "board/esd/hub405/Kconfig"
source "board/esd/ocrtc/Kconfig"

12
board/esd/du440/Kconfig
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@ -1,12 +0,0 @@
if TARGET_DU440
config SYS_BOARD
default "du440"
config SYS_VENDOR
default "esd"
config SYS_CONFIG_NAME
default "DU440"
endif

6
board/esd/du440/MAINTAINERS
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@ -1,6 +0,0 @@
DU440 BOARD
M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
S: Maintained
F: board/esd/du440/
F: include/configs/DU440.h
F: configs/DU440_defconfig

9
board/esd/du440/Makefile
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@ -1,9 +0,0 @@
#
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = du440.o
extra-y += init.o

16
board/esd/du440/config.mk
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@ -1,16 +0,0 @@
#
# (C) Copyright 2002-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

882
board/esd/du440/du440.c
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@ -1,882 +0,0 @@
/*
* (C) Copyright 2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/bitops.h>
#include <command.h>
#include <i2c.h>
#include <asm/ppc440.h>
#include "du440.h"
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
extern ulong flash_get_size (ulong base, int banknum);
int usbhub_init(void);
int dvi_init(void);
int eeprom_write_enable (unsigned dev_addr, int state);
int board_revision(void);
static int du440_post_errors;
int board_early_init_f(void)
{
u32 sdr0_cust0;
u32 sdr0_pfc1, sdr0_pfc2;
u32 reg;
mtdcr(EBC0_CFGADDR, EBC0_CFG);
mtdcr(EBC0_CFGDATA, 0xb8400000);
/*
* Setup the GPIO pins
*/
out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
out_be32((void*)GPIO0_OSRL, 0x50055400);
out_be32((void*)GPIO0_OSRH, 0x55005000);
out_be32((void*)GPIO0_TSRL, 0x50055400);
out_be32((void*)GPIO0_TSRH, 0x55005000);
out_be32((void*)GPIO0_ISR1L, 0x50000000);
out_be32((void*)GPIO0_ISR1H, 0x00000000);
out_be32((void*)GPIO0_ISR2L, 0x00000000);
out_be32((void*)GPIO0_ISR2H, 0x00000000);
out_be32((void*)GPIO0_ISR3L, 0x00000000);
out_be32((void*)GPIO0_ISR3H, 0x00000000);
out_be32((void*)GPIO1_OR, 0x00000000);
out_be32((void*)GPIO1_TCR, 0xc2000000 |
CONFIG_SYS_GPIO1_IORSTN |
CONFIG_SYS_GPIO1_IORST2N |
CONFIG_SYS_GPIO1_LEDUSR1 |
CONFIG_SYS_GPIO1_LEDUSR2 |
CONFIG_SYS_GPIO1_LEDPOST |
CONFIG_SYS_GPIO1_LEDDU);
out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
out_be32((void*)GPIO1_OSRL, 0x0c280000);
out_be32((void*)GPIO1_OSRH, 0x00000000);
out_be32((void*)GPIO1_TSRL, 0xcc000000);
out_be32((void*)GPIO1_TSRH, 0x00000000);
out_be32((void*)GPIO1_ISR1L, 0x00005550);
out_be32((void*)GPIO1_ISR1H, 0x00000000);
out_be32((void*)GPIO1_ISR2L, 0x00050000);
out_be32((void*)GPIO1_ISR2H, 0x00000000);
out_be32((void*)GPIO1_ISR3L, 0x01400000);
out_be32((void*)GPIO1_ISR3H, 0x00000000);
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
/*
* UIC1:
* bit30: ext. Irq 1: PLD : int 32+30
*/
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xfffffffd);
mtdcr(UIC1TR, 0x00000000);
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*
* UIC2
* bit3: ext. Irq 2: DCF77 : int 64+3
*/
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_PFC2, sdr0_pfc2);
/* setup EMAC bridge interface */
if (board_revision() == 0) {
/* 1 x MII */
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
SDR0_PFC1_SELECT_CONFIG_1_2;
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
SDR0_PFC2_SELECT_CONFIG_1_2;
} else {
/* 2 x SMII */
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
SDR0_PFC1_SELECT_CONFIG_6;
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
SDR0_PFC2_SELECT_CONFIG_6;
}
/* enable 2nd IIC */
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
mtsdr(SDR0_PFC2, sdr0_pfc2);
mtsdr(SDR0_PFC1, sdr0_pfc1);
/* PCI arbiter enabled */
mfsdr(SDR0_PCI0, reg);
mtsdr(SDR0_PCI0, 0x80000000 | reg);
/* setup NAND FLASH */
mfsdr(SDR0_CUST0, sdr0_cust0);
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
(0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
(0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
return 0;
}
int misc_init_r(void)
{
uint pbcr;
int size_val = 0;
u32 reg;
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1;
unsigned long sdr0_srst0, sdr0_srst1;
int i, j;
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(EBC0_CFGADDR, PB0CR);
mtdcr(EBC0_CFGDATA, pbcr);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, 0);
/*
* USB suff...
*/
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
/* An 8-bit/60MHz interface is the only possible alternative
when connecting the Device to the PHY */
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
/* To enable the USB 2.0 Device function through the UTMI interface */
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
/*
* Take USB out of reset:
* -Initial status = all cores are in reset
* -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
* -wait 1 ms
* -deassert reset to PHY
* -wait 1 ms
* -deassert reset to HOST
* -wait 4 ms
* -deassert all other resets
*/
mfsdr(SDR0_SRST1, sdr0_srst1);
sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
SDR0_SRST1_P4OPB0 | \
SDR0_SRST1_OPBA2 | \
SDR0_SRST1_PLB42OPB1 | \
SDR0_SRST1_OPB2PLB40);
mtsdr(SDR0_SRST1, sdr0_srst1);
udelay(1000);
mfsdr(SDR0_SRST1, sdr0_srst1);
sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
mtsdr(SDR0_SRST1, sdr0_srst1);
udelay(1000);
mfsdr(SDR0_SRST0, sdr0_srst0);
sdr0_srst0 &= ~SDR0_SRST0_USB2H;
mtsdr(SDR0_SRST0, sdr0_srst0);
udelay(4000);
/* finally all the other resets */
mtsdr(SDR0_SRST1, 0x00000000);
mtsdr(SDR0_SRST0, 0x00000000);
printf("USB: Host(int phy)\n");
/*
* Clear PLB4A0_ACR[WRP]
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
mtdcr(PLB4A0_ACR, reg);
/*
* release IO-RST#
* We have to wait at least 560ms until we may call usbhub_init
*/
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
/*
* flash USR1/2 LEDs (600ms)
* This results in the necessary delay from IORST# until
* calling usbhub_init will succeed
*/
for (j = 0; j < 3; j++) {
out_be32((void*)GPIO1_OR,
(in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
CONFIG_SYS_GPIO1_LEDUSR1);
for (i = 0; i < 100; i++)
udelay(1000);
out_be32((void*)GPIO1_OR,
(in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
CONFIG_SYS_GPIO1_LEDUSR2);
for (i = 0; i < 100; i++)
udelay(1000);
}
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
if (usbhub_init())
du440_post_errors++;
if (dvi_init())
du440_post_errors++;
return 0;
}
int pld_revision(void)
{
out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
}
int board_revision(void)
{
int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
>> CONFIG_SYS_GPIO1_HWVER_SHIFT);
return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
((rpins & 4) >> 1) | ((rpins & 8) >> 3);
}
#if defined(CONFIG_SHOW_ACTIVITY)
void board_show_activity (ulong timestamp)
{
if ((timestamp % 100) == 0)
out_be32((void*)GPIO1_OR,
in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
}
void show_activity(int arg)
{
}
#endif /* CONFIG_SHOW_ACTIVITY */
int du440_phy_addr(int devnum)
{
if (board_revision() == 0)
return devnum;
return devnum + 1;
}
int checkboard(void)
{
char serno[32];
puts("Board: DU440");
if (getenv_f("serial#", serno, sizeof(serno)) > 0) {
puts(", serial# ");
puts(serno);
}
printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
board_revision(), pld_revision());
return (0);
}
int last_stage_init(void)
{
int e, i;
/* everyting is ok: turn on POST-LED */
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
/* slowly blink on errors and finally keep LED off */
for (e = 0; e < du440_post_errors; e++) {
out_be32((void*)GPIO1_OR,
in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
for (i = 0; i < 500; i++)
udelay(1000);
out_be32((void*)GPIO1_OR,
in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
for (i = 0; i < 500; i++)
udelay(1000);
}
return 0;
}
/*
* read field strength from I2C ADC
*/
int dcf77_status(void)
{
unsigned int oldbus;
uchar u[2];
int mv;
oldbus = I2C_GET_BUS();
I2C_SET_BUS(1);
if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
I2C_SET_BUS(oldbus);
return -1;
}
mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
I2C_SET_BUS(oldbus);
return mv;
}
int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int mv;
u32 pin, pinold;
unsigned long long t1, t2;
bd_t *bd = gd->bd;
printf("DCF77: ");
mv = dcf77_status();
if (mv > 0)
printf("signal=%d mV\n", mv);
else
printf("ERROR - no signal\n");
t1 = t2 = 0;
pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
while (!ctrlc()) {
pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
if (pin && !pinold) { /* bit start */
t1 = get_ticks();
if (t2 && ((unsigned int)(t1 - t2) /
(bd->bi_procfreq / 1000) >= 1800))
printf("Start of minute\n");
t2 = t1;
}
if (t1 && !pin && pinold) { /* bit end */
printf("%5d\n", (unsigned int)(get_ticks() - t1) /
(bd->bi_procfreq / 1000));
}
pinold = pin;
}
printf("Abort\n");
return 0;
}
U_BOOT_CMD(
dcf77, 1, 1, do_dcf77,
"Check DCF77 receiver",
""
);
/*
* initialize USB hub via I2C1
*/
int usbhub_init(void)
{
int reg;
int ret = 0;
unsigned int oldbus;
uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
0x32};
uchar stcd;
printf("Hub: ");
oldbus = I2C_GET_BUS();
I2C_SET_BUS(1);
for (reg = 0; reg < sizeof(u); reg++)
if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
ret = -1;
break;
}
if (ret == 0) {
stcd = 0x03;
if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
ret = -1;
}
if (ret == 0)
printf("initialized\n");
else
printf("failed - cannot initialize USB hub\n");
I2C_SET_BUS(oldbus);
return ret;
}
int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
usbhub_init();
return 0;
}
U_BOOT_CMD(
hubinit, 1, 1, do_hubinit,
"Initialize USB hub",
""
);
#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
int boot_eeprom_write (unsigned dev_addr,
unsigned offset,
uchar *buffer,
unsigned cnt)
{
unsigned end = offset + cnt;
unsigned blk_off;
int rcode = 0;
#if defined(CONFIG_SYS_EEPROM_WREN)
eeprom_write_enable(dev_addr, 1);
#endif
/*
* Write data until done or would cross a write page boundary.
* We must write the address again when changing pages
* because the address counter only increments within a page.
*/
while (offset < end) {
unsigned alen, len;
unsigned maxlen;
uchar addr[2];
blk_off = offset & 0xFF; /* block offset */
addr[0] = offset >> 8; /* block number */
addr[1] = blk_off; /* block offset */
alen = 2;
addr[0] |= dev_addr; /* insert device address */
len = end - offset;
/*
* For a FRAM device there is no limit on the number of the
* bytes that can be ccessed with the single read or write
* operation.
*/
#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
maxlen = BOOT_EEPROM_PAGE_SIZE -
BOOT_EEPROM_PAGE_OFFSET(blk_off);
#else
maxlen = 0x100 - blk_off;
#endif
if (maxlen > I2C_RXTX_LEN)
maxlen = I2C_RXTX_LEN;
if (len > maxlen)
len = maxlen;
if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
rcode = 1;
buffer += len;
offset += len;
#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
}
#if defined(CONFIG_SYS_EEPROM_WREN)
eeprom_write_enable(dev_addr, 0);
#endif
return rcode;
}
int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong sdsdp[4];
if (argc > 1) {
if (!strcmp(argv[1], "533")) {
printf("Bootstrapping for 533MHz\n");
sdsdp[0] = 0x87788252;
/* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
sdsdp[1] = 0x095fa030;
sdsdp[2] = 0x40082350;
sdsdp[3] = 0x0d050000;
} else if (!strcmp(argv[1], "533-66")) {
printf("Bootstrapping for 533MHz (66MHz PCI)\n");
sdsdp[0] = 0x87788252;
/* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
sdsdp[1] = 0x0957a030;
sdsdp[2] = 0x40082350;
sdsdp[3] = 0x0d050000;
} else if (!strcmp(argv[1], "667")) {
printf("Bootstrapping for 667MHz\n");
sdsdp[0] = 0x8778a256;
/* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
sdsdp[1] = 0x0947a030;
/* PLB-PCI-divider = 3 : sync PCI clock=44MHz
* -> not working when overclocking 533MHz chips
* -> untested on 667MHz chips */
/* sdsdp[1]=0x095fa030; */
sdsdp[2] = 0x40082350;
sdsdp[3] = 0x0d050000;
} else if (!strcmp(argv[1], "667-166")) {
printf("Bootstrapping for 667-166MHz\n");
sdsdp[0] = 0x8778a252;
sdsdp[1] = 0x09d7a030;
sdsdp[2] = 0x40082350;
sdsdp[3] = 0x0d050000;
}
} else {
printf("Bootstrapping for 533MHz (default)\n");
sdsdp[0] = 0x87788252;
/* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
sdsdp[1] = 0x095fa030;
sdsdp[2] = 0x40082350;
sdsdp[3] = 0x0d050000;
}
printf("Writing boot EEPROM ...\n");
if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
0, (uchar*)sdsdp, 16) != 0)
printf("boot_eeprom_write failed\n");
else
printf("done (dump via 'i2c md 52 0.1 10')\n");
return 0;
}
U_BOOT_CMD(
sbe, 2, 0, do_setup_boot_eeprom,
"setup boot eeprom",
""
);
#if defined(CONFIG_SYS_EEPROM_WREN)
/*
* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
* 0: disable write
* 1: enable write
* Returns: -1: wrong device address
* 0: dis-/en- able done
* 0/1: current state if <state> was -1.
*/
int eeprom_write_enable (unsigned dev_addr, int state)
{
if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
return -1;
else {
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
state = 0;
break;
default:
/* Read current status back. */
state = (0 == (in_be32((void*)GPIO0_OR) &
CONFIG_SYS_GPIO0_EP_EEP));
break;
}
}
return state;
}
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int query = argc == 1;
int state = 0;
if (query) {
/* Query write access state. */
state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0)
puts ("Query of write access state failed.\n");
else {
printf ("Write access for device 0x%0x is %sabled.\n",
CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
} else {
/* Enable write access. */
state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
}
if (state < 0)
puts ("Setup of write access state failed.\n");
}
return state;
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
"Enable / disable / query EEPROM write access",
""
);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
static int got_pldirq;
static int pld_interrupt(u32 arg)
{
int rc = -1; /* not for us */
u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
/* check for PLD interrupt */
if (status & PWR_INT_FLAG) {
/* reset this int */
out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
rc = 0;
got_pldirq = 1; /* trigger backend */
}
return rc;
}
int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
got_pldirq = 0;
/* clear any pending interrupt */
out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
irq_install_handler(CPLD_IRQ,
(interrupt_handler_t *)pld_interrupt, 0);
printf("Waiting ...\n");
while(!got_pldirq) {
/* Abort if ctrl-c was pressed */
if (ctrlc()) {
puts("\nAbort\n");
break;
}
}
if (got_pldirq) {
printf("Got interrupt!\n");
printf("Power %sready!\n",
in_8((void *)CONFIG_SYS_CPLD_BASE) &
PWR_RDY ? "":"NOT ");
}
irq_free_handler(CPLD_IRQ);
return 0;
}
U_BOOT_CMD(
wpi, 1, 1, do_waitpwrirq,
"Wait for power change interrupt",
""
);
/*
* initialize DVI panellink transmitter
*/
int dvi_init(void)
{
int i;
int ret = 0;
unsigned int oldbus;
uchar u[] = {0x08, 0x34,
0x09, 0x20,
0x0a, 0x90,
0x0c, 0x89,
0x08, 0x35};
printf("DVI: ");
oldbus = I2C_GET_BUS();
I2C_SET_BUS(0);
for (i = 0; i < sizeof(u); i += 2)
if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
ret = -1;
break;
}
if (ret == 0)
printf("initialized\n");
else
printf("failed - cannot initialize DVI transmitter\n");
I2C_SET_BUS(oldbus);
return ret;
}
int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
dvi_init();
return 0;
}
U_BOOT_CMD(
dviinit, 1, 1, do_dviinit,
"Initialize DVI Panellink transmitter",
""
);
/*
* TODO: 'time' command might be useful for others as well.
* Move to 'common' directory.
*/
int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long long start, end;
char c, cmd[CONFIG_SYS_CBSIZE];
char *p, *d = cmd;
int ret, i;
ulong us;
for (i = 1; i < argc; i++) {
p = argv[i];
if (i > 1)
*d++ = ' ';
while ((c = *p++) != '\0') {
*d++ = c;
}
}
*d = '\0';
start = get_ticks();
ret = run_command(cmd, 0);
end = get_ticks();
printf("ticks=%ld\n", (ulong)(end - start));
us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
printf("usec=%ld\n", us);
return ret;
}
U_BOOT_CMD(
time, CONFIG_SYS_MAXARGS, 1, do_time,
"run command and output execution time",
""
);
extern void video_hw_rectfill (
unsigned int bpp, /* bytes per pixel */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y, /* frame height */
unsigned int color /* fill color */
);
/*
* graphics demo
* draw rectangles using pseudorandom number generator
* (see http://www.embedded.com/columns/technicalinsights/20900500)
*/
unsigned int rprime = 9972;
static unsigned int r;
static unsigned int Y;
unsigned int prng(unsigned int max)
{
if (r == 0 || r == 1 || r == -1)
r = rprime; /* keep from getting stuck */
r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
Y = (r >> 16) % max; /* choose upper bits and reduce */
return Y;
}
int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned int color;
unsigned int x, y, dx, dy;
while (!ctrlc()) {
x = prng(1280 - 1);
y = prng(1024 - 1);
dx = prng(1280- x - 1);
dy = prng(1024 - y - 1);
color = prng(0x10000);
video_hw_rectfill(2, x, y, dx, dy, color);
}
return 0;
}
U_BOOT_CMD(
gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,
"demo",
""
);

27
board/esd/du440/du440.h
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/*
* (C) Copyright 2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define SDR0_USB0 0x0320 /* USB Control Register */
#define CONFIG_SYS_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
#define CONFIG_SYS_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
#define CONFIG_SYS_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
#define CONFIG_SYS_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */
#define CONFIG_SYS_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
#define CONFIG_SYS_GPIO1_HWVER_SHIFT 4
#define CONFIG_SYS_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
#define CONFIG_SYS_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
#define CONFIG_SYS_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
#define CONFIG_SYS_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
#define CPLD_VERSION_MASK 0x0f
#define PWR_INT_FLAG 0x80
#define PWR_RDY 0x10
#define CPLD_IRQ (32+30)

66
board/esd/du440/init.S
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/*
* (C) Copyright 2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
/*
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
#endif
/* TLB-entry for PCI Memory */
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
/* TLB-entry for PCI IO */
tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG )
/* TLB-entries for EBC: CPLD, DUMEM, DUIO */
tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG )
tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG )
tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG )
/* TLB-entry for NAND */
tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG )
tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG )
/* TLB-entry for Internal Registers & OCM */
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
/* TLB-entry PCI registers */
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
/* TLB-entry for peripherals */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
tlbtab_end

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configs/DU440_defconfig
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CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_DU440=y

1
doc/README.scrapyard
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
DU440 ppc4xx 440epx - - Matthias Fuchs <matthias.fuchs@esd.eu>
DU405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
DP405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
CPCIISER4 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs@esd.eu>

415
include/configs/DU440.h
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/*
* (C) Copyright 2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
*
* based on the Sequoia board configuration by
* Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
**********************************************************************
* DU440.h - configuration for esd's DU440 board (Power PC440EPx)
**********************************************************************
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_DU440 1 /* Board is esd DU440 */
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
#endif
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */
#define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */
#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
#define CONFIG_SYS_PCI_IOBASE 0xe8000000
#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
/*
* Initial RAM & stack pointer
*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
#define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*
* Video Port
*/
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SMI_LYNXEM
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
/*
* Environment
*/
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
/*
* FLASH related
*/
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET 0 /* environment starts at */
/* the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
#endif
/*
* DDR SDRAM
*/
#define CONFIG_SYS_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#define CONFIG_DDR_ECC /* Use ECC when available */
#define SPD_EEPROM_ADDRESS {0x50}
#define CONFIG_PROG_SDRAM_TLB
/*
* I2C
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_PPC4XX_CH1
#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
#define CONFIG_SYS_SPD_BUS_NUM 0
#define IIC1_MCP3021_ADDR 0x4d
#define IIC1_USB2507_ADDR 0x2c
#define CONFIG_SYS_I2C_NOPROBES { {1, IIC1_USB2507_ADDR} }
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
#define CONFIG_SYS_EEPROM_WREN 1
#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
/*
* standard dtt sensor configuration - bottom bit will determine local or
* remote sensor of the TMP401
*/
#define CONFIG_DTT_SENSORS { 0, 1 }
/*
* The PMC440 uses a TI TMP401 temperature sensor. This part
* is basically compatible to the ADM1021 that is supported
* by U-Boot.
*
* - i2c addr 0x4c
* - conversion rate 0x02 = 0.25 conversions/second
* - ALERT ouput disabled
* - local temp sensor enabled, min set to 0 deg, max set to 70 deg
* - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
*/
#define CONFIG_DTT_ADM1021
#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
/*
* RTC stuff
*/
#define CONFIG_RTC_DS1338
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"ethrotate=no\0" \
"hostname=du440\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_self=run ramargs addip addtty optargs;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
"bootm\0" \
"rootpath=/tftpboot/du440/target_root_du440\0" \
"img=/tftpboot/du440/uImage\0" \
"kernel_addr=FFC00000\0" \
"ramdisk_addr=FFE00000\0" \
"initrd_high=30000000\0" \
"load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 100000 FFFA0000 60000\0" \
""
#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#ifndef __ASSEMBLY__
int du440_phy_addr(int devnum);
#endif
#define CONFIG_PPC4xx_EMAC
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#undef CONFIG_PHY_GIGE /* no GbE detection */
#define CONFIG_HAS_ETH0
#define CONFIG_SYS_RX_ETH_BUFFER 128
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR du440_phy_addr(1)
/*
* USB
*/
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "du440"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BMP
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_USB
#define CONFIG_SUPPORT_VFAT
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT \
"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
/*
* PCI stuff
*/
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* External Bus Controller (EBC) Setup
*/
#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CPLD_BASE 0xC0000000
#define CONFIG_SYS_CPLD_RANGE 0x00000010
#define CONFIG_SYS_DUMEM_BASE 0xC0100000
#define CONFIG_SYS_DUMEM_RANGE 0x00100000
#define CONFIG_SYS_DUIO_BASE 0xC0200000
#define CONFIG_SYS_DUIO_RANGE 0x00010000
#define CONFIG_SYS_NAND0_CS 2 /* NAND chip connected to CSx */
#define CONFIG_SYS_NAND1_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x04017200
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
#define CONFIG_SYS_EBC_PB1AP 0x018003c0
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
/* Memory Bank 2 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x018003c0
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND0_ADDR | 0x1c000)
/* Memory Bank 3 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x018003c0
#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND1_ADDR | 0x1c000)
/* Memory Bank 4 (DUMEM, 1MB) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x018053c0
#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_DUMEM_BASE | 0x18000)
/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
#define CONFIG_SYS_EBC_PB5AP 0x018053c0
#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_DUIO_BASE | 0x18000)
/*
* NAND FLASH
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 2
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
#define CONFIG_SOURCE 1
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#endif /* __CONFIG_H */
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