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@ -14,25 +14,16 @@ |
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/*
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* High Level Configuration Options |
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*/ |
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#define CONFIG_OMAP /* in a TI OMAP core */ |
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#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ |
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#define CONFIG_OMAP_GPIO |
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#define CONFIG_OMAP_COMMON |
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/* Common ARM Erratas */ |
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#define CONFIG_ARM_ERRATA_454179 |
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#define CONFIG_ARM_ERRATA_430973 |
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#define CONFIG_ARM_ERRATA_621766 |
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ |
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#define CONFIG_SYS_TEXT_BASE 0x80400000 |
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#define CONFIG_SDRC /* The chip has SDRC controller */ |
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#include <asm/arch/cpu.h> /* get chip and board defs */ |
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#include <asm/arch/omap.h> |
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#include <configs/ti_omap3_common.h> |
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#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ |
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/*
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* Display CPU and Board information |
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*/ |
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#define CONFIG_DISPLAY_CPUINFO |
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#define CONFIG_DISPLAY_BOARDINFO |
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@ -55,25 +46,14 @@ |
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*/ |
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
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/* Sector */ |
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
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/*
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* Hardware drivers |
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*/ |
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/*
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* NS16550 Configuration |
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*/ |
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#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ |
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#define CONFIG_SYS_NS16550 |
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#define CONFIG_SYS_NS16550_SERIAL |
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#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
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/*
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* select serial console configuration |
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*/ |
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#undef CONFIG_CONS_INDEX |
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#define CONFIG_CONS_INDEX 1 |
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#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 |
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#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */ |
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@ -92,7 +72,6 @@ |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_CMD_EXT2 /* EXT2 Support */ |
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#define CONFIG_CMD_FAT /* FAT support */ |
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#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ |
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#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
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#define MTDIDS_DEFAULT "nand0=omap2-nand.0" |
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@ -120,32 +99,24 @@ |
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/*
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* TWL4030 |
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*/ |
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#define CONFIG_TWL4030_POWER |
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/*
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* Board NAND Info. |
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*/ |
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#define CONFIG_SYS_NAND_BASE NAND_BASE |
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#define CONFIG_SYS_NAND_QUIET_TEST |
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#define CONFIG_NAND_OMAP_GPMC |
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ |
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/* to access nand */ |
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ |
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/* to access nand at */ |
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/* CS0 */ |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ |
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/* NAND devices */ |
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#define CONFIG_SYS_NAND_BUSWIDTH_16BIT |
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#define CONFIG_JFFS2_NAND |
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/* nand device jffs2 lives on */ |
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#define CONFIG_JFFS2_DEV "nand0" |
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/* start of jffs2 partition */ |
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#define CONFIG_JFFS2_PART_OFFSET 0x680000 |
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#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ |
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/* partition */ |
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/* Environment information */ |
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#define CONFIG_BOOTDELAY 2 |
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/*
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* PREBOOT assumes the 4.3" display is attached. User can interrupt |
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@ -239,17 +210,13 @@ |
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/* Print Buffer Size */ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
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sizeof(CONFIG_SYS_PROMPT) + 16) |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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/* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
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/* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) |
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ |
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0x01F00000) /* 31MB */ |
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ |
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/* address */ |
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock |
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). |
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@ -292,12 +259,8 @@ |
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
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#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET |
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800 |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE) |
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/*
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* SMSC922x Ethernet |
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