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clk: renesas: Make PLL configurations per-SoC

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Not all SoCs have the same PLL configuration options,
so make those PLL configuraion tables per-SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
master
Marek Vasut 7 years ago committed by Marek Vasut
parent f11c9679ab
commit 7c88556323
6 changed files with 178 additions and 51 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 53
      drivers/clk/renesas/clk-rcar-gen3.c
  2. 56
      drivers/clk/renesas/r8a7795-cpg-mssr.c
  3. 56
      drivers/clk/renesas/r8a7796-cpg-mssr.c
  4. 39
      drivers/clk/renesas/r8a77970-cpg-mssr.c
  5. 24
      drivers/clk/renesas/r8a77995-cpg-mssr.c
  6. 1
      drivers/clk/renesas/renesas-cpg-mssr.h

53
drivers/clk/renesas/clk-rcar-gen3.c
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@ -75,56 +75,6 @@ static const u16 smstpcr[] = {
#define SRSTCLR(i) (0x940 + (i) * 4)
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
* 14 13 19 17 (MHz)
*-------------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
* 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
* 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
* 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
* 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
/* EXTAL div PLL1 mult PLL3 mult */
{ 1, 192, 192, },
{ 1, 192, 128, },
{ 0, /* Prohibited setting */ },
{ 1, 192, 192, },
{ 1, 160, 160, },
{ 1, 160, 106, },
{ 0, /* Prohibited setting */ },
{ 1, 160, 160, },
{ 1, 128, 128, },
{ 1, 128, 84, },
{ 0, /* Prohibited setting */ },
{ 1, 128, 128, },
{ 2, 192, 192, },
{ 2, 192, 128, },
{ 0, /* Prohibited setting */ },
{ 2, 192, 192, },
};
/*
* SDn Clock
*/
#define CPG_SD_STP_HCK BIT(9)
@ -520,7 +470,8 @@ int gen3_clk_probe(struct udevice *dev)
cpg_mode = readl(rst_base + CPG_RST_MODEMR);
priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
priv->cpg_pll_config =
(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
if (!priv->cpg_pll_config->extal_div)
return -EINVAL;

56
drivers/clk/renesas/r8a7795-cpg-mssr.c
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@ -264,6 +264,56 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
* 14 13 19 17 (MHz)
*-------------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
* 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
* 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
* 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
* 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 192, 1, 192, 1, },
{ 1, 192, 1, 128, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, },
{ 1, 160, 1, 160, 1, },
{ 1, 160, 1, 106, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, },
{ 1, 128, 1, 128, 1, },
{ 1, 128, 1, 84, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, },
{ 2, 192, 1, 192, 1, },
{ 2, 192, 1, 128, 1, },
{ 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, },
};
static const struct mstp_stop_table r8a7795_mstp_table[] = {
{ 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 },
{ 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 },
@ -273,6 +323,11 @@ static const struct mstp_stop_table r8a7795_mstp_table[] = {
{ 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 },
};
static const void *r8a7795_get_pll_config(const u32 cpg_mode)
{
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
}
static const struct cpg_mssr_info r8a7795_cpg_mssr_info = {
.core_clk = r8a7795_core_clks,
.core_clk_size = ARRAY_SIZE(r8a7795_core_clks),
@ -285,6 +340,7 @@ static const struct cpg_mssr_info r8a7795_cpg_mssr_info = {
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = CLK_EXTALR,
.get_pll_config = r8a7795_get_pll_config,
};
static const struct udevice_id r8a7795_clk_ids[] = {

56
drivers/clk/renesas/r8a7796-cpg-mssr.c
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@ -237,6 +237,56 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
* 14 13 19 17 (MHz)
*-------------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
* 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
* 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
* 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
* 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 192, 1, 192, 1, },
{ 1, 192, 1, 128, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, },
{ 1, 160, 1, 160, 1, },
{ 1, 160, 1, 106, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, },
{ 1, 128, 1, 128, 1, },
{ 1, 128, 1, 84, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, },
{ 2, 192, 1, 192, 1, },
{ 2, 192, 1, 128, 1, },
{ 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, },
};
static const struct mstp_stop_table r8a7796_mstp_table[] = {
{ 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
{ 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
@ -246,6 +296,11 @@ static const struct mstp_stop_table r8a7796_mstp_table[] = {
{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
};
static const void *r8a7796_get_pll_config(const u32 cpg_mode)
{
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
}
static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
.core_clk = r8a7796_core_clks,
.core_clk_size = ARRAY_SIZE(r8a7796_core_clks),
@ -258,6 +313,7 @@ static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = CLK_EXTALR,
.get_pll_config = r8a7796_get_pll_config,
};
static const struct udevice_id r8a7796_clk_ids[] = {

39
drivers/clk/renesas/r8a77970-cpg-mssr.c
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@ -145,6 +145,39 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = {
DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz)
*-------------------------------------------------
* 0 0 0 16.66 x 1 x192 x192 x96
* 0 0 1 16.66 x 1 x192 x192 x80
* 0 1 0 20 x 1 x160 x160 x80
* 0 1 1 20 x 1 x160 x160 x66
* 1 0 0 27 / 2 x236 x236 x118
* 1 0 1 27 / 2 x236 x236 x98
* 1 1 0 33.33 / 2 x192 x192 x96
* 1 1 1 33.33 / 2 x192 x192 x80
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 192, 1, 96, 1, },
{ 1, 192, 1, 80, 1, },
{ 1, 160, 1, 80, 1, },
{ 1, 160, 1, 66, 1, },
{ 2, 236, 1, 118, 1, },
{ 2, 236, 1, 98, 1, },
{ 2, 192, 1, 96, 1, },
{ 2, 192, 1, 80, 1, },
};
static const struct mstp_stop_table r8a77970_mstp_table[] = {
{ 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 },
{ 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 },
@ -154,6 +187,11 @@ static const struct mstp_stop_table r8a77970_mstp_table[] = {
{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
};
static const void *r8a77970_get_pll_config(const u32 cpg_mode)
{
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
}
static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
.core_clk = r8a77970_core_clks,
.core_clk_size = ARRAY_SIZE(r8a77970_core_clks),
@ -166,6 +204,7 @@ static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = CLK_EXTALR,
.get_pll_config = r8a77970_get_pll_config,
};
static const struct udevice_id r8a77970_clk_ids[] = {

24
drivers/clk/renesas/r8a77995-cpg-mssr.c
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@ -169,6 +169,24 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
};
/*
* CPG Clock Data
*/
/*
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
*--------------------------------------------------------------------
* 0 48 x 1 x250/4 x100/3 x100/3
* 1 48 x 1 x250/4 x100/3 x116/6
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 100, 3, 100, 3, },
{ 1, 100, 3, 116, 6, },
};
static const struct mstp_stop_table r8a77995_mstp_table[] = {
{ 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
{ 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
@ -178,6 +196,11 @@ static const struct mstp_stop_table r8a77995_mstp_table[] = {
{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
};
static const void *r8a77995_get_pll_config(const u32 cpg_mode)
{
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
}
static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
.core_clk = r8a77995_core_clks,
.core_clk_size = ARRAY_SIZE(r8a77995_core_clks),
@ -189,6 +212,7 @@ static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = ~0,
.get_pll_config = r8a77995_get_pll_config,
};
static const struct udevice_id r8a77995_clk_ids[] = {

1
drivers/clk/renesas/renesas-cpg-mssr.h
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@ -26,6 +26,7 @@ struct cpg_mssr_info {
unsigned int mod_clk_base;
unsigned int clk_extal_id;
unsigned int clk_extalr_id;
const void *(*get_pll_config)(const u32 cpg_mode);
};
struct gen3_clk_priv {

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