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@ -113,10 +113,17 @@ static void reg_file_set_sub_stage(u8 set_sub_stage) |
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clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8); |
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} |
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/**
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* phy_mgr_initialize() - Initialize PHY Manager |
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* |
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* Initialize PHY Manager. |
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*/ |
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static void phy_mgr_initialize(void) |
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{ |
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u32 ratio; |
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debug("%s:%d\n", __func__, __LINE__); |
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/* USER calibration has control over path to memory */ |
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/* Calibration has control over path to memory */ |
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/*
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* In Hard PHY this is a 2-bit control: |
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* 0: AFI Mux Select |
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@ -132,21 +139,19 @@ static void phy_mgr_initialize(void) |
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writel(0, &phy_mgr_cfg->cal_debug_info); |
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if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) { |
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param->read_correct_mask_vg = ((uint32_t)1 << |
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(RW_MGR_MEM_DQ_PER_READ_DQS / |
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RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1; |
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param->write_correct_mask_vg = ((uint32_t)1 << |
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(RW_MGR_MEM_DQ_PER_READ_DQS / |
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RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1; |
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param->read_correct_mask = ((uint32_t)1 << |
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RW_MGR_MEM_DQ_PER_READ_DQS) - 1; |
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param->write_correct_mask = ((uint32_t)1 << |
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RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1; |
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param->dm_correct_mask = ((uint32_t)1 << |
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(RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH)) |
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- 1; |
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} |
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/* Init params only if we do NOT skip calibration. */ |
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if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) |
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return; |
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ratio = RW_MGR_MEM_DQ_PER_READ_DQS / |
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RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS; |
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param->read_correct_mask_vg = (1 << ratio) - 1; |
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param->write_correct_mask_vg = (1 << ratio) - 1; |
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param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1; |
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param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1; |
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ratio = RW_MGR_MEM_DATA_WIDTH / |
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RW_MGR_MEM_DATA_MASK_WIDTH; |
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param->dm_correct_mask = (1 << ratio) - 1; |
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} |
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static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode) |
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