@ -60,115 +60,6 @@ typedef struct {
ulong or ;
} pcmcia_win_t ;
/*
* Definitions for PCMCIA control registers to operate in IDE mode
*
* All timing related setup ( PCMCIA_SHT , PCMCIA_SST , PCMCIA_SL )
* to be done later ( depending on CPU clock )
*/
/* Window 0:
* Base : 0xFE100000 CS1
* Port Size : 2 Bytes
* Port Size : 16 Bit
* Common Memory Space
*/
# define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
# define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
| PCMCIA_PPS_16 \
| PCMCIA_PRS_MEM \
| PCMCIA_SLOT_x \
| PCMCIA_PV \
)
/* Window 1:
* Base : 0xFE100080 CS1
* Port Size : 8 Bytes
* Port Size : 8 Bit
* Common Memory Space
*/
# define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
# define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
| PCMCIA_PPS_8 \
| PCMCIA_PRS_MEM \
| PCMCIA_SLOT_x \
| PCMCIA_PV \
)
/* Window 2:
* Base : 0xFE100100 CS2
* Port Size : 8 Bytes
* Port Size : 8 Bit
* Common Memory Space
*/
# define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
# define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
| PCMCIA_PPS_8 \
| PCMCIA_PRS_MEM \
| PCMCIA_SLOT_x \
| PCMCIA_PV \
)
/* Window 3:
* not used
*/
# define CONFIG_SYS_PCMCIA_PBR3 0
# define CONFIG_SYS_PCMCIA_POR3 0
/* Window 4:
* Base : 0xFE100C00 CS1
* Port Size : 2 Bytes
* Port Size : 16 Bit
* Common Memory Space
*/
# define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
# define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
| PCMCIA_PPS_16 \
| PCMCIA_PRS_MEM \
| PCMCIA_SLOT_x \
| PCMCIA_PV \
)
/* Window 5:
* Base : 0xFE100C80 CS1
* Port Size : 8 Bytes
* Port Size : 8 Bit
* Common Memory Space
*/
# define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
# define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
| PCMCIA_PPS_8 \
| PCMCIA_PRS_MEM \
| PCMCIA_SLOT_x \
| PCMCIA_PV \
)
/* Window 6:
* Base : 0xFE100D00 CS2
* Port Size : 8 Bytes
* Port Size : 8 Bit
* Common Memory Space
*/
# define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
# define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
| PCMCIA_PPS_8 \
| PCMCIA_PRS_MEM \
| PCMCIA_SLOT_x \
| PCMCIA_PV \
)
/* Window 7:
* not used
*/
# define CONFIG_SYS_PCMCIA_PBR7 0
# define CONFIG_SYS_PCMCIA_POR7 0
/**********************************************************************/
/*