This patch removes all EBC related defines from the PPC4xx headers ppc405.h and ppc440.h and introduces a new header include/asm-ppc/ppc4xx-ebc.h with all those defines. Signed-off-by: Stefan Roese <sr@denx.de>master
Stefan Roese
16 years ago
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e321801bed
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7ee2619c20
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/*
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* (C) Copyright 2008 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _PPC4xx_EBC_H_ |
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#define _PPC4xx_EBC_H_ |
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/*
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* Currently there are two register layout versions for the |
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* IBM EBC core used on 4xx PPC's: |
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*/ |
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#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ |
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defined(CONFIG_405EP) || \
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defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
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#define CONFIG_EBC_PPC4xx_IBM_VER1 |
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#endif |
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/* Bank Configuration Register */ |
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#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) |
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#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK)) |
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#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) |
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#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) |
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#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) |
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#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) |
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#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) |
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#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) |
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#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) |
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#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) |
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#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) |
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#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) |
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#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) |
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#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) |
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#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) |
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#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) |
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#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) |
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#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) |
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#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) |
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#if defined(CONFIG_EBC_PPC4xx_IBM_VER1) |
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#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x2) |
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#else |
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#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) |
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#endif |
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/* Bank Access Parameter Register */ |
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#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) |
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#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) |
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#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF) |
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#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F) |
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#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7) |
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#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) |
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#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) |
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#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) |
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#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) |
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#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) |
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#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) |
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#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) |
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#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3) |
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#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3) |
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#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3) |
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#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3) |
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#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7) |
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#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) |
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#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) |
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#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) |
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#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) |
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#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) |
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#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) |
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#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) |
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#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) |
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/* Common fields in EBC0_CFG register */ |
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#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) |
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#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) |
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#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) |
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#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) |
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#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) |
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#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) |
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#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) |
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#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) |
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#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) |
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#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) |
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#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) |
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#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) |
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#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) |
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#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) |
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#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) |
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#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) |
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#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F) |
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/* Now the two versions of the other bits */ |
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#if defined(CONFIG_EBC_PPC4xx_IBM_VER1) |
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#define EBC_CFG_EBTC_MASK PPC_REG_VAL(0, 0x1) |
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#define EBC_CFG_EBTC_HI PPC_REG_VAL(0, 0x0) |
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#define EBC_CFG_EBTC_DRIVEN PPC_REG_VAL(0, 0x1) |
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#define EBC_CFG_EMPH_MASK PPC_REG_VAL(6, 0x3) |
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#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(6, (static_cast(u32, n)) & 0x3) |
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#define EBC_CFG_EMPL_MASK PPC_REG_VAL(8, 0x3) |
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#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x3) |
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#define EBC_CFG_CSTC_MASK PPC_REG_VAL(9, 0x1) |
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#define EBC_CFG_CSTC_HI PPC_REG_VAL(9, 0x0) |
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#define EBC_CFG_CSTC_DRIVEN PPC_REG_VAL(9, 0x1) |
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#define EBC_CFG_BPR_MASK PPC_REG_VAL(11, 0x3) |
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#define EBC_CFG_BPR_1DW PPC_REG_VAL(11, 0x0) |
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#define EBC_CFG_BPR_2DW PPC_REG_VAL(11, 0x1) |
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#define EBC_CFG_BPR_4DW PPC_REG_VAL(11, 0x2) |
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#define EBC_CFG_EMS_MASK PPC_REG_VAL(13, 0x3) |
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#define EBC_CFG_EMS_8BIT PPC_REG_VAL(13, 0x0) |
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#define EBC_CFG_EMS_16BIT PPC_REG_VAL(13, 0x1) |
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#define EBC_CFG_EMS_32BIT PPC_REG_VAL(13, 0x2) |
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#else |
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#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) |
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#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) |
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#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) |
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#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) |
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#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) |
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#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) |
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#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) |
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#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) |
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#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) |
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#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) |
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#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) |
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#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) |
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#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) |
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#define EBC_CFG_OEO_HI PPC_REG_VAL(8, 0x0) |
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#define EBC_CFG_OEO_PREVIOUS PPC_REG_VAL(8, 0x1) |
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#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) |
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#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) |
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#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) |
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#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) |
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#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) |
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#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) |
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#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) |
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#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) |
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#endif |
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#endif /* _PPC4xx_EBC_H_ */ |
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