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@ -142,7 +142,6 @@ |
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#ifdef CONFIG_NAND_DENALI |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
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#define CONFIG_SYS_NAND_ONFI_DETECTION |
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#define CONFIG_NAND_DENALI_ECC_SIZE 512 |
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#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS |
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#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS |
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#endif |
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@ -294,7 +293,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); |
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/* SPL NAND boot support */ |
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#ifdef CONFIG_SPL_NAND_SUPPORT |
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#define CONFIG_SYS_NAND_USE_FLASH_BBT |
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 |
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 |
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#endif |
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