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ARM: socfpga: Add new CycloneV SoC Devboards DBM-SoC1 board

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Add support for a new boards from devboards.de , the DBM-SoC1 .
This board has one ethernet port, one USB OTG port and USB UART.

Signed-off-by: Marek Vasut <marex@denx.de>
master
Marek Vasut 7 years ago
parent 85447f785c
commit 7fb464302e
12 changed files with 1551 additions and 0 deletions
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  1. 1
      arch/arm/dts/Makefile
  2. 59
      arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
  3. 7
      arch/arm/mach-socfpga/Kconfig
  4. 4
      board/devboards/dbm-soc1/MAINTAINERS
  5. 7
      board/devboards/dbm-soc1/Makefile
  6. 660
      board/devboards/dbm-soc1/qts/iocsr_config.h
  7. 219
      board/devboards/dbm-soc1/qts/pinmux_config.h
  8. 85
      board/devboards/dbm-soc1/qts/pll_config.h
  9. 344
      board/devboards/dbm-soc1/qts/sdram_config.h
  10. 6
      board/devboards/dbm-soc1/socfpga.c
  11. 63
      configs/socfpga_dbm_soc1_defconfig
  12. 96
      include/configs/socfpga_dbm_soc1.h

1
arch/arm/dts/Makefile
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@ -177,6 +177,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_dbm_soc1.dtb \
socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_de1_soc.dtb \
socfpga_cyclone5_de10_nano.dtb \

59
arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
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@ -0,0 +1,59 @@
/*
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "socfpga_cyclone5.dtsi"
/ {
model = "Devboards.de DBM-SoC1";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,115200";
};
aliases {
ethernet0 = &gmac1;
udc0 = &usb1;
};
memory {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
soc {
u-boot,dm-pre-reloc;
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&mmc0 {
status = "okay";
bus-width = <4>;
u-boot,dm-pre-reloc;
};
&usb1 {
disable-over-current;
status = "okay";
};

7
arch/arm/mach-socfpga/Kconfig
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@ -69,6 +69,10 @@ config TARGET_SOCFPGA_ARIES_MCVEVK
bool "Aries MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
bool "Devboards DBM-SoC1 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_EBV_SOCRATES
bool "EBV SoCrates (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@ -108,6 +112,7 @@ config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
@ -123,6 +128,7 @@ config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@ -137,6 +143,7 @@ config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO

4
board/devboards/dbm-soc1/MAINTAINERS
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@ -0,0 +1,4 @@
Devboards.de DBM-SoC1 BOARD
M: Marek Vasut <marex@denx.de>
F: include/configs/socfpga_dbm_soc1.h
F: configs/socfpga_dbm_soc1_defconfig

7
board/devboards/dbm-soc1/Makefile
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@ -0,0 +1,7 @@
#
# Copyright (C) 2018 Marek Vasut <marex@denx.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := socfpga.o

660
board/devboards/dbm-soc1/qts/iocsr_config.h
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@ -0,0 +1,660 @@
/*
* Altera SoCFPGA IOCSR configuration
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
0x00000000,
0x0FF00000,
0xC0000000,
0x0000003F,
0x00008000,
0x00004824,
0x01209000,
0x82400000,
0x00018004,
0x00000000,
0x00004000,
0x00002412,
0x00904800,
0x41200000,
0x80000002,
0x00000904,
0x00002000,
0x00001209,
0x00482400,
0x20900000,
0x40000001,
0x00000482,
0x00001000,
};
const unsigned long iocsr_scan_chain1_table[] = {
0x00009048,
0x02412000,
0x048000C0,
0x00000009,
0x00002412,
0x00008000,
0x00004824,
0x01209000,
0x82400000,
0x00000004,
0x00001209,
0x00004000,
0x00002412,
0x00904800,
0x41200000,
0x80000002,
0x00000904,
0x00002000,
0x06001209,
0x00482400,
0x01FE0000,
0xF8000000,
0x00000007,
0x80001000,
0x00000904,
0x00241200,
0x90480000,
0x20003000,
0x00000241,
0x00000800,
0x00000000,
0x00000000,
0x48240000,
0x90000000,
0x00000120,
0x00000400,
0x00000000,
0x00090480,
0x00000003,
0x00000000,
0x00000000,
0x90000200,
0x00600120,
0x00000000,
0x12090000,
0x24000600,
0x00000048,
0x48000100,
0x00300090,
0xC0024120,
0x09048000,
0x12000300,
0x000C0024,
0x00000080,
};
const unsigned long iocsr_scan_chain2_table[] = {
0x30009048,
0x00000000,
0x0FF00000,
0x00000000,
0x0C002412,
0x00008000,
0x18004824,
0x01209000,
0x82400060,
0x00018004,
0x06001209,
0x00004000,
0x00002412,
0x00904800,
0x00000030,
0x80000000,
0x03000904,
0x00002000,
0x00001209,
0x00482400,
0x20900000,
0x40000001,
0x00000482,
0x80001000,
0x00000904,
0x00000000,
0x90480000,
0x20000000,
0x00C00241,
0x00000800,
};
const unsigned long iocsr_scan_chain3_table[] = {
0x0C420D80,
0x082000FF,
0x0A804001,
0x07900000,
0x08020000,
0x00100000,
0x0A800000,
0x07900000,
0x08020000,
0x00100000,
0xC8800000,
0x00003001,
0x00C00722,
0x00000000,
0x00000021,
0x82000004,
0x05400000,
0x03C80000,
0x04010000,
0x00080000,
0x05400000,
0x03C80000,
0x05400000,
0x03C80000,
0xE4400000,
0x00001800,
0x00600391,
0x800E4400,
0x00000001,
0x40000002,
0x02A00000,
0x01E40000,
0x02A00000,
0x01E40000,
0x02A00000,
0x01E40000,
0x02A00000,
0x01E40000,
0x72200000,
0x80000C00,
0x003001C8,
0xC0072200,
0x1C880000,
0x20000300,
0x00040000,
0x50670000,
0x00000010,
0x24590000,
0x00001000,
0xA0000034,
0x0D000001,
0xC0680618,
0x45034071,
0x0A281A01,
0x806180D0,
0x34071C06,
0x01A034D0,
0x180D0000,
0x71C06806,
0x01450340,
0xD000001A,
0x0680E380,
0x10040000,
0x00200000,
0x10040000,
0x00200000,
0x15000000,
0x0F200000,
0x15000000,
0x0F200000,
0x01FE0000,
0x00000000,
0x01800E44,
0x00391000,
0x007F8006,
0x00000000,
0x0A800001,
0x07900000,
0x0A800000,
0x07900000,
0x0A800000,
0x07900000,
0x08020000,
0x00100000,
0xC8800000,
0x00003001,
0x00C00722,
0x00000FF0,
0x72200000,
0x80000C00,
0x05400000,
0x02480000,
0x04000000,
0x00080000,
0x05400000,
0x03C80000,
0x05400000,
0x03C80000,
0x6A1C0000,
0x00001800,
0x00600391,
0x800E4400,
0x1A870001,
0x40000600,
0x02A00040,
0x01E40000,
0x02A00000,
0x01E40000,
0x02A00000,
0x01E40000,
0x02A00000,
0x01E40000,
0x72200000,
0x80000C00,
0x003001C8,
0xC0072200,
0x1C880000,
0x20000300,
0x00040000,
0x50670000,
0x00000010,
0x24590000,
0x00001000,
0xA0000034,
0x0D000001,
0xC0680618,
0x45034071,
0x0A281A01,
0x806180D0,
0x34071C06,
0x01A00040,
0x180D0002,
0x71C06806,
0x01450340,
0xD00A281A,
0x06806180,
0x10040000,
0x00200000,
0x10040000,
0x00200000,
0x15000000,
0x0F200000,
0x15000000,
0x0F200000,
0x01FE0000,
0x00000000,
0x01800E44,
0x00391000,
0x007F8006,
0x00000000,
0x99300001,
0x34343400,
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
0x01C3A800,
0x00040100,
0x00000800,
0x00000000,
0x00001208,
0x00482000,
0x01000000,
0x00000000,
0x00410482,
0x0006A000,
0x0001B400,
0x00020000,
0x00000400,
0x0002A000,
0x0001E400,
0x5506A000,
0x00E1D400,
0x00000000,
0xC880090C,
0x00003001,
0x90400000,
0x00000000,
0x2020C243,
0x2A835000,
0x0070EA00,
0x2A835000,
0x0070EA00,
0x2A835000,
0x0070EA00,
0x00010040,
0x00000200,
0x00000000,
0x00000482,
0x00120800,
0x00002000,
0x80000000,
0x00104120,
0x00000200,
0xAC0D5F80,
0xFFFFFFFF,
0x14F3690D,
0x1A041414,
0x00D00000,
0x14864000,
0x59647A05,
0xCB2CA3DD,
0xF5D1451E,
0x034AD348,
0x821A0000,
0x0000D000,
0x030C0680,
0xDD59647A,
0x1ECB2CA3,
0x48F5D145,
0x00035AD3,
0x00080200,
0x00001000,
0x00080200,
0x00001000,
0x000A8000,
0x00075000,
0x541A8000,
0x03875001,
0x10000000,
0x00000000,
0x0080C000,
0x41000000,
0x00003FC2,
0x00820000,
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
0x01C3A800,
0x00040100,
0x00000800,
0x00000000,
0x00001208,
0x00482000,
0x00008000,
0x00000000,
0x00410482,
0x0006A000,
0x0001B400,
0x00020000,
0x00000400,
0x00020080,
0x00000400,
0x5506A000,
0x00E1D400,
0x00000000,
0x0000090C,
0x00000010,
0x90400000,
0x00000000,
0x2020C243,
0x2A835000,
0x0070EA00,
0x2A835000,
0x0070EA00,
0x2A835000,
0x0070EA00,
0x00015000,
0x0000F200,
0x00000000,
0x00000482,
0x00120800,
0x00600391,
0x80000000,
0x00104120,
0x00000200,
0xAC0D5F80,
0xFFFFFFFF,
0x14F3690D,
0x1A041414,
0x00D00000,
0x14864000,
0x59647A05,
0x8B2CA3DD,
0xF6D1451E,
0x035AD348,
0x821A0041,
0x0000D000,
0x00000680,
0xDD59647A,
0x1ECB2CA3,
0x48F6D145,
0x00035AD3,
0x00080200,
0x00001000,
0x00080200,
0x00001000,
0x000A8000,
0x00075000,
0x541A8000,
0x03875001,
0x10000000,
0x00000000,
0x0080C000,
0x41000000,
0x04000002,
0x00820000,
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
0x01C3A800,
0x00040100,
0x00000800,
0x00000000,
0x00001208,
0x00482000,
0x00008000,
0x00000000,
0x00410482,
0x0006A000,
0x0001B400,
0x00020000,
0x00000400,
0x0002A000,
0x0001E400,
0x5506A000,
0x00E1D400,
0x00000000,
0xC880090C,
0x00003001,
0x90400000,
0x00000000,
0x2020C243,
0x2A835000,
0x0070EA00,
0x2A835000,
0x0070EA00,
0x2A835000,
0x0070EA00,
0x00010040,
0x00000200,
0x00000000,
0x00000482,
0x00120800,
0x00002000,
0x80000000,
0x00104120,
0x00000200,
0xAC0D5F80,
0xFFFFFFFF,
0x14F3690D,
0x1A041414,
0x00D00000,
0x14864000,
0x59647A05,
0xCB2CA3D5,
0xF6D1451E,
0x035AB2C8,
0x821A0000,
0x0000D000,
0x00000680,
0xDD59647A,
0x1ECB2CA3,
0x48F6D145,
0x00034AD3,
0x00080200,
0x00001000,
0x00080200,
0x00001000,
0x000A8000,
0x00075000,
0x541A8000,
0x03875001,
0x10000000,
0x00000000,
0x0080C000,
0x41000000,
0x04000002,
0x00820000,
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
0x01C3A800,
0x00040100,
0x00000800,
0x00000000,
0x00001208,
0x00482000,
0x00008000,
0x00000000,
0x00410482,
0x0006A000,
0x0001B400,
0x00020000,
0x00000400,
0x00020080,
0x00000400,
0x5506A000,
0x00E1D400,
0x00000000,
0x0000090C,
0x00000010,
0x90400000,
0x00000000,
0x2020C243,
0x2A835000,
0x0070EA00,
0x2A835000,
0x0070EA00,
0x2A835000,
0x0070EA00,
0x00010040,
0x00000200,
0x00000000,
0x00000482,
0x00120800,
0x00400000,
0x80000000,
0x00104120,
0x00000200,
0xAC0D5F80,
0xFFFFFFFF,
0x14F1690D,
0x1A041414,
0x00D00000,
0x04864000,
0x69A47A01,
0x8B2CA3D5,
0xF6D1451E,
0x034A9248,
0x821A0000,
0x0000D000,
0x00000680,
0xD569A47A,
0x1E8B2CA3,
0x48F6D145,
0x00034A92,
0x00080200,
0x00001000,
0x00080200,
0x00001000,
0x000A8000,
0x00075000,
0x541A8000,
0x03875001,
0x10000000,
0x00000000,
0x0080C000,
0x41000000,
0x04000002,
0x00820000,
0x00489800,
0x801A1A1A,
0x00000200,
0x80000004,
0x00000200,
0x80000004,
0x00000200,
0x80000004,
0x00000200,
0x00000004,
0x00040000,
0x10000000,
0x00000000,
0x00000040,
0x00010000,
0x40002000,
0x00000100,
0x40000002,
0x00000100,
0x40000002,
0x00000100,
0x40000002,
0x00000100,
0x00000002,
0x00020000,
0x08000000,
0x00000000,
0x00000020,
0x00008000,
0x20001000,
0x00000080,
0x20000001,
0x00000080,
0x20000001,
0x00000080,
0x20000001,
0x00000080,
0x00000001,
0x00010000,
0x04000000,
0x00FF0000,
0x00000000,
0x00004000,
0x00000800,
0xC0000001,
0x00041419,
0x40000000,
0x04000816,
0x000D0000,
0x00006800,
0x00000340,
0xD000001A,
0x06800000,
0x00340000,
0x0001A000,
0x00000D00,
0x40000068,
0x1A000003,
0x00D00000,
0x00068000,
0x00003400,
0x000001A0,
0x00000401,
0x00000008,
0x00000401,
0x00000008,
0x00000401,
0x00000008,
0x00000401,
0x80000008,
0x0000007F,
0x20000000,
0x00000000,
0xE0000080,
0x0000001F,
0x00004000,
};
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

219
board/devboards/dbm-soc1/qts/pinmux_config.h
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@ -0,0 +1,219 @@
/*
* Altera SoCFPGA PinMux configuration
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SOCFPGA_PINMUX_CONFIG_H__
#define __SOCFPGA_PINMUX_CONFIG_H__
const u8 sys_mgr_init_table[] = {
0, /* EMACIO0 */
2, /* EMACIO1 */
2, /* EMACIO2 */
2, /* EMACIO3 */
2, /* EMACIO4 */
2, /* EMACIO5 */
2, /* EMACIO6 */
2, /* EMACIO7 */
2, /* EMACIO8 */
0, /* EMACIO9 */
2, /* EMACIO10 */
2, /* EMACIO11 */
2, /* EMACIO12 */
2, /* EMACIO13 */
0, /* EMACIO14 */
0, /* EMACIO15 */
0, /* EMACIO16 */
0, /* EMACIO17 */
0, /* EMACIO18 */
0, /* EMACIO19 */
3, /* FLASHIO0 */
0, /* FLASHIO1 */
3, /* FLASHIO2 */
3, /* FLASHIO3 */
0, /* FLASHIO4 */
0, /* FLASHIO5 */
0, /* FLASHIO6 */
0, /* FLASHIO7 */
0, /* FLASHIO8 */
3, /* FLASHIO9 */
3, /* FLASHIO10 */
3, /* FLASHIO11 */
0, /* GENERALIO0 */
1, /* GENERALIO1 */
1, /* GENERALIO2 */
0, /* GENERALIO3 */
0, /* GENERALIO4 */
0, /* GENERALIO5 */
0, /* GENERALIO6 */
0, /* GENERALIO7 */
0, /* GENERALIO8 */
3, /* GENERALIO9 */
3, /* GENERALIO10 */
3, /* GENERALIO11 */
3, /* GENERALIO12 */
1, /* GENERALIO13 */
1, /* GENERALIO14 */
1, /* GENERALIO15 */
1, /* GENERALIO16 */
1, /* GENERALIO17 */
1, /* GENERALIO18 */
0, /* GENERALIO19 */
0, /* GENERALIO20 */
0, /* GENERALIO21 */
0, /* GENERALIO22 */
0, /* GENERALIO23 */
0, /* GENERALIO24 */
0, /* GENERALIO25 */
0, /* GENERALIO26 */
0, /* GENERALIO27 */
0, /* GENERALIO28 */
0, /* GENERALIO29 */
0, /* GENERALIO30 */
0, /* GENERALIO31 */
2, /* MIXED1IO0 */
2, /* MIXED1IO1 */
2, /* MIXED1IO2 */
2, /* MIXED1IO3 */
2, /* MIXED1IO4 */
2, /* MIXED1IO5 */
2, /* MIXED1IO6 */
2, /* MIXED1IO7 */
2, /* MIXED1IO8 */
2, /* MIXED1IO9 */
2, /* MIXED1IO10 */
2, /* MIXED1IO11 */
2, /* MIXED1IO12 */
2, /* MIXED1IO13 */
0, /* MIXED1IO14 */
3, /* MIXED1IO15 */
3, /* MIXED1IO16 */
3, /* MIXED1IO17 */
3, /* MIXED1IO18 */
3, /* MIXED1IO19 */
3, /* MIXED1IO20 */
0, /* MIXED1IO21 */
0, /* MIXED2IO0 */
0, /* MIXED2IO1 */
0, /* MIXED2IO2 */
0, /* MIXED2IO3 */
0, /* MIXED2IO4 */
0, /* MIXED2IO5 */
0, /* MIXED2IO6 */
0, /* MIXED2IO7 */
0, /* GPLINMUX48 */
0, /* GPLINMUX49 */
0, /* GPLINMUX50 */
0, /* GPLINMUX51 */
0, /* GPLINMUX52 */
0, /* GPLINMUX53 */
0, /* GPLINMUX54 */
0, /* GPLINMUX55 */
0, /* GPLINMUX56 */
0, /* GPLINMUX57 */
0, /* GPLINMUX58 */
0, /* GPLINMUX59 */
0, /* GPLINMUX60 */
0, /* GPLINMUX61 */
0, /* GPLINMUX62 */
0, /* GPLINMUX63 */
0, /* GPLINMUX64 */
0, /* GPLINMUX65 */
0, /* GPLINMUX66 */
0, /* GPLINMUX67 */
0, /* GPLINMUX68 */
0, /* GPLINMUX69 */
0, /* GPLINMUX70 */
1, /* GPLMUX0 */
1, /* GPLMUX1 */
1, /* GPLMUX2 */
1, /* GPLMUX3 */
1, /* GPLMUX4 */
1, /* GPLMUX5 */
1, /* GPLMUX6 */
1, /* GPLMUX7 */
1, /* GPLMUX8 */
1, /* GPLMUX9 */
1, /* GPLMUX10 */
1, /* GPLMUX11 */
1, /* GPLMUX12 */
1, /* GPLMUX13 */
1, /* GPLMUX14 */
1, /* GPLMUX15 */
1, /* GPLMUX16 */
1, /* GPLMUX17 */
1, /* GPLMUX18 */
1, /* GPLMUX19 */
1, /* GPLMUX20 */
1, /* GPLMUX21 */
1, /* GPLMUX22 */
1, /* GPLMUX23 */
1, /* GPLMUX24 */
1, /* GPLMUX25 */
1, /* GPLMUX26 */
1, /* GPLMUX27 */
1, /* GPLMUX28 */
1, /* GPLMUX29 */
1, /* GPLMUX30 */
1, /* GPLMUX31 */
1, /* GPLMUX32 */
1, /* GPLMUX33 */
1, /* GPLMUX34 */
1, /* GPLMUX35 */
1, /* GPLMUX36 */
1, /* GPLMUX37 */
1, /* GPLMUX38 */
1, /* GPLMUX39 */
1, /* GPLMUX40 */
1, /* GPLMUX41 */
1, /* GPLMUX42 */
1, /* GPLMUX43 */
1, /* GPLMUX44 */
1, /* GPLMUX45 */
1, /* GPLMUX46 */
1, /* GPLMUX47 */
1, /* GPLMUX48 */
1, /* GPLMUX49 */
1, /* GPLMUX50 */
1, /* GPLMUX51 */
1, /* GPLMUX52 */
1, /* GPLMUX53 */
1, /* GPLMUX54 */
1, /* GPLMUX55 */
1, /* GPLMUX56 */
1, /* GPLMUX57 */
1, /* GPLMUX58 */
1, /* GPLMUX59 */
1, /* GPLMUX60 */
1, /* GPLMUX61 */
1, /* GPLMUX62 */
1, /* GPLMUX63 */
1, /* GPLMUX64 */
1, /* GPLMUX65 */
1, /* GPLMUX66 */
1, /* GPLMUX67 */
1, /* GPLMUX68 */
1, /* GPLMUX69 */
1, /* GPLMUX70 */
0, /* NANDUSEFPGA */
0, /* UART0USEFPGA */
0, /* RGMII1USEFPGA */
0, /* SPIS0USEFPGA */
0, /* CAN0USEFPGA */
0, /* I2C0USEFPGA */
0, /* SDMMCUSEFPGA */
0, /* QSPIUSEFPGA */
0, /* SPIS1USEFPGA */
0, /* RGMII0USEFPGA */
0, /* UART1USEFPGA */
0, /* CAN1USEFPGA */
0, /* USB1USEFPGA */
0, /* I2C3USEFPGA */
0, /* I2C2USEFPGA */
0, /* I2C1USEFPGA */
0, /* SPIM1USEFPGA */
0, /* USB0USEFPGA */
0 /* SPIM0USEFPGA */
};
#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */

85
board/devboards/dbm-soc1/qts/pll_config.h
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/*
* Altera SoCFPGA Clock and PLL configuration
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
#define CONFIG_HPS_CLK_NAND_HZ 50000000
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
#define CONFIG_HPS_CLK_QSPI_HZ 400000000
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
#define CONFIG_HPS_CLK_CAN0_HZ 12500000
#define CONFIG_HPS_CLK_CAN1_HZ 12500000
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */

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board/devboards/dbm-soc1/qts/sdram_config.h
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/*
* Altera SoCFPGA SDRAM configuration
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SOCFPGA_SDRAM_CONFIG_H__
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
#define RW_MGR_ACTIVATE_1 0x0F
#define RW_MGR_CLEAR_DQS_ENABLE 0x49
#define RW_MGR_GUARANTEED_READ 0x4C
#define RW_MGR_GUARANTEED_READ_CONT 0x54
#define RW_MGR_GUARANTEED_WRITE 0x18
#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
#define RW_MGR_IDLE 0x00
#define RW_MGR_IDLE_LOOP1 0x7B
#define RW_MGR_IDLE_LOOP2 0x7A
#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
#define RW_MGR_INIT_RESET_1_CKE_0 0x74
#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
#define RW_MGR_MRS0_DLL_RESET 0x02
#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
#define RW_MGR_MRS0_USER 0x07
#define RW_MGR_MRS0_USER_MIRR 0x0C
#define RW_MGR_MRS1 0x03
#define RW_MGR_MRS1_MIRR 0x09
#define RW_MGR_MRS2 0x04
#define RW_MGR_MRS2_MIRR 0x0A
#define RW_MGR_MRS3 0x05
#define RW_MGR_MRS3_MIRR 0x0B
#define RW_MGR_PRECHARGE_ALL 0x12
#define RW_MGR_READ_B2B 0x59
#define RW_MGR_READ_B2B_WAIT1 0x61
#define RW_MGR_READ_B2B_WAIT2 0x6B
#define RW_MGR_REFRESH_ALL 0x14
#define RW_MGR_RETURN 0x01
#define RW_MGR_SGLE_READ 0x7D
#define RW_MGR_ZQCL 0x06
/* Sequencer defines configuration */
#define AFI_RATE_RATIO 1
#define CALIB_LFIFO_OFFSET 7
#define CALIB_VFIFO_OFFSET 5
#define ENABLE_SUPER_QUICK_CALIBRATION 0
#define IO_DELAY_PER_DCHAIN_TAP 25
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
#define IO_DELAY_PER_OPA_TAP 312
#define IO_DLL_CHAIN_LENGTH 8
#define IO_DQDQS_OUT_PHASE_MAX 0
#define IO_DQS_EN_DELAY_MAX 31
#define IO_DQS_EN_DELAY_OFFSET 0
#define IO_DQS_EN_PHASE_MAX 7
#define IO_DQS_IN_DELAY_MAX 31
#define IO_DQS_IN_RESERVE 4
#define IO_DQS_OUT_RESERVE 4
#define IO_IO_IN_DELAY_MAX 31
#define IO_IO_OUT1_DELAY_MAX 31
#define IO_IO_OUT2_DELAY_MAX 0
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
#define MAX_LATENCY_COUNT_WIDTH 5
#define READ_VALID_FIFO_SIZE 16
#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504a1
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
#define RW_MGR_MEM_DATA_WIDTH 32
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
#define TINIT_CNTR0_VAL 99
#define TINIT_CNTR1_VAL 32
#define TINIT_CNTR2_VAL 32
#define TRESET_CNTR0_VAL 99
#define TRESET_CNTR1_VAL 99
#define TRESET_CNTR2_VAL 10
/* Sequencer ac_rom_init configuration */
const u32 ac_rom_init[] = {
0x20700000,
0x20780000,
0x10080421,
0x10080520,
0x10090044,
0x100a0008,
0x100b0000,
0x10380400,
0x10080441,
0x100804c0,
0x100a0024,
0x10090010,
0x100b0000,
0x30780000,
0x38780000,
0x30780000,
0x10680000,
0x106b0000,
0x10280400,
0x10480000,
0x1c980000,
0x1c9b0000,
0x1c980008,
0x1c9b0008,
0x38f80000,
0x3cf80000,
0x38780000,
0x18180000,
0x18980000,
0x13580000,
0x135b0000,
0x13580008,
0x135b0008,
0x33780000,
0x10580008,
0x10780000
};
/* Sequencer inst_rom_init configuration */
const u32 inst_rom_init[] = {
0x80000,
0x80680,
0x8180,
0x8200,
0x8280,
0x8300,
0x8380,
0x8100,
0x8480,
0x8500,
0x8580,
0x8600,
0x8400,
0x800,
0x8680,
0x880,
0xa680,
0x80680,
0x900,
0x80680,
0x980,
0xa680,
0x8680,
0x80680,
0xb68,
0xcce8,
0xae8,
0x8ce8,
0xb88,
0xec88,
0xa08,
0xac88,
0x80680,
0xce00,
0xcd80,
0xe700,
0xc00,
0x20ce0,
0x20ce0,
0x20ce0,
0x20ce0,
0xd00,
0x680,
0x680,
0x680,
0x680,
0x60e80,
0x61080,
0x61080,
0x61080,
0xa680,
0x8680,
0x80680,
0xce00,
0xcd80,
0xe700,
0xc00,
0x30ce0,
0x30ce0,
0x30ce0,
0x30ce0,
0xd00,
0x680,
0x680,
0x680,
0x680,
0x70e80,
0x71080,
0x71080,
0x71080,
0xa680,
0x8680,
0x80680,
0x1158,
0x6d8,
0x80680,
0x1168,
0x7e8,
0x7e8,
0x87e8,
0x40fe8,
0x410e8,
0x410e8,
0x410e8,
0x1168,
0x7e8,
0x7e8,
0xa7e8,
0x80680,
0x40e88,
0x41088,
0x41088,
0x41088,
0x40f68,
0x410e8,
0x410e8,
0x410e8,
0xa680,
0x40fe8,
0x410e8,
0x410e8,
0x410e8,
0x41008,
0x41088,
0x41088,
0x41088,
0x1100,
0xc680,
0x8680,
0xe680,
0x80680,
0x0,
0x8000,
0xa000,
0xc000,
0x80000,
0x80,
0x8080,
0xa080,
0xc080,
0x80080,
0x9180,
0x8680,
0xa680,
0x80680,
0x40f08,
0x80680
};
#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */

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board/devboards/dbm-soc1/socfpga.c
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/*
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>

63
configs/socfpga_dbm_soc1_defconfig
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CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="devboards"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y

96
include/configs/socfpga_dbm_soc1.h
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/*
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_DEVBOARDS_DBM_SOC1_H__
#define __CONFIG_DEVBOARDS_DBM_SOC1_H__
#include <asm/arch/base_addr_ac5.h>
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_PREBOOT "run try_bootscript"
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Environment is in MMC */
#define CONFIG_ENV_OVERWRITE
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"consdev=ttyS0\0" \
"baudrate=115200\0" \
"bootscript=boot.scr\0" \
"bootdev=/dev/mmcblk0p2\0" \
"rootdev=/dev/mmcblk0p3\0" \
"netdev=eth0\0" \
"hostname=dbm_soc1\0" \
"kernel_addr_r=0x10000000\0" \
"dfu_alt_info=mmc raw 0 3867148288\0" \
"update_filename=u-boot-with-spl.sfp\0" \
"update_sd_offset=0x800\0" \
"update_sd=" /* Update the SD firmware partition */ \
"if mmc rescan ; then " \
"if tftp ${update_filename} ; then " \
"setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
"setexpr fw_sz ${fw_sz} + 1 ; " \
"mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; " \
"fi ; " \
"fi\0" \
"fpga_filename=output_file.rbf\0" \
"load_fpga=" /* Load FPGA bitstream */ \
"if tftp ${fpga_filename} ; then " \
"fpga load 0 $loadaddr $filesize ; " \
"bridge enable ; " \
"fi\0" \
"addcons=" \
"setenv bootargs ${bootargs} " \
"console=${consdev},${baudrate}\0" \
"addip=" \
"setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:${hostname}:${netdev}:off\0" \
"addmisc=" \
"setenv bootargs ${bootargs} ${miscargs}\0" \
"addargs=run addcons addmisc\0" \
"mmcload=" \
"mmc rescan ; " \
"load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \
"netload=" \
"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
"miscargs=nohlt panic=1\0" \
"mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
"nfsargs=" \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath},v3,tcp\0" \
"mmc_mmc=" \
"run mmcload mmcargs addargs ; " \
"bootm ${kernel_addr_r}\0" \
"mmc_nfs=" \
"run mmcload nfsargs addip addargs ; " \
"bootm ${kernel_addr_r}\0" \
"net_mmc=" \
"run netload mmcargs addargs ; " \
"bootm ${kernel_addr_r}\0" \
"net_nfs=" \
"run netload nfsargs addip addargs ; " \
"bootm ${kernel_addr_r}\0" \
"try_bootscript=" \
"mmc rescan;" \
"if test -e mmc 0:2 ${bootscript} ; then " \
"if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \
"then ; " \
"echo Running bootscript... ; " \
"source ${kernel_addr_r} ; " \
"fi ; " \
"fi\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#endif /* __CONFIG_DEVBOARDS_DBM_SOC1_H__ */
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