The rsk7264 (also know as rsk2+sh7264) is an SH2A based board with 64MB NAND flash and 64MB SDRAM. It is very similar to the rsk7203 board. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master
Phil Edworthy
14 years ago
committed by
Nobuhiro Iwamatsu
parent
fa82f871c8
commit
7fbeb6422d
@ -0,0 +1,41 @@ |
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#ifndef _ASM_CPU_SH7264_H_ |
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#define _ASM_CPU_SH7264_H_ |
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|
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/* Cache */ |
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#define CCR1 0xFFFC1000 |
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#define CCR CCR1 |
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/* PFC */ |
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#define PACR 0xA4050100 |
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#define PBCR 0xA4050102 |
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#define PCCR 0xA4050104 |
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#define PETCR 0xA4050106 |
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/* Port Data Registers */ |
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#define PADR 0xA4050120 |
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#define PBDR 0xA4050122 |
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#define PCDR 0xA4050124 |
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/* BSC */ |
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/* SDRAM controller */ |
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/* SCIF */ |
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#define SCSMR_3 0xFFFE9800 |
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#define SCIF3_BASE SCSMR_3 |
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/* Timer(CMT) */ |
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#define CMSTR 0xFFFEC000 |
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#define CMCSR_0 0xFFFEC002 |
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#define CMCNT_0 0xFFFEC004 |
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#define CMCOR_0 0xFFFEC006 |
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#define CMCSR_1 0xFFFEC008 |
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#define CMCNT_1 0xFFFEC00A |
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#define CMCOR_1 0xFFFEC00C |
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/* On chip oscillator circuits */ |
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#define FRQCR 0xA415FF80 |
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#define WTCNT 0xA415FF84 |
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#define WTCSR 0xA415FF86 |
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#endif /* _ASM_CPU_SH7264_H_ */ |
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@ -0,0 +1,32 @@ |
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#
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# Copyright (C) 2011 Renesas Electronics Europe Ltd.
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#
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# This file is released under the terms of GPL v2 and any later version.
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# See the file COPYING in the root directory of the source tree for details.
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).o
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OBJS := rsk7264.o
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SOBJS := lowlevel_init.o
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LIB := $(addprefix $(obj),$(LIB))
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OBJS := $(addprefix $(obj),$(OBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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@ -0,0 +1,212 @@ |
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/* |
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* Copyright (C) 2011 Renesas Electronics Europe Ltd. |
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* Copyright (C) 2008 Renesas Solutions Corp. |
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* Copyright (C) 2008 Nobuhiro Iwamatsu |
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* |
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* Based on board/renesas/rsk7203/lowlevel_init.S |
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* |
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* This file is released under the terms of GPL v2 and any later version. |
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* See the file COPYING in the root directory of the source tree for details. |
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*/ |
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#include <config.h> |
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#include <version.h> |
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#include <asm/processor.h> |
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#include <asm/macro.h> |
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.global lowlevel_init
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.text |
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.align 2
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lowlevel_init: |
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/* Cache setting */ |
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write32 CCR1_A ,CCR1_D |
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/* io_set_cpg */ |
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write8 STBCR3_A, STBCR3_D |
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write8 STBCR4_A, STBCR4_D |
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write8 STBCR5_A, STBCR5_D |
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write8 STBCR6_A, STBCR6_D |
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write8 STBCR7_A, STBCR7_D |
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write8 STBCR8_A, STBCR8_D |
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/* ConfigurePortPins */ |
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/* Leaving LED1 ON for sanity test */ |
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write16 PJCR1_A, PJCR1_D1 |
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write16 PJCR2_A, PJCR2_D |
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write16 PJIOR0_A, PJIOR0_D1 |
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write16 PJDR0_A, PJDR0_D |
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write16 PJPR0_A, PJPR0_D |
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/* Configure EN_PIN & RS_PIN */ |
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write16 PGCR2_A, PGCR2_D |
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write16 PGIOR0_A, PGIOR0_D |
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/* Configure the port pins connected to UART */ |
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write16 PJCR1_A, PJCR1_D2 |
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write16 PJIOR0_A, PJIOR0_D2 |
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/* Configure Operating Frequency */ |
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write16 WTCSR_A, WTCSR_D0 |
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write16 WTCSR_A, WTCSR_D1 |
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write16 WTCNT_A, WTCNT_D |
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/* Control of RESBANK */ |
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write16 IBNR_A, IBNR_D |
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/* Enable SCIF3 module */ |
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write16 STBCR4_A, STBCR4_D |
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/* Set clock mode*/ |
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write16 FRQCR_A, FRQCR_D |
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/* Configure Bus And Memory */ |
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init_bsc_cs0: |
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pfc_settings: |
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write16 PCCR2_A, PCCR2_D |
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write16 PCCR1_A, PCCR1_D |
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write16 PCCR0_A, PCCR0_D |
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write16 PBCR0_A, PBCR0_D |
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write16 PBCR1_A, PBCR1_D |
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write16 PBCR2_A, PBCR2_D |
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write16 PBCR3_A, PBCR3_D |
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write16 PBCR4_A, PBCR4_D |
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write16 PBCR5_A, PBCR5_D |
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write16 PDCR0_A, PDCR0_D |
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write16 PDCR1_A, PDCR1_D |
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write16 PDCR2_A, PDCR2_D |
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write16 PDCR3_A, PDCR3_D |
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write32 CS0WCR_A, CS0WCR_D |
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write32 CS0BCR_A, CS0BCR_D |
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init_bsc_cs2: |
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write16 PJCR0_A, PJCR0_D |
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write32 CS2WCR_A, CS2WCR_D |
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init_sdram: |
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write32 CS3BCR_A, CS3BCR_D |
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write32 CS3WCR_A, CS3WCR_D |
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write32 SDCR_A, SDCR_D |
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write32 RTCOR_A, RTCOR_D |
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write32 RTCSR_A, RTCSR_D |
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/* wait 200us */ |
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mov.l REPEAT_D, r3 |
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mov #0, r2 |
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repeat0: |
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add #1, r2 |
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cmp/hs r3, r2 |
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bf repeat0 |
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nop |
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mov.l SDRAM_MODE, r1 |
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mov #0, r0 |
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mov.l r0, @r1
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nop |
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rts |
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.align 4
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CCR1_A: .long CCR1 |
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CCR1_D: .long 0x0000090B |
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FRQCR_A: .long 0xFFFE0010 |
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FRQCR_D: .word 0x1003 |
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.align 2
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STBCR3_A: .long 0xFFFE0408 |
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STBCR3_D: .long 0x00000002 |
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STBCR4_A: .long 0xFFFE040C |
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STBCR4_D: .word 0x0000 |
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.align 2
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STBCR5_A: .long 0xFFFE0410 |
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STBCR5_D: .long 0x00000010 |
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STBCR6_A: .long 0xFFFE0414 |
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STBCR6_D: .long 0x00000002 |
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STBCR7_A: .long 0xFFFE0418 |
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STBCR7_D: .long 0x0000002A |
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STBCR8_A: .long 0xFFFE041C |
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STBCR8_D: .long 0x0000007E |
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PJCR1_A: .long 0xFFFE390C |
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PJCR1_D1: .word 0x0000 |
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PJCR1_D2: .word 0x0022 |
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PJCR2_A: .long 0xFFFE390A |
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PJCR2_D: .word 0x0000 |
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.align 2
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PJIOR0_A: .long 0xFFFE3912 |
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PJIOR0_D1: .word 0x0FC0 |
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PJIOR0_D2: .word 0x0FE0 |
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PJDR0_A: .long 0xFFFE3916 |
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PJDR0_D: .word 0x0FBF |
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.align 2
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PJPR0_A: .long 0xFFFE391A |
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PJPR0_D: .long 0x00000FBF |
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PGCR2_A: .long 0xFFFE38CA |
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PGCR2_D: .word 0x0000 |
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.align 2
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PGIOR0_A: .long 0xFFFE38D2 |
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PGIOR0_D: .word 0x03F0 |
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.align 2
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WTCSR_A: .long 0xFFFE0000 |
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WTCSR_D0: .word 0x0000 |
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WTCSR_D1: .word 0x0000 |
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WTCNT_A: .long 0xFFFE0002 |
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WTCNT_D: .word 0x0000 |
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.align 2
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PCCR0_A: .long 0xFFFE384E |
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PDCR0_A: .long 0xFFFE386E |
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PDCR1_A: .long 0xFFFE386C |
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PDCR2_A: .long 0xFFFE386A |
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PDCR3_A: .long 0xFFFE3868 |
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PBCR0_A: .long 0xFFFE382E |
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PBCR1_A: .long 0xFFFE382C |
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PBCR2_A: .long 0xFFFE382A |
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PBCR3_A: .long 0xFFFE3828 |
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PBCR4_A: .long 0xFFFE3826 |
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PBCR5_A: .long 0xFFFE3824 |
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PCCR0_D: .word 0x1111 |
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PDCR0_D: .word 0x1111 |
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PDCR1_D: .word 0x1111 |
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PDCR2_D: .word 0x1111 |
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PDCR3_D: .word 0x1111 |
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PBCR0_D: .word 0x1110 |
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PBCR1_D: .word 0x1111 |
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PBCR2_D: .word 0x1111 |
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PBCR3_D: .word 0x1111 |
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PBCR4_D: .word 0x1111 |
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PBCR5_D: .word 0x0111 |
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.align 2
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CS0WCR_A: .long 0xFFFC0028 |
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CS0WCR_D: .long 0x00000B41 |
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CS0BCR_A: .long 0xFFFC0004 |
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CS0BCR_D: .long 0x10000400 |
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PJCR0_A: .long 0xFFFE390E |
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PJCR0_D: .word 0x0300 |
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.align 2
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CS2WCR_A: .long 0xFFFC0030 |
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CS2WCR_D: .long 0x00000B01 |
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PCCR2_A: .long 0xFFFE384A |
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PCCR2_D: .word 0x0001 |
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.align 2
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PCCR1_A: .long 0xFFFE384C |
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PCCR1_D: .word 0x1111 |
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.align 2
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CS3BCR_A: .long 0xFFFC0010 |
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CS3BCR_D: .long 0x00004400 |
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CS3WCR_A: .long 0xFFFC0034 |
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CS3WCR_D: .long 0x0000288A |
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SDCR_A: .long 0xFFFC004C |
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SDCR_D: .long 0x00000812 |
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RTCOR_A: .long 0xFFFC0058 |
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RTCOR_D: .long 0xA55A0046 |
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RTCSR_A: .long 0xFFFC0050 |
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RTCSR_D: .long 0xA55A0010 |
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IBNR_A: .long 0xFFFE080E |
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IBNR_D: .word 0x0000 |
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.align 2
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SDRAM_MODE: .long 0xFFFC5040 |
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REPEAT_D: .long 0x00000085 |
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@ -0,0 +1,72 @@ |
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/*
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* Copyright (C) 2011 Renesas Electronics Europe Ltd. |
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* Copyright (C) 2008 Renesas Solutions Corp. |
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* Copyright (C) 2008 Nobuhiro Iwamatsu |
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* |
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* Based on u-boot/board/rsk7264/rsk7203.c |
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* |
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* This file is released under the terms of GPL v2 and any later version. |
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* See the file COPYING in the root directory of the source tree for details. |
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*/ |
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#include <common.h> |
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#include <net.h> |
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#include <netdev.h> |
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#include <asm/io.h> |
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#include <asm/processor.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int checkboard(void) |
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{ |
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puts("BOARD: Renesas Technology RSK7264\n"); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; |
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gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; |
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printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); |
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return 0; |
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} |
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void led_set_state(unsigned short value) |
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{ |
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} |
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/*
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* The RSK board has the SMSC89218 wired up 'incorrectly'. |
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* Byte-swapping is necessary, and so poor performance is inevitable. |
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* This problem cannot evade by the swap function of CHIP, this can |
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* evade by software Byte-swapping. |
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* And this has problem by FIFO access only. pkt_data_pull/pkt_data_push |
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* functions necessary to solve this problem. |
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*/ |
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u32 pkt_data_pull(struct eth_device *dev, u32 addr) |
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{ |
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volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); |
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return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
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| swab16(*(addr_16 + 1)); |
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} |
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void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) |
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{ |
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addr += dev->iobase; |
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*(volatile u16 *)(addr + 2) = swab16((u16)val); |
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*(volatile u16 *)(addr) = swab16((u16)(val >> 16)); |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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#ifdef CONFIG_SMC911X |
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
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#endif |
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return rc; |
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} |
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@ -0,0 +1,99 @@ |
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/*
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* Configuation settings for the Renesas Technology RSK 7264 |
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* |
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* Copyright (C) 2011 Renesas Electronics Europe Ltd. |
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* Copyright (C) 2008 Nobuhiro Iwamatsu |
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* Copyright (C) 2008 Renesas Solutions Corp. |
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* |
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* This file is released under the terms of GPL v2 and any later version. |
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* See the file COPYING in the root directory of the source tree for details. |
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*/ |
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#ifndef __RSK7264_H |
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#define __RSK7264_H |
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#undef DEBUG |
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#define CONFIG_SH 1 |
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#define CONFIG_SH2 1 |
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#define CONFIG_SH2A 1 |
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#define CONFIG_CPU_SH7264 1 |
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#define CONFIG_RSK7264 1 |
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#define CONFIG_CMD_FLASH |
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#define CONFIG_CMD_NET |
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#define CONFIG_CMD_NFS |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_SAVEENV |
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#define CONFIG_CMD_SDRAM |
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#define CONFIG_CMD_MEMORY |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_BOOTARGS "console=ttySC3,115200" |
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#define CONFIG_BOOTDELAY 3 |
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#define CONFIG_LOADADDR 0x0C100000 /* RSK7264_SDRAM_BASE + 1MB */ |
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#define CONFIG_VERSION_VARIABLE |
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#undef CONFIG_SHOW_BOOT_PROGRESS |
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/* MEMORY */ |
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#define RSK7264_SDRAM_BASE 0x0C000000 |
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#define RSK7264_FLASH_BASE_1 0x20000000 /* Non cache */ |
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#define CONFIG_SYS_TEXT_BASE 0x0C1C0000 |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
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#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ |
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#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ |
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#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ |
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/* Buffer size for Boot Arguments passed to kernel */ |
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#define CONFIG_SYS_BARGSIZE 512 |
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/* List of legal baudrate settings for this board */ |
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } |
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/* SCIF */ |
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#define CONFIG_SCIF_CONSOLE 1 |
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#define CONFIG_CONS_SCIF3 1 |
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#define CONFIG_SYS_MEMTEST_START RSK7264_SDRAM_BASE |
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024)) |
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#define CONFIG_SYS_SDRAM_BASE RSK7264_SDRAM_BASE |
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#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) |
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024) |
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#define CONFIG_SYS_MONITOR_BASE RSK7264_FLASH_BASE_1 |
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
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/* FLASH */ |
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#define CONFIG_FLASH_CFI_DRIVER |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
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#undef CONFIG_SYS_FLASH_QUIET_TEST |
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
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#define CONFIG_SYS_FLASH_BASE RSK7264_FLASH_BASE_1 |
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
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#define CONFIG_SYS_MAX_FLASH_SECT 512 |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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#define CONFIG_ENV_IS_IN_FLASH |
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#define CONFIG_ENV_SECT_SIZE (128 * 1024) |
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 |
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/* Board Clock */ |
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#define CONFIG_SYS_CLK_FREQ 33333333 |
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#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ |
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#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) |
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/* Network interface */ |
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#define CONFIG_NET_MULTI |
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#define CONFIG_SMC911X |
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#define CONFIG_SMC911X_16_BIT |
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#define CONFIG_SMC911X_BASE (0x28000000) |
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#endif /* __RSK7264_H */ |
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