T4240 SoC has been available for a long time. Emulator support is no longer needed. Signed-off-by: York Sun <yorksun@freescale.com>master
York Sun
10 years ago
parent
e1bfd1c6b7
commit
7fc63cca61
@ -1,4 +0,0 @@ |
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" |
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CONFIG_PPC=y |
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CONFIG_MPC85xx=y |
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CONFIG_TARGET_T4240EMU=y |
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@ -1,181 +0,0 @@ |
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/*
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* T4240 EMU board configuration file |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#define CONFIG_T4240EMU |
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#define CONFIG_PHYS_64BIT |
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#define CONFIG_SYS_NO_FLASH 1 |
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#define CONFIG_SYS_FSL_DDR_EMU 1 |
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#define CONFIG_SYS_FSL_NO_QIXIS 1 |
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#define CONFIG_SYS_FSL_NO_SERDES 1 |
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#include "t4qds.h" |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_CMD_CACHE_FLUSH |
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#define CONFIG_ENV_IS_NOWHERE |
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#define CONFIG_ENV_SIZE 0x2000 |
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#define CONFIG_SYS_CLK_FREQ 100000000 |
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#define CONFIG_DDR_CLK_FREQ 133333333 |
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#define CONFIG_FSL_TBCLK_EXTRA_DIV 100 |
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/*
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* DDR Setup |
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*/ |
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#define CONFIG_SYS_SPD_BUS_NUM 1 |
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#define SPD_EEPROM_ADDRESS1 0x51 |
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#define SPD_EEPROM_ADDRESS2 0x52 |
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#define SPD_EEPROM_ADDRESS3 0x53 |
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#define SPD_EEPROM_ADDRESS4 0x54 |
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#define SPD_EEPROM_ADDRESS5 0x55 |
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#define SPD_EEPROM_ADDRESS6 0x56 |
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#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ |
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#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
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/*
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* IFC Definitions |
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*/ |
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#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) |
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
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/* NOR Flash Timing Params */ |
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#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ |
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+ 0x8000000) | \
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CSPR_PORT_SIZE_32 | \
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CSPR_MSEL_NOR | \
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CSPR_V) |
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#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0) |
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ |
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FTIM0_NOR_TEADC(0x1) | \
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FTIM0_NOR_TEAHC(0x1)) |
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ |
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FTIM1_NOR_TRAD_NOR(0x1)) |
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ |
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FTIM2_NOR_TCH(0x0) | \
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FTIM2_NOR_TWP(0x1)) |
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#define CONFIG_SYS_NOR_FTIM3 0x04000000 |
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#define CONFIG_SYS_IFC_CCR 0x01000000 |
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR |
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
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/* I2C */ |
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#define CONFIG_SYS_FSL_I2C_SPEED 4000000 /* faster speed for emulator */ |
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#define CONFIG_SYS_FSL_I2C2_SPEED 4000000 |
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/* Qman/Bman */ |
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#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
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#define CONFIG_SYS_BMAN_NUM_PORTALS 50 |
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#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
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#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
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#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
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#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
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#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 |
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#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE |
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#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) |
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#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ |
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CONFIG_SYS_BMAN_CENA_SIZE) |
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#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) |
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#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 |
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#define CONFIG_SYS_QMAN_NUM_PORTALS 50 |
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#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
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#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
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#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
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#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
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#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 |
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#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE |
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#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) |
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#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ |
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CONFIG_SYS_QMAN_CENA_SIZE) |
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#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) |
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#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 |
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#define CONFIG_SYS_DPAA_FMAN |
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#define CONFIG_SYS_DPAA_PME |
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#define CONFIG_SYS_PMAN |
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#define CONFIG_SYS_DPAA_DCE |
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#define CONFIG_SYS_DPAA_RMAN |
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#define CONFIG_SYS_INTERLAKEN |
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
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#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
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#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
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#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
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#define CONFIG_BOOTDELAY 0 |
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/*
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* T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be |
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* 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way |
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* interleaving. It can be cacheline, page, bank, superbank. |
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* See doc/README.fsl-ddr for details. |
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*/ |
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#ifdef CONFIG_PPC_T4240 |
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#define CTRL_INTLV_PREFERED 3way_4KB |
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#else |
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#define CTRL_INTLV_PREFERED cacheline |
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#endif |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"hwconfig=fsl_ddr:" \
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"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
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"bank_intlv=auto;" \
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=t4240emu/ramdisk.uboot\0" \
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"fdtaddr=c00000\0" \
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"fdtfile=t4240emu/t4240emu.dtb\0" \
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"bdev=sda3\0" |
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/*
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* For emulation this causes u-boot to jump to the start of the proof point |
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* app code automatically |
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*/ |
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#define CONFIG_PROOF_POINTS \ |
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"setenv bootargs root=/dev/$bdev rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"cpu 1 release 0x29000000 - - -;" \
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"cpu 2 release 0x29000000 - - -;" \
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"cpu 3 release 0x29000000 - - -;" \
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"cpu 4 release 0x29000000 - - -;" \
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"cpu 5 release 0x29000000 - - -;" \
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"cpu 6 release 0x29000000 - - -;" \
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"cpu 7 release 0x29000000 - - -;" \
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"go 0x29000000" |
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#define CONFIG_HVBOOT \ |
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"setenv bootargs config-addr=0x60000000; " \
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"bootm 0x01000000 - 0x00f00000" |
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#define CONFIG_LINUX \ |
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"errata;" \
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"setenv othbootargs ignore_loglevel;" \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"setenv ramdiskaddr 0x02000000;" \
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"setenv fdtaddr 0x00c00000;" \
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"setenv loadaddr 0x1000000;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr" |
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#define CONFIG_BOOTCOMMAND CONFIG_LINUX |
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#endif /* __CONFIG_H */ |
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