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@ -10,58 +10,27 @@ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <pci.h> |
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#include <asm/io.h> |
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#include <asm/pci.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, |
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struct pci_config_table *table) |
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{ |
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u8 secondary; |
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hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); |
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hose->last_busno = max(hose->last_busno, (int)secondary); |
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pci_hose_scan_bus(hose, secondary); |
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} |
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static struct pci_config_table pci_coreboot_config_table[] = { |
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/* vendor, device, class, bus, dev, func */ |
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, |
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, |
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{} |
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static const struct dm_pci_ops pci_x86_ops = { |
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.read_config = pci_x86_read_config, |
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.write_config = pci_x86_write_config, |
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}; |
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void board_pci_setup_hose(struct pci_controller *hose) |
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{ |
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hose->config_table = pci_coreboot_config_table; |
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hose->first_busno = 0; |
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hose->last_busno = 0; |
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/* PCI memory space */ |
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pci_set_region(hose->regions + 0, |
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CONFIG_PCI_MEM_BUS, |
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CONFIG_PCI_MEM_PHYS, |
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CONFIG_PCI_MEM_SIZE, |
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PCI_REGION_MEM); |
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/* PCI IO space */ |
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pci_set_region(hose->regions + 1, |
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CONFIG_PCI_IO_BUS, |
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CONFIG_PCI_IO_PHYS, |
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CONFIG_PCI_IO_SIZE, |
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PCI_REGION_IO); |
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pci_set_region(hose->regions + 2, |
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CONFIG_PCI_PREF_BUS, |
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CONFIG_PCI_PREF_PHYS, |
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CONFIG_PCI_PREF_SIZE, |
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PCI_REGION_PREFETCH); |
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pci_set_region(hose->regions + 3, |
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0, |
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0, |
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gd->ram_size, |
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); |
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static const struct udevice_id pci_x86_ids[] = { |
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{ .compatible = "pci-x86" }, |
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{ } |
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}; |
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hose->region_count = 4; |
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} |
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U_BOOT_DRIVER(pci_x86_drv) = { |
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.name = "pci_x86", |
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.id = UCLASS_PCI, |
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.of_match = pci_x86_ids, |
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.ops = &pci_x86_ops, |
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}; |
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